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authorSumanto Kar2024-11-21 22:09:07 +0530
committerGitHub2024-11-21 22:09:07 +0530
commitc7f8a75e51d3c79aaa994b25849bcb358543f12c (patch)
treee0164ce8ed66b4b6d26fb522b37daed7d3d14dde /library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch
parent5aa4943922ff5af9bbb840782aaf26e72de40576 (diff)
parent8e6fb624fda240239f9bfff67b40c28fba44e744 (diff)
downloadeSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.tar.gz
eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.tar.bz2
eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.zip
Merge pull request #289 from Eyantra698Sumanto/master
Subcircuit Files of ICs(Contributor: Varad Patil)
Diffstat (limited to 'library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch')
-rw-r--r--library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch1294
1 files changed, 1294 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch
new file mode 100644
index 00000000..67998706
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch
@@ -0,0 +1,1294 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74ALS280-cache
+EELAYER 25 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
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+$Comp
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+L 3_and X2
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+F 0 "X2" H 12900 10400 60 0000 C CNN
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+$EndComp
+Wire Wire Line
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+L d_nand U55
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+$EndComp
+$Comp
+L d_nand U56
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+$EndComp
+$Comp
+L d_nand U57
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+$EndComp
+Wire Wire Line
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+L 4_and X4
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+P 14250 11650
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+$EndComp
+$Comp
+L d_inverter U59
+U 1 1 666F0936
+P 13650 10750
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+ 1 13650 10750
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+$EndComp
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+L d_inverter U26
+U 1 1 666F094E
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+$EndComp
+$Comp
+L d_inverter U49
+U 1 1 666F0954
+P 11850 11100
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+$EndComp
+Wire Wire Line
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+L d_inverter U25
+U 1 1 666F095B
+P 9200 11100
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+$EndComp
+$Comp
+L d_inverter U50
+U 1 1 666F0961
+P 11850 11800
+F 0 "U50" H 11850 11700 60 0000 C CNN
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+Wire Wire Line
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+L d_inverter U27
+U 1 1 666F0968
+P 9200 12550
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+$EndComp
+$Comp
+L d_inverter U51
+U 1 1 666F096E
+P 11900 12550
+F 0 "U51" H 11900 12450 60 0000 C CNN
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+$EndComp
+Wire Wire Line
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+L PORT U1
+U 1 1 666DBC06
+P 6150 4700
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+$EndComp
+$Comp
+L PORT U1
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+ 2 6150 4800
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+$EndComp
+$Comp
+L PORT U1
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+$EndComp
+$Comp
+L PORT U1
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+$Comp
+L PORT U1
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+$EndComp
+$Comp
+L PORT U1
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+ 6 6200 8400
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+$EndComp
+$Comp
+L PORT U1
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+F 3 "" H 6300 11700 60 0000 C CNN
+ 7 6300 11700
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+$Comp
+L PORT U1
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+$EndComp
+$Comp
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+F 3 "" H 6300 11900 60 0000 C CNN
+ 9 6300 11900
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+$EndComp
+$Comp
+L PORT U1
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+ 10 20950 7950
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+$Comp
+L PORT U1
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+F 3 "" H 20950 8050 60 0000 C CNN
+ 11 20950 8050
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC