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| author | Sumanto Kar | 2024-11-21 22:09:07 +0530 |
|---|---|---|
| committer | GitHub | 2024-11-21 22:09:07 +0530 |
| commit | c7f8a75e51d3c79aaa994b25849bcb358543f12c (patch) | |
| tree | e0164ce8ed66b4b6d26fb522b37daed7d3d14dde /library | |
| parent | 5aa4943922ff5af9bbb840782aaf26e72de40576 (diff) | |
| parent | 8e6fb624fda240239f9bfff67b40c28fba44e744 (diff) | |
| download | eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.tar.gz eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.tar.bz2 eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.zip | |
Merge pull request #289 from Eyantra698Sumanto/master
Subcircuit Files of ICs(Contributor: Varad Patil)
Diffstat (limited to 'library')
171 files changed, 18827 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286-cache.lib b/library/SubcircuitLibrary/74ACT11286/74ACT11286-cache.lib new file mode 100644 index 00000000..001e0ac1 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286-cache.lib @@ -0,0 +1,110 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xnor +# +DEF d_xnor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xnor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 43 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir b/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir new file mode 100644 index 00000000..5af79599 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir @@ -0,0 +1,31 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74ACT11286\74ACT11286.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/15/24 21:23:24 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U17 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U17-Pad3_ d_xnor +U21 Net-_U1-Pad3_ Net-_U21-Pad2_ d_inverter +U25 Net-_U17-Pad3_ Net-_U21-Pad2_ Net-_U25-Pad3_ d_xnor +U18 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U18-Pad3_ d_xnor +U22 Net-_U1-Pad6_ Net-_U22-Pad2_ d_inverter +U26 Net-_U18-Pad3_ Net-_U22-Pad2_ Net-_U26-Pad3_ d_xnor +U19 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U19-Pad3_ d_xnor +U23 Net-_U1-Pad9_ Net-_U23-Pad2_ d_inverter +U27 Net-_U19-Pad3_ Net-_U23-Pad2_ Net-_U27-Pad3_ d_xnor +U29 Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U29-Pad3_ d_xnor +U30 Net-_U27-Pad3_ Net-_U30-Pad2_ d_inverter +U31 Net-_U29-Pad3_ Net-_U30-Pad2_ Net-_U24-Pad1_ d_xnor +U32 Net-_U24-Pad1_ Net-_U32-Pad2_ d_inverter +U33 Net-_U32-Pad2_ Net-_U28-Pad2_ Net-_U33-Pad3_ d_xnor +U35 Net-_U33-Pad3_ Net-_U34-Pad2_ Net-_U1-Pad12_ d_nand +U34 Net-_U20-Pad2_ Net-_U34-Pad2_ d_inverter +U28 Net-_U1-Pad10_ Net-_U28-Pad2_ d_inverter +U20 Net-_U1-Pad11_ Net-_U20-Pad2_ d_inverter +U24 Net-_U24-Pad1_ Net-_U20-Pad2_ Net-_U16-Pad1_ d_tristate +U16 Net-_U16-Pad1_ Net-_U1-Pad10_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT + +.end diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir.out b/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir.out new file mode 100644 index 00000000..25df9f76 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.cir.out @@ -0,0 +1,92 @@ +* c:\fossee\esim\library\subcircuitlibrary\74act11286\74act11286.cir + +* u17 net-_u1-pad1_ net-_u1-pad2_ net-_u17-pad3_ d_xnor +* u21 net-_u1-pad3_ net-_u21-pad2_ d_inverter +* u25 net-_u17-pad3_ net-_u21-pad2_ net-_u25-pad3_ d_xnor +* u18 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad3_ d_xnor +* u22 net-_u1-pad6_ net-_u22-pad2_ d_inverter +* u26 net-_u18-pad3_ net-_u22-pad2_ net-_u26-pad3_ d_xnor +* u19 net-_u1-pad7_ net-_u1-pad8_ net-_u19-pad3_ d_xnor +* u23 net-_u1-pad9_ net-_u23-pad2_ d_inverter +* u27 net-_u19-pad3_ net-_u23-pad2_ net-_u27-pad3_ d_xnor +* u29 net-_u25-pad3_ net-_u26-pad3_ net-_u29-pad3_ d_xnor +* u30 net-_u27-pad3_ net-_u30-pad2_ d_inverter +* u31 net-_u29-pad3_ net-_u30-pad2_ net-_u24-pad1_ d_xnor +* u32 net-_u24-pad1_ net-_u32-pad2_ d_inverter +* u33 net-_u32-pad2_ net-_u28-pad2_ net-_u33-pad3_ d_xnor +* u35 net-_u33-pad3_ net-_u34-pad2_ net-_u1-pad12_ d_nand +* u34 net-_u20-pad2_ net-_u34-pad2_ d_inverter +* u28 net-_u1-pad10_ net-_u28-pad2_ d_inverter +* u20 net-_u1-pad11_ net-_u20-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u20-pad2_ net-_u16-pad1_ d_tristate +* u16 net-_u16-pad1_ net-_u1-pad10_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u17-pad3_ u17 +a2 net-_u1-pad3_ net-_u21-pad2_ u21 +a3 [net-_u17-pad3_ net-_u21-pad2_ ] net-_u25-pad3_ u25 +a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad3_ u18 +a5 net-_u1-pad6_ net-_u22-pad2_ u22 +a6 [net-_u18-pad3_ net-_u22-pad2_ ] net-_u26-pad3_ u26 +a7 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u19-pad3_ u19 +a8 net-_u1-pad9_ net-_u23-pad2_ u23 +a9 [net-_u19-pad3_ net-_u23-pad2_ ] net-_u27-pad3_ u27 +a10 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u29-pad3_ u29 +a11 net-_u27-pad3_ net-_u30-pad2_ u30 +a12 [net-_u29-pad3_ net-_u30-pad2_ ] net-_u24-pad1_ u31 +a13 net-_u24-pad1_ net-_u32-pad2_ u32 +a14 [net-_u32-pad2_ net-_u28-pad2_ ] net-_u33-pad3_ u33 +a15 [net-_u33-pad3_ net-_u34-pad2_ ] net-_u1-pad12_ u35 +a16 net-_u20-pad2_ net-_u34-pad2_ u34 +a17 net-_u1-pad10_ net-_u28-pad2_ u28 +a18 net-_u1-pad11_ net-_u20-pad2_ u20 +a19 net-_u24-pad1_ net-_u20-pad2_ net-_u16-pad1_ u24 +a20 net-_u16-pad1_ net-_u1-pad10_ u16 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u17 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u27 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u29 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u31 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u33 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.pro b/library/SubcircuitLibrary/74ACT11286/74ACT11286.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.proj b/library/SubcircuitLibrary/74ACT11286/74ACT11286.proj new file mode 100644 index 00000000..ab6299e8 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.proj @@ -0,0 +1 @@ +schematicFile 74ACT11286.sch diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.sch b/library/SubcircuitLibrary/74ACT11286/74ACT11286.sch new file mode 100644 index 00000000..2cf134b4 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.sch @@ -0,0 +1,505 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74ACT11286-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xnor U17 +U 1 1 666D7714 +P 15100 8600 +F 0 "U17" H 15100 8600 60 0000 C CNN +F 1 "d_xnor" H 15150 8700 47 0000 C CNN +F 2 "" H 15100 8600 60 0000 C CNN +F 3 "" H 15100 8600 60 0000 C CNN + 1 15100 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 666D7745 +P 15250 8850 +F 0 "U21" H 15250 8750 60 0000 C CNN +F 1 "d_inverter" H 15250 9000 60 0000 C CNN +F 2 "" H 15300 8800 60 0000 C CNN +F 3 "" H 15300 8800 60 0000 C CNN + 1 15250 8850 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U25 +U 1 1 666D7764 +P 16000 8750 +F 0 "U25" H 16000 8750 60 0000 C CNN +F 1 "d_xnor" H 16050 8850 47 0000 C CNN +F 2 "" H 16000 8750 60 0000 C CNN +F 3 "" H 16000 8750 60 0000 C CNN + 1 16000 8750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15550 8650 15550 8550 +Wire Wire Line + 15550 8750 15550 8850 +Wire Wire Line + 14450 8500 14650 8500 +Wire Wire Line + 14450 8600 14650 8600 +Wire Wire Line + 14450 8850 14950 8850 +$Comp +L d_xnor U18 +U 1 1 666D78DF +P 15100 9550 +F 0 "U18" H 15100 9550 60 0000 C CNN +F 1 "d_xnor" H 15150 9650 47 0000 C CNN +F 2 "" H 15100 9550 60 0000 C CNN +F 3 "" H 15100 9550 60 0000 C CNN + 1 15100 9550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 666D78E5 +P 15250 9800 +F 0 "U22" H 15250 9700 60 0000 C CNN +F 1 "d_inverter" H 15250 9950 60 0000 C CNN +F 2 "" H 15300 9750 60 0000 C CNN +F 3 "" H 15300 9750 60 0000 C CNN + 1 15250 9800 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U26 +U 1 1 666D78EB +P 16000 9700 +F 0 "U26" H 16000 9700 60 0000 C CNN +F 1 "d_xnor" H 16050 9800 47 0000 C CNN +F 2 "" H 16000 9700 60 0000 C CNN +F 3 "" H 16000 9700 60 0000 C CNN + 1 16000 9700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15550 9600 15550 9500 +Wire Wire Line + 15550 9700 15550 9800 +Wire Wire Line + 14450 9450 14650 9450 +Wire Wire Line + 14450 9550 14650 9550 +Wire Wire Line + 14450 9800 14950 9800 +$Comp +L d_xnor U19 +U 1 1 666D799B +P 15150 10450 +F 0 "U19" H 15150 10450 60 0000 C CNN +F 1 "d_xnor" H 15200 10550 47 0000 C CNN +F 2 "" H 15150 10450 60 0000 C CNN +F 3 "" H 15150 10450 60 0000 C CNN + 1 15150 10450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 666D79A1 +P 15300 10700 +F 0 "U23" H 15300 10600 60 0000 C CNN +F 1 "d_inverter" H 15300 10850 60 0000 C CNN +F 2 "" H 15350 10650 60 0000 C CNN +F 3 "" H 15350 10650 60 0000 C CNN + 1 15300 10700 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U27 +U 1 1 666D79A7 +P 16050 10600 +F 0 "U27" H 16050 10600 60 0000 C CNN +F 1 "d_xnor" H 16100 10700 47 0000 C CNN +F 2 "" H 16050 10600 60 0000 C CNN +F 3 "" H 16050 10600 60 0000 C CNN + 1 16050 10600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15600 10500 15600 10400 +Wire Wire Line + 15600 10600 15600 10700 +Wire Wire Line + 14500 10350 14700 10350 +Wire Wire Line + 14500 10450 14700 10450 +Wire Wire Line + 14500 10700 15000 10700 +$Comp +L d_xnor U29 +U 1 1 666D7CAF +P 17400 9600 +F 0 "U29" H 17400 9600 60 0000 C CNN +F 1 "d_xnor" H 17450 9700 47 0000 C CNN +F 2 "" H 17400 9600 60 0000 C CNN +F 3 "" H 17400 9600 60 0000 C CNN + 1 17400 9600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 666D7CB5 +P 17550 9850 +F 0 "U30" H 17550 9750 60 0000 C CNN +F 1 "d_inverter" H 17550 10000 60 0000 C CNN +F 2 "" H 17600 9800 60 0000 C CNN +F 3 "" H 17600 9800 60 0000 C CNN + 1 17550 9850 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U31 +U 1 1 666D7CBB +P 18300 9750 +F 0 "U31" H 18300 9750 60 0000 C CNN +F 1 "d_xnor" H 18350 9850 47 0000 C CNN +F 2 "" H 18300 9750 60 0000 C CNN +F 3 "" H 18300 9750 60 0000 C CNN + 1 18300 9750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17850 9650 17850 9550 +Wire Wire Line + 17850 9750 17850 9850 +Wire Wire Line + 16750 9500 16950 9500 +Wire Wire Line + 16750 9600 16950 9600 +Wire Wire Line + 16750 9850 17250 9850 +$Comp +L d_inverter U32 +U 1 1 666D7CDE +P 19200 9700 +F 0 "U32" H 19200 9600 60 0000 C CNN +F 1 "d_inverter" H 19200 9850 60 0000 C CNN +F 2 "" H 19250 9650 60 0000 C CNN +F 3 "" H 19250 9650 60 0000 C CNN + 1 19200 9700 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U33 +U 1 1 666D7D3F +P 20050 9800 +F 0 "U33" H 20050 9800 60 0000 C CNN +F 1 "d_xnor" H 20100 9900 47 0000 C CNN +F 2 "" H 20050 9800 60 0000 C CNN +F 3 "" H 20050 9800 60 0000 C CNN + 1 20050 9800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U35 +U 1 1 666D7DCD +P 21150 9850 +F 0 "U35" H 21150 9850 60 0000 C CNN +F 1 "d_nand" H 21200 9950 60 0000 C CNN +F 2 "" H 21150 9850 60 0000 C CNN +F 3 "" H 21150 9850 60 0000 C CNN + 1 21150 9850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 666D7E1D +P 20650 10400 +F 0 "U34" H 20650 10300 60 0000 C CNN +F 1 "d_inverter" H 20650 10550 60 0000 C CNN +F 2 "" H 20700 10350 60 0000 C CNN +F 3 "" H 20700 10350 60 0000 C CNN + 1 20650 10400 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U28 +U 1 1 666D7F1E +P 16400 11550 +F 0 "U28" H 16400 11450 60 0000 C CNN +F 1 "d_inverter" H 16400 11700 60 0000 C CNN +F 2 "" H 16450 11500 60 0000 C CNN +F 3 "" H 16450 11500 60 0000 C CNN + 1 16400 11550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 666D7FCA +P 15200 11750 +F 0 "U20" H 15200 11650 60 0000 C CNN +F 1 "d_inverter" H 15200 11900 60 0000 C CNN +F 2 "" H 15250 11700 60 0000 C CNN +F 3 "" H 15250 11700 60 0000 C CNN + 1 15200 11750 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U24 +U 1 1 666D806E +P 15750 11500 +F 0 "U24" H 15500 11750 60 0000 C CNN +F 1 "d_tristate" H 15550 11950 60 0000 C CNN +F 2 "" H 15650 11850 60 0000 C CNN +F 3 "" H 15650 11850 60 0000 C CNN + 1 15750 11500 + -1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 666D80CE +P 14900 11150 +F 0 "U16" H 14900 11050 60 0000 C CNN +F 1 "d_inverter" H 14900 11300 60 0000 C CNN +F 2 "" H 14950 11100 60 0000 C CNN +F 3 "" H 14950 11100 60 0000 C CNN + 1 14900 11150 + -1 0 0 -1 +$EndComp +Wire Wire Line + 15800 11450 15800 11750 +Wire Wire Line + 15500 11750 20650 11750 +Wire Wire Line + 16100 11550 14600 11550 +Wire Wire Line + 14600 11550 14600 11150 +Wire Wire Line + 14600 11150 14500 11150 +Wire Wire Line + 14900 11750 14500 11750 +Wire Wire Line + 16350 11150 18850 11150 +Wire Wire Line + 18850 11150 18850 9700 +Wire Wire Line + 18750 9700 18900 9700 +Connection ~ 18850 9700 +Wire Wire Line + 19600 9700 19500 9700 +Wire Wire Line + 19600 9800 19600 11550 +Wire Wire Line + 19600 11550 16700 11550 +Wire Wire Line + 20650 11750 20650 10700 +Connection ~ 15800 11750 +Wire Wire Line + 20650 10100 20650 9850 +Wire Wire Line + 20650 9850 20700 9850 +Wire Wire Line + 20700 9750 20500 9750 +Wire Wire Line + 16750 9850 16750 10550 +Wire Wire Line + 16750 10550 16500 10550 +Wire Wire Line + 16750 9600 16750 9650 +Wire Wire Line + 16750 9650 16450 9650 +Wire Wire Line + 16750 9500 16750 8700 +Wire Wire Line + 16750 8700 16450 8700 +Wire Wire Line + 14500 11150 14500 11350 +Wire Wire Line + 14500 11750 14500 11450 +Wire Wire Line + 14500 10700 14500 10550 +Wire Wire Line + 14450 9800 14450 9650 +Wire Wire Line + 14450 8850 14450 8700 +$Comp +L PORT U1 +U 1 1 666DBDFE +P 14200 8500 +F 0 "U1" H 14250 8600 30 0000 C CNN +F 1 "PORT" H 14200 8500 30 0000 C CNN +F 2 "" H 14200 8500 60 0000 C CNN +F 3 "" H 14200 8500 60 0000 C CNN + 1 14200 8500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 666DBE49 +P 14200 8600 +F 0 "U1" H 14250 8700 30 0000 C CNN +F 1 "PORT" H 14200 8600 30 0000 C CNN +F 2 "" H 14200 8600 60 0000 C CNN +F 3 "" H 14200 8600 60 0000 C CNN + 2 14200 8600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 666DBE8A +P 14200 8700 +F 0 "U1" H 14250 8800 30 0000 C CNN +F 1 "PORT" H 14200 8700 30 0000 C CNN +F 2 "" H 14200 8700 60 0000 C CNN +F 3 "" H 14200 8700 60 0000 C CNN + 3 14200 8700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 666DBFCA +P 14200 9450 +F 0 "U1" H 14250 9550 30 0000 C CNN +F 1 "PORT" H 14200 9450 30 0000 C CNN +F 2 "" H 14200 9450 60 0000 C CNN +F 3 "" H 14200 9450 60 0000 C CNN + 4 14200 9450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 666DC00F +P 14200 9550 +F 0 "U1" H 14250 9650 30 0000 C CNN +F 1 "PORT" H 14200 9550 30 0000 C CNN +F 2 "" H 14200 9550 60 0000 C CNN +F 3 "" H 14200 9550 60 0000 C CNN + 5 14200 9550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 666DC056 +P 14200 9650 +F 0 "U1" H 14250 9750 30 0000 C CNN +F 1 "PORT" H 14200 9650 30 0000 C CNN +F 2 "" H 14200 9650 60 0000 C CNN +F 3 "" H 14200 9650 60 0000 C CNN + 6 14200 9650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 666DC1A3 +P 14250 10350 +F 0 "U1" H 14300 10450 30 0000 C CNN +F 1 "PORT" H 14250 10350 30 0000 C CNN +F 2 "" H 14250 10350 60 0000 C CNN +F 3 "" H 14250 10350 60 0000 C CNN + 7 14250 10350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 666DC1EE +P 14250 10450 +F 0 "U1" H 14300 10550 30 0000 C CNN +F 1 "PORT" H 14250 10450 30 0000 C CNN +F 2 "" H 14250 10450 60 0000 C CNN +F 3 "" H 14250 10450 60 0000 C CNN + 8 14250 10450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 666DC23B +P 14250 10550 +F 0 "U1" H 14300 10650 30 0000 C CNN +F 1 "PORT" H 14250 10550 30 0000 C CNN +F 2 "" H 14250 10550 60 0000 C CNN +F 3 "" H 14250 10550 60 0000 C CNN + 9 14250 10550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 666DC28A +P 14250 11350 +F 0 "U1" H 14300 11450 30 0000 C CNN +F 1 "PORT" H 14250 11350 30 0000 C CNN +F 2 "" H 14250 11350 60 0000 C CNN +F 3 "" H 14250 11350 60 0000 C CNN + 10 14250 11350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 666DC2DD +P 14250 11450 +F 0 "U1" H 14300 11550 30 0000 C CNN +F 1 "PORT" H 14250 11450 30 0000 C CNN +F 2 "" H 14250 11450 60 0000 C CNN +F 3 "" H 14250 11450 60 0000 C CNN + 11 14250 11450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 666DC4E2 +P 21850 9800 +F 0 "U1" H 21900 9900 30 0000 C CNN +F 1 "PORT" H 21850 9800 30 0000 C CNN +F 2 "" H 21850 9800 60 0000 C CNN +F 3 "" H 21850 9800 60 0000 C CNN + 12 21850 9800 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286.sub b/library/SubcircuitLibrary/74ACT11286/74ACT11286.sub new file mode 100644 index 00000000..bcf12808 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286.sub @@ -0,0 +1,86 @@ +* Subcircuit 74ACT11286 +.subckt 74ACT11286 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ +* c:\fossee\esim\library\subcircuitlibrary\74act11286\74act11286.cir +* u17 net-_u1-pad1_ net-_u1-pad2_ net-_u17-pad3_ d_xnor +* u21 net-_u1-pad3_ net-_u21-pad2_ d_inverter +* u25 net-_u17-pad3_ net-_u21-pad2_ net-_u25-pad3_ d_xnor +* u18 net-_u1-pad4_ net-_u1-pad5_ net-_u18-pad3_ d_xnor +* u22 net-_u1-pad6_ net-_u22-pad2_ d_inverter +* u26 net-_u18-pad3_ net-_u22-pad2_ net-_u26-pad3_ d_xnor +* u19 net-_u1-pad7_ net-_u1-pad8_ net-_u19-pad3_ d_xnor +* u23 net-_u1-pad9_ net-_u23-pad2_ d_inverter +* u27 net-_u19-pad3_ net-_u23-pad2_ net-_u27-pad3_ d_xnor +* u29 net-_u25-pad3_ net-_u26-pad3_ net-_u29-pad3_ d_xnor +* u30 net-_u27-pad3_ net-_u30-pad2_ d_inverter +* u31 net-_u29-pad3_ net-_u30-pad2_ net-_u24-pad1_ d_xnor +* u32 net-_u24-pad1_ net-_u32-pad2_ d_inverter +* u33 net-_u32-pad2_ net-_u28-pad2_ net-_u33-pad3_ d_xnor +* u35 net-_u33-pad3_ net-_u34-pad2_ net-_u1-pad12_ d_nand +* u34 net-_u20-pad2_ net-_u34-pad2_ d_inverter +* u28 net-_u1-pad10_ net-_u28-pad2_ d_inverter +* u20 net-_u1-pad11_ net-_u20-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u20-pad2_ net-_u16-pad1_ d_tristate +* u16 net-_u16-pad1_ net-_u1-pad10_ d_inverter +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u17-pad3_ u17 +a2 net-_u1-pad3_ net-_u21-pad2_ u21 +a3 [net-_u17-pad3_ net-_u21-pad2_ ] net-_u25-pad3_ u25 +a4 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u18-pad3_ u18 +a5 net-_u1-pad6_ net-_u22-pad2_ u22 +a6 [net-_u18-pad3_ net-_u22-pad2_ ] net-_u26-pad3_ u26 +a7 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u19-pad3_ u19 +a8 net-_u1-pad9_ net-_u23-pad2_ u23 +a9 [net-_u19-pad3_ net-_u23-pad2_ ] net-_u27-pad3_ u27 +a10 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u29-pad3_ u29 +a11 net-_u27-pad3_ net-_u30-pad2_ u30 +a12 [net-_u29-pad3_ net-_u30-pad2_ ] net-_u24-pad1_ u31 +a13 net-_u24-pad1_ net-_u32-pad2_ u32 +a14 [net-_u32-pad2_ net-_u28-pad2_ ] net-_u33-pad3_ u33 +a15 [net-_u33-pad3_ net-_u34-pad2_ ] net-_u1-pad12_ u35 +a16 net-_u20-pad2_ net-_u34-pad2_ u34 +a17 net-_u1-pad10_ net-_u28-pad2_ u28 +a18 net-_u1-pad11_ net-_u20-pad2_ u20 +a19 net-_u24-pad1_ net-_u20-pad2_ net-_u16-pad1_ u24 +a20 net-_u16-pad1_ net-_u1-pad10_ u16 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u17 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u27 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u29 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u31 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u33 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u24 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74ACT11286
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74ACT11286/74ACT11286_Previous_Values.xml b/library/SubcircuitLibrary/74ACT11286/74ACT11286_Previous_Values.xml new file mode 100644 index 00000000..805c7021 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11286/74ACT11286_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u17 name="type">d_xnor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u17><u21 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u21><u25 name="type">d_xnor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u25><u18 name="type">d_xnor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u18><u22 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u22><u26 name="type">d_xnor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u26><u19 name="type">d_xnor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u19><u23 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u23><u27 name="type">d_xnor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u27><u29 name="type">d_xnor<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_xnor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u32><u33 name="type">d_xnor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u33><u35 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u35><u34 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u34><u28 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u28><u20 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u20><u24 name="type">d_tristate<field55 name="Enter Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Enable Load (default=1.0e-12)" /></u24><u16 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u16></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74ACT11286/analysis b/library/SubcircuitLibrary/74ACT11286/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74ACT11286/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74LVC1G97/74LVC1G97-cache.lib b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97-cache.lib new file mode 100644 index 00000000..889b4267 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir new file mode 100644 index 00000000..1f3aa522 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir @@ -0,0 +1,20 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74LVC1G97\74LVC1G97.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/16/24 02:11:52 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U8 Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad1_ d_and +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad4_ d_or +U9 Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad2_ d_and +U7 Net-_U3-Pad2_ Net-_U7-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U4-Pad2_ Net-_U5-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir.out b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir.out new file mode 100644 index 00000000..9148aa48 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir.out @@ -0,0 +1,48 @@ +* c:\fossee\esim\library\subcircuitlibrary\74lvc1g97\74lvc1g97.cir + +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u8 net-_u6-pad2_ net-_u5-pad2_ net-_u10-pad1_ d_and +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad4_ d_or +* u9 net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ d_and +* u7 net-_u3-pad2_ net-_u7-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 net-_u1-pad2_ net-_u3-pad2_ u3 +a2 [net-_u6-pad2_ net-_u5-pad2_ ] net-_u10-pad1_ u8 +a3 net-_u2-pad2_ net-_u6-pad2_ u6 +a4 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad4_ u10 +a5 [net-_u7-pad2_ net-_u4-pad2_ ] net-_u10-pad2_ u9 +a6 net-_u3-pad2_ net-_u7-pad2_ u7 +a7 net-_u1-pad1_ net-_u2-pad2_ u2 +a8 net-_u1-pad3_ net-_u4-pad2_ u4 +a9 net-_u4-pad2_ net-_u5-pad2_ u5 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.pro b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sch b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sch new file mode 100644 index 00000000..cbc3c029 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sch @@ -0,0 +1,224 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 666DFBF0 +P 3350 2900 +F 0 "U3" H 3350 2800 60 0000 C CNN +F 1 "d_inverter" H 3350 3050 60 0000 C CNN +F 2 "" H 3400 2850 60 0000 C CNN +F 3 "" H 3400 2850 60 0000 C CNN + 1 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 666DFC27 +P 5150 2500 +F 0 "U8" H 5150 2500 60 0000 C CNN +F 1 "d_and" H 5200 2600 60 0000 C CNN +F 2 "" H 5150 2500 60 0000 C CNN +F 3 "" H 5150 2500 60 0000 C CNN + 1 5150 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 666DFC6E +P 4400 2400 +F 0 "U6" H 4400 2300 60 0000 C CNN +F 1 "d_inverter" H 4400 2550 60 0000 C CNN +F 2 "" H 4450 2350 60 0000 C CNN +F 3 "" H 4450 2350 60 0000 C CNN + 1 4400 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U10 +U 1 1 666DFCAC +P 6050 2750 +F 0 "U10" H 6050 2750 60 0000 C CNN +F 1 "d_or" H 6050 2850 60 0000 C CNN +F 2 "" H 6050 2750 60 0000 C CNN +F 3 "" H 6050 2750 60 0000 C CNN + 1 6050 2750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 666DFD21 +P 5150 3000 +F 0 "U9" H 5150 3000 60 0000 C CNN +F 1 "d_and" H 5200 3100 60 0000 C CNN +F 2 "" H 5150 3000 60 0000 C CNN +F 3 "" H 5150 3000 60 0000 C CNN + 1 5150 3000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 666DFD27 +P 4400 2900 +F 0 "U7" H 4400 2800 60 0000 C CNN +F 1 "d_inverter" H 4400 3050 60 0000 C CNN +F 2 "" H 4450 2850 60 0000 C CNN +F 3 "" H 4450 2850 60 0000 C CNN + 1 4400 2900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 666DFD59 +P 3350 2400 +F 0 "U2" H 3350 2300 60 0000 C CNN +F 1 "d_inverter" H 3350 2550 60 0000 C CNN +F 2 "" H 3400 2350 60 0000 C CNN +F 3 "" H 3400 2350 60 0000 C CNN + 1 3350 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 666DFD92 +P 3350 3400 +F 0 "U4" H 3350 3300 60 0000 C CNN +F 1 "d_inverter" H 3350 3550 60 0000 C CNN +F 2 "" H 3400 3350 60 0000 C CNN +F 3 "" H 3400 3350 60 0000 C CNN + 1 3350 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 666DFDE2 +P 4100 3400 +F 0 "U5" H 4100 3300 60 0000 C CNN +F 1 "d_inverter" H 4100 3550 60 0000 C CNN +F 2 "" H 4150 3350 60 0000 C CNN +F 3 "" H 4150 3350 60 0000 C CNN + 1 4100 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3650 3400 3800 3400 +Wire Wire Line + 4100 2900 3650 2900 +Wire Wire Line + 3650 2400 4100 2400 +Wire Wire Line + 4700 2500 4600 2500 +Wire Wire Line + 4600 2500 4600 3400 +Wire Wire Line + 4600 3400 4400 3400 +Wire Wire Line + 4700 3000 3750 3000 +Wire Wire Line + 3750 3000 3750 3400 +Connection ~ 3750 3400 +Wire Wire Line + 5600 2650 5600 2650 +Wire Wire Line + 5600 2650 5600 2450 +Wire Wire Line + 5600 2750 5600 2750 +Wire Wire Line + 5600 2750 5600 2950 +$Comp +L PORT U1 +U 4 1 666DFEB3 +P 6750 2700 +F 0 "U1" H 6800 2800 30 0000 C CNN +F 1 "PORT" H 6750 2700 30 0000 C CNN +F 2 "" H 6750 2700 60 0000 C CNN +F 3 "" H 6750 2700 60 0000 C CNN + 4 6750 2700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 666E01B8 +P 3050 2150 +F 0 "U1" H 3100 2250 30 0000 C CNN +F 1 "PORT" H 3050 2150 30 0000 C CNN +F 2 "" H 3050 2150 60 0000 C CNN +F 3 "" H 3050 2150 60 0000 C CNN + 1 3050 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 666E0201 +P 3050 2650 +F 0 "U1" H 3100 2750 30 0000 C CNN +F 1 "PORT" H 3050 2650 30 0000 C CNN +F 2 "" H 3050 2650 60 0000 C CNN +F 3 "" H 3050 2650 60 0000 C CNN + 2 3050 2650 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 666E023A +P 3050 3150 +F 0 "U1" H 3100 3250 30 0000 C CNN +F 1 "PORT" H 3050 3150 30 0000 C CNN +F 2 "" H 3050 3150 60 0000 C CNN +F 3 "" H 3050 3150 60 0000 C CNN + 3 3050 3150 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sub b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sub new file mode 100644 index 00000000..8900cec3 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sub @@ -0,0 +1,42 @@ +* Subcircuit 74LVC1G97 +.subckt 74LVC1G97 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\fossee\esim\library\subcircuitlibrary\74lvc1g97\74lvc1g97.cir +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u8 net-_u6-pad2_ net-_u5-pad2_ net-_u10-pad1_ d_and +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad4_ d_or +* u9 net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ d_and +* u7 net-_u3-pad2_ net-_u7-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +a1 net-_u1-pad2_ net-_u3-pad2_ u3 +a2 [net-_u6-pad2_ net-_u5-pad2_ ] net-_u10-pad1_ u8 +a3 net-_u2-pad2_ net-_u6-pad2_ u6 +a4 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad4_ u10 +a5 [net-_u7-pad2_ net-_u4-pad2_ ] net-_u10-pad2_ u9 +a6 net-_u3-pad2_ net-_u7-pad2_ u7 +a7 net-_u1-pad1_ net-_u2-pad2_ u2 +a8 net-_u1-pad3_ net-_u4-pad2_ u4 +a9 net-_u4-pad2_ net-_u5-pad2_ u5 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74LVC1G97
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74LVC1G97/74LVC1G97_Previous_Values.xml b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97_Previous_Values.xml new file mode 100644 index 00000000..16396780 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u8 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u6><u10 name="type">d_or<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u9><u7 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u7><u2 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u2><u4 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u5></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74LVC1G97/analysis b/library/SubcircuitLibrary/74LVC1G97/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G97/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4050/CD4050-cache.lib b/library/SubcircuitLibrary/CD4050/CD4050-cache.lib new file mode 100644 index 00000000..d8775da4 --- /dev/null +++ b/library/SubcircuitLibrary/CD4050/CD4050-cache.lib @@ -0,0 +1,132 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4050/CD4050.cir b/library/SubcircuitLibrary/CD4050/CD4050.cir new file mode 100644 index 00000000..ff1009b3 --- /dev/null +++ b/library/SubcircuitLibrary/CD4050/CD4050.cir @@ -0,0 +1,29 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4050\CD4050.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/06/24 14:47:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ mosfet_p +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND mosfet_n +C1 Net-_C1-Pad1_ GND 1u +M5 Net-_M2-Pad1_ Net-_M3-Pad2_ Net-_C2-Pad1_ Net-_M2-Pad1_ mosfet_p +M3 Net-_C2-Pad1_ Net-_M3-Pad2_ GND GND mosfet_n +C2 Net-_C2-Pad1_ GND 1u +M6 Net-_M2-Pad1_ Net-_M4-Pad2_ Net-_C3-Pad1_ Net-_M2-Pad1_ mosfet_p +M4 Net-_C3-Pad1_ Net-_M4-Pad2_ GND GND mosfet_n +C3 Net-_C3-Pad1_ GND 1u +M9 Net-_M2-Pad1_ Net-_M12-Pad2_ Net-_C6-Pad1_ Net-_M2-Pad1_ mosfet_p +M12 Net-_C6-Pad1_ Net-_M12-Pad2_ GND GND mosfet_n +C6 Net-_C6-Pad1_ GND 1u +M7 Net-_M2-Pad1_ Net-_M10-Pad2_ Net-_C4-Pad1_ Net-_M2-Pad1_ mosfet_p +M10 Net-_C4-Pad1_ Net-_M10-Pad2_ GND GND mosfet_n +C4 Net-_C4-Pad1_ GND 1u +M8 Net-_M2-Pad1_ Net-_M11-Pad2_ Net-_C5-Pad1_ Net-_M2-Pad1_ mosfet_p +M11 Net-_C5-Pad1_ Net-_M11-Pad2_ GND GND mosfet_n +C5 Net-_C5-Pad1_ GND 1u +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M3-Pad2_ Net-_C2-Pad1_ Net-_M4-Pad2_ Net-_C3-Pad1_ GND Net-_M2-Pad1_ Net-_M10-Pad2_ Net-_C4-Pad1_ Net-_M11-Pad2_ Net-_C5-Pad1_ Net-_M12-Pad2_ Net-_C6-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4050/CD4050.cir.out b/library/SubcircuitLibrary/CD4050/CD4050.cir.out new file mode 100644 index 00000000..9fe40b96 --- /dev/null +++ b/library/SubcircuitLibrary/CD4050/CD4050.cir.out @@ -0,0 +1,32 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4050\cd4050.cir + +.include NMOS-0.5um.lib +.include PMOS-0.5um.lib +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c1 net-_c1-pad1_ gnd 1u +m5 net-_m2-pad1_ net-_m3-pad2_ net-_c2-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m3 net-_c2-pad1_ net-_m3-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c2 net-_c2-pad1_ gnd 1u +m6 net-_m2-pad1_ net-_m4-pad2_ net-_c3-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m4 net-_c3-pad1_ net-_m4-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c3 net-_c3-pad1_ gnd 1u +m9 net-_m2-pad1_ net-_m12-pad2_ net-_c6-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m12 net-_c6-pad1_ net-_m12-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c6 net-_c6-pad1_ gnd 1u +m7 net-_m2-pad1_ net-_m10-pad2_ net-_c4-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m10 net-_c4-pad1_ net-_m10-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c4 net-_c4-pad1_ gnd 1u +m8 net-_m2-pad1_ net-_m11-pad2_ net-_c5-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m11 net-_c5-pad1_ net-_m11-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c5 net-_c5-pad1_ gnd 1u +* u1 net-_m1-pad2_ net-_c1-pad1_ net-_m3-pad2_ net-_c2-pad1_ net-_m4-pad2_ net-_c3-pad1_ gnd net-_m2-pad1_ net-_m10-pad2_ net-_c4-pad1_ net-_m11-pad2_ net-_c5-pad1_ net-_m12-pad2_ net-_c6-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4050/CD4050.pro b/library/SubcircuitLibrary/CD4050/CD4050.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4050/CD4050.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4050/CD4050.sch b/library/SubcircuitLibrary/CD4050/CD4050.sch new file mode 100644 index 00000000..dd289095 --- /dev/null +++ b/library/SubcircuitLibrary/CD4050/CD4050.sch @@ -0,0 +1,647 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4050-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M2 +U 1 1 66617828 +P 2500 2600 +F 0 "M2" H 2450 2650 50 0000 R CNN +F 1 "mosfet_p" H 2550 2750 50 0000 R CNN +F 2 "" H 2750 2700 29 0000 C CNN +F 3 "" H 2550 2600 60 0000 C CNN + 1 2500 2600 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 66617865 +P 2450 2900 +F 0 "M1" H 2450 2750 50 0000 R CNN +F 1 "mosfet_n" H 2550 2850 50 0000 R CNN +F 2 "" H 2750 2600 29 0000 C CNN +F 3 "" H 2550 2700 60 0000 C CNN + 1 2450 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2650 2900 2650 2800 +$Comp +L capacitor C1 +U 1 1 6661789E +P 2900 3150 +F 0 "C1" H 2925 3250 50 0000 L CNN +F 1 "1u" H 2925 3050 50 0000 L CNN +F 2 "" H 2938 3000 30 0000 C CNN +F 3 "" H 2900 3150 60 0000 C CNN + 1 2900 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2900 3000 2900 2850 +Wire Wire Line + 2650 2850 3300 2850 +Connection ~ 2650 2850 +Wire Wire Line + 2750 3250 2750 3400 +Wire Wire Line + 2650 3400 4350 3400 +Wire Wire Line + 2900 3400 2900 3300 +Wire Wire Line + 2650 3400 2650 3300 +Connection ~ 2750 3400 +Wire Wire Line + 2350 3100 2350 2600 +Wire Wire Line + 2750 2750 2800 2750 +Wire Wire Line + 2800 2750 2800 2400 +Wire Wire Line + 2650 2400 4350 2400 +Wire Wire Line + 2350 2850 2300 2850 +Wire Wire Line + 2300 2850 2300 3400 +Wire Wire Line + 2300 3400 2050 3400 +Connection ~ 2350 2850 +Wire Wire Line + 2050 3500 3300 3500 +Wire Wire Line + 3300 3500 3300 2850 +Connection ~ 2900 2850 +$Comp +L mosfet_p M5 +U 1 1 666179DF +P 2550 4000 +F 0 "M5" H 2500 4050 50 0000 R CNN +F 1 "mosfet_p" H 2600 4150 50 0000 R CNN +F 2 "" H 2800 4100 29 0000 C CNN +F 3 "" H 2600 4000 60 0000 C CNN + 1 2550 4000 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M3 +U 1 1 666179E5 +P 2500 4300 +F 0 "M3" H 2500 4150 50 0000 R CNN +F 1 "mosfet_n" H 2600 4250 50 0000 R CNN +F 2 "" H 2800 4000 29 0000 C CNN +F 3 "" H 2600 4100 60 0000 C CNN + 1 2500 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2700 4300 2700 4200 +$Comp +L capacitor C2 +U 1 1 666179EC +P 2950 4550 +F 0 "C2" H 2975 4650 50 0000 L CNN +F 1 "1u" H 2975 4450 50 0000 L CNN +F 2 "" H 2988 4400 30 0000 C CNN +F 3 "" H 2950 4550 60 0000 C CNN + 1 2950 4550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2950 4400 2950 4250 +Wire Wire Line + 2700 4250 3350 4250 +Connection ~ 2700 4250 +Wire Wire Line + 2800 4650 2800 4800 +Wire Wire Line + 2700 4800 4300 4800 +Wire Wire Line + 2950 4800 2950 4700 +Wire Wire Line + 2700 4800 2700 4700 +Connection ~ 2800 4800 +Wire Wire Line + 2400 4500 2400 4000 +Wire Wire Line + 2800 4150 2850 4150 +Wire Wire Line + 2850 4150 2850 3800 +Wire Wire Line + 2700 3800 4300 3800 +Wire Wire Line + 2400 4250 2350 4250 +Wire Wire Line + 2350 4250 2350 4800 +Wire Wire Line + 2350 4800 2100 4800 +Connection ~ 2400 4250 +Wire Wire Line + 2100 4900 3350 4900 +Wire Wire Line + 3350 4900 3350 4250 +Connection ~ 2950 4250 +$Comp +L mosfet_p M6 +U 1 1 66617BA0 +P 2550 5400 +F 0 "M6" H 2500 5450 50 0000 R CNN +F 1 "mosfet_p" H 2600 5550 50 0000 R CNN +F 2 "" H 2800 5500 29 0000 C CNN +F 3 "" H 2600 5400 60 0000 C CNN + 1 2550 5400 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M4 +U 1 1 66617BA6 +P 2500 5700 +F 0 "M4" H 2500 5550 50 0000 R CNN +F 1 "mosfet_n" H 2600 5650 50 0000 R CNN +F 2 "" H 2800 5400 29 0000 C CNN +F 3 "" H 2600 5500 60 0000 C CNN + 1 2500 5700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2700 5700 2700 5600 +$Comp +L capacitor C3 +U 1 1 66617BAD +P 2950 5950 +F 0 "C3" H 2975 6050 50 0000 L CNN +F 1 "1u" H 2975 5850 50 0000 L CNN +F 2 "" H 2988 5800 30 0000 C CNN +F 3 "" H 2950 5950 60 0000 C CNN + 1 2950 5950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2950 5800 2950 5650 +Wire Wire Line + 2700 5650 3350 5650 +Connection ~ 2700 5650 +Wire Wire Line + 2800 6050 2800 6200 +Wire Wire Line + 2700 6200 4300 6200 +Wire Wire Line + 2950 6200 2950 6100 +Wire Wire Line + 2700 6200 2700 6100 +Connection ~ 2800 6200 +Wire Wire Line + 2400 5900 2400 5400 +Wire Wire Line + 2800 5550 2850 5550 +Wire Wire Line + 2850 5550 2850 5200 +Wire Wire Line + 2700 5200 4300 5200 +Wire Wire Line + 2400 5650 2350 5650 +Wire Wire Line + 2350 5650 2350 6200 +Wire Wire Line + 2350 6200 2100 6200 +Connection ~ 2400 5650 +Wire Wire Line + 2100 6300 3350 6300 +Wire Wire Line + 3350 6300 3350 5650 +Connection ~ 2950 5650 +$Comp +L mosfet_p M9 +U 1 1 66618007 +P 4500 2600 +F 0 "M9" H 4450 2650 50 0000 R CNN +F 1 "mosfet_p" H 4550 2750 50 0000 R CNN +F 2 "" H 4750 2700 29 0000 C CNN +F 3 "" H 4550 2600 60 0000 C CNN + 1 4500 2600 + -1 0 0 -1 +$EndComp +$Comp +L mosfet_n M12 +U 1 1 6661800D +P 4550 2900 +F 0 "M12" H 4550 2750 50 0000 R CNN +F 1 "mosfet_n" H 4650 2850 50 0000 R CNN +F 2 "" H 4850 2600 29 0000 C CNN +F 3 "" H 4650 2700 60 0000 C CNN + 1 4550 2900 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4350 2900 4350 2800 +$Comp +L capacitor C6 +U 1 1 66618014 +P 4100 3150 +F 0 "C6" H 4125 3250 50 0000 L CNN +F 1 "1u" H 4125 3050 50 0000 L CNN +F 2 "" H 4138 3000 30 0000 C CNN +F 3 "" H 4100 3150 60 0000 C CNN + 1 4100 3150 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4100 3000 4100 2850 +Wire Wire Line + 4350 2850 3700 2850 +Connection ~ 4350 2850 +Wire Wire Line + 4250 3250 4250 3400 +Wire Wire Line + 4100 3400 4100 3300 +Wire Wire Line + 4350 3400 4350 3300 +Connection ~ 4250 3400 +Wire Wire Line + 4650 3100 4650 2600 +Wire Wire Line + 4250 2750 4200 2750 +Wire Wire Line + 4200 2750 4200 2400 +Wire Wire Line + 4650 2850 4700 2850 +Wire Wire Line + 4700 2850 4700 3400 +Wire Wire Line + 4700 3400 4950 3400 +Connection ~ 4650 2850 +Wire Wire Line + 4950 3500 3700 3500 +Wire Wire Line + 3700 3500 3700 2850 +Connection ~ 4100 2850 +$Comp +L mosfet_p M7 +U 1 1 6661802D +P 4450 4000 +F 0 "M7" H 4400 4050 50 0000 R CNN +F 1 "mosfet_p" H 4500 4150 50 0000 R CNN +F 2 "" H 4700 4100 29 0000 C CNN +F 3 "" H 4500 4000 60 0000 C CNN + 1 4450 4000 + -1 0 0 -1 +$EndComp +$Comp +L mosfet_n M10 +U 1 1 66618033 +P 4500 4300 +F 0 "M10" H 4500 4150 50 0000 R CNN +F 1 "mosfet_n" H 4600 4250 50 0000 R CNN +F 2 "" H 4800 4000 29 0000 C CNN +F 3 "" H 4600 4100 60 0000 C CNN + 1 4500 4300 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4300 4300 4300 4200 +$Comp +L capacitor C4 +U 1 1 6661803A +P 4050 4550 +F 0 "C4" H 4075 4650 50 0000 L CNN +F 1 "1u" H 4075 4450 50 0000 L CNN +F 2 "" H 4088 4400 30 0000 C CNN +F 3 "" H 4050 4550 60 0000 C CNN + 1 4050 4550 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4050 4400 4050 4250 +Wire Wire Line + 4300 4250 3650 4250 +Connection ~ 4300 4250 +Wire Wire Line + 4200 4650 4200 4800 +Wire Wire Line + 4050 4800 4050 4700 +Wire Wire Line + 4300 4800 4300 4700 +Connection ~ 4200 4800 +Wire Wire Line + 4600 4500 4600 4000 +Wire Wire Line + 4200 4150 4150 4150 +Wire Wire Line + 4150 4150 4150 3800 +Wire Wire Line + 4600 4250 4650 4250 +Wire Wire Line + 4650 4250 4650 4800 +Wire Wire Line + 4650 4800 4900 4800 +Connection ~ 4600 4250 +Wire Wire Line + 4900 4900 3650 4900 +Wire Wire Line + 3650 4900 3650 4250 +Connection ~ 4050 4250 +$Comp +L mosfet_p M8 +U 1 1 66618053 +P 4450 5400 +F 0 "M8" H 4400 5450 50 0000 R CNN +F 1 "mosfet_p" H 4500 5550 50 0000 R CNN +F 2 "" H 4700 5500 29 0000 C CNN +F 3 "" H 4500 5400 60 0000 C CNN + 1 4450 5400 + -1 0 0 -1 +$EndComp +$Comp +L mosfet_n M11 +U 1 1 66618059 +P 4500 5700 +F 0 "M11" H 4500 5550 50 0000 R CNN +F 1 "mosfet_n" H 4600 5650 50 0000 R CNN +F 2 "" H 4800 5400 29 0000 C CNN +F 3 "" H 4600 5500 60 0000 C CNN + 1 4500 5700 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4300 5700 4300 5600 +$Comp +L capacitor C5 +U 1 1 66618060 +P 4050 5950 +F 0 "C5" H 4075 6050 50 0000 L CNN +F 1 "1u" H 4075 5850 50 0000 L CNN +F 2 "" H 4088 5800 30 0000 C CNN +F 3 "" H 4050 5950 60 0000 C CNN + 1 4050 5950 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4050 5800 4050 5650 +Wire Wire Line + 4300 5650 3650 5650 +Connection ~ 4300 5650 +Wire Wire Line + 4200 6050 4200 6200 +Wire Wire Line + 4050 6200 4050 6100 +Wire Wire Line + 4300 6200 4300 6100 +Connection ~ 4200 6200 +Wire Wire Line + 4600 5900 4600 5400 +Wire Wire Line + 4200 5550 4150 5550 +Wire Wire Line + 4150 5550 4150 5200 +Wire Wire Line + 4600 5650 4650 5650 +Wire Wire Line + 4650 5650 4650 6200 +Wire Wire Line + 4650 6200 4900 6200 +Connection ~ 4600 5650 +Wire Wire Line + 4900 6300 3650 6300 +Wire Wire Line + 3650 6300 3650 5650 +Connection ~ 4050 5650 +Connection ~ 4100 3400 +Connection ~ 2900 3400 +Connection ~ 4050 4800 +Connection ~ 2950 4800 +Connection ~ 2950 6200 +Connection ~ 4050 6200 +Wire Wire Line + 3400 3400 3400 6200 +Connection ~ 3400 4800 +Connection ~ 3400 6200 +Connection ~ 3400 3400 +Connection ~ 4150 5200 +Connection ~ 2850 5200 +Wire Wire Line + 3600 2400 3600 5200 +Connection ~ 4150 3800 +Connection ~ 3600 5200 +Connection ~ 2850 3800 +Connection ~ 3600 3800 +Connection ~ 4200 2400 +Connection ~ 3600 2400 +Connection ~ 2800 2400 +$Comp +L PORT U1 +U 8 1 66618EC8 +P 3600 2150 +F 0 "U1" H 3650 2250 30 0000 C CNN +F 1 "PORT" H 3600 2150 30 0000 C CNN +F 2 "" H 3600 2150 60 0000 C CNN +F 3 "" H 3600 2150 60 0000 C CNN + 8 3600 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 66618F0F +P 3400 3150 +F 0 "U1" H 3450 3250 30 0000 C CNN +F 1 "PORT" H 3400 3150 30 0000 C CNN +F 2 "" H 3400 3150 60 0000 C CNN +F 3 "" H 3400 3150 60 0000 C CNN + 7 3400 3150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 66618F54 +P 1800 3400 +F 0 "U1" H 1850 3500 30 0000 C CNN +F 1 "PORT" H 1800 3400 30 0000 C CNN +F 2 "" H 1800 3400 60 0000 C CNN +F 3 "" H 1800 3400 60 0000 C CNN + 1 1800 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 66618F9B +P 1800 3500 +F 0 "U1" H 1850 3600 30 0000 C CNN +F 1 "PORT" H 1800 3500 30 0000 C CNN +F 2 "" H 1800 3500 60 0000 C CNN +F 3 "" H 1800 3500 60 0000 C CNN + 2 1800 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 66618FE0 +P 5200 3400 +F 0 "U1" H 5250 3500 30 0000 C CNN +F 1 "PORT" H 5200 3400 30 0000 C CNN +F 2 "" H 5200 3400 60 0000 C CNN +F 3 "" H 5200 3400 60 0000 C CNN + 13 5200 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 66619039 +P 5200 3500 +F 0 "U1" H 5250 3600 30 0000 C CNN +F 1 "PORT" H 5200 3500 30 0000 C CNN +F 2 "" H 5200 3500 60 0000 C CNN +F 3 "" H 5200 3500 60 0000 C CNN + 14 5200 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 66619832 +P 1850 4800 +F 0 "U1" H 1900 4900 30 0000 C CNN +F 1 "PORT" H 1850 4800 30 0000 C CNN +F 2 "" H 1850 4800 60 0000 C CNN +F 3 "" H 1850 4800 60 0000 C CNN + 3 1850 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 66619879 +P 1850 4900 +F 0 "U1" H 1900 5000 30 0000 C CNN +F 1 "PORT" H 1850 4900 30 0000 C CNN +F 2 "" H 1850 4900 60 0000 C CNN +F 3 "" H 1850 4900 60 0000 C CNN + 4 1850 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 666198C2 +P 5150 4800 +F 0 "U1" H 5200 4900 30 0000 C CNN +F 1 "PORT" H 5150 4800 30 0000 C CNN +F 2 "" H 5150 4800 60 0000 C CNN +F 3 "" H 5150 4800 60 0000 C CNN + 9 5150 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 66619915 +P 5150 4900 +F 0 "U1" H 5200 5000 30 0000 C CNN +F 1 "PORT" H 5150 4900 30 0000 C CNN +F 2 "" H 5150 4900 60 0000 C CNN +F 3 "" H 5150 4900 60 0000 C CNN + 10 5150 4900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 66619966 +P 1850 6200 +F 0 "U1" H 1900 6300 30 0000 C CNN +F 1 "PORT" H 1850 6200 30 0000 C CNN +F 2 "" H 1850 6200 60 0000 C CNN +F 3 "" H 1850 6200 60 0000 C CNN + 5 1850 6200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 666199B7 +P 1850 6300 +F 0 "U1" H 1900 6400 30 0000 C CNN +F 1 "PORT" H 1850 6300 30 0000 C CNN +F 2 "" H 1850 6300 60 0000 C CNN +F 3 "" H 1850 6300 60 0000 C CNN + 6 1850 6300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 66619A08 +P 5150 6200 +F 0 "U1" H 5200 6300 30 0000 C CNN +F 1 "PORT" H 5150 6200 30 0000 C CNN +F 2 "" H 5150 6200 60 0000 C CNN +F 3 "" H 5150 6200 60 0000 C CNN + 11 5150 6200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 66619A61 +P 5150 6300 +F 0 "U1" H 5200 6400 30 0000 C CNN +F 1 "PORT" H 5150 6300 30 0000 C CNN +F 2 "" H 5150 6300 60 0000 C CNN +F 3 "" H 5150 6300 60 0000 C CNN + 12 5150 6300 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 66617FD5 +P 3850 3400 +F 0 "#PWR01" H 3850 3150 50 0001 C CNN +F 1 "GND" H 3850 3250 50 0000 C CNN +F 2 "" H 3850 3400 50 0001 C CNN +F 3 "" H 3850 3400 50 0001 C CNN + 1 3850 3400 + 1 0 0 -1 +$EndComp +Connection ~ 3850 3400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4050/CD4050.sub b/library/SubcircuitLibrary/CD4050/CD4050.sub new file mode 100644 index 00000000..efdcf8be --- /dev/null +++ b/library/SubcircuitLibrary/CD4050/CD4050.sub @@ -0,0 +1,26 @@ +* Subcircuit CD4050 +.subckt CD4050 net-_m1-pad2_ net-_c1-pad1_ net-_m3-pad2_ net-_c2-pad1_ net-_m4-pad2_ net-_c3-pad1_ gnd net-_m2-pad1_ net-_m10-pad2_ net-_c4-pad1_ net-_m11-pad2_ net-_c5-pad1_ net-_m12-pad2_ net-_c6-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\cd4050\cd4050.cir +.include NMOS-0.5um.lib +.include PMOS-0.5um.lib +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c1 net-_c1-pad1_ gnd 1u +m5 net-_m2-pad1_ net-_m3-pad2_ net-_c2-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m3 net-_c2-pad1_ net-_m3-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c2 net-_c2-pad1_ gnd 1u +m6 net-_m2-pad1_ net-_m4-pad2_ net-_c3-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m4 net-_c3-pad1_ net-_m4-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c3 net-_c3-pad1_ gnd 1u +m9 net-_m2-pad1_ net-_m12-pad2_ net-_c6-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m12 net-_c6-pad1_ net-_m12-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c6 net-_c6-pad1_ gnd 1u +m7 net-_m2-pad1_ net-_m10-pad2_ net-_c4-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m10 net-_c4-pad1_ net-_m10-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c4 net-_c4-pad1_ gnd 1u +m8 net-_m2-pad1_ net-_m11-pad2_ net-_c5-pad1_ net-_m2-pad1_ mos_p W=100u L=100u M=1 +m11 net-_c5-pad1_ net-_m11-pad2_ gnd gnd mos_n W=100u L=100u M=1 +c5 net-_c5-pad1_ gnd 1u +* Control Statements + +.ends CD4050
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4050/CD4050_Previous_Values.xml b/library/SubcircuitLibrary/CD4050/CD4050_Previous_Values.xml new file mode 100644 index 00000000..572745f5 --- /dev/null +++ b/library/SubcircuitLibrary/CD4050/CD4050_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field /><field /><field /></m2><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field /><field /><field /></m1><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field /><field /><field /></m5><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field /><field /><field /></m3><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field /><field /><field /></m6><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field /><field /><field /></m4><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field /><field /><field /></m9><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field /><field /><field /></m12><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field /><field /><field /></m7><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field /><field /><field /></m10><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-0.5um.lib</field><field /><field /><field /></m8><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-0.5um.lib</field><field /><field /><field /></m11></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4050/NMOS-0.5um.lib b/library/SubcircuitLibrary/CD4050/NMOS-0.5um.lib new file mode 100644 index 00000000..2e6f4635 --- /dev/null +++ b/library/SubcircuitLibrary/CD4050/NMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 )
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4050/PMOS-0.5um.lib b/library/SubcircuitLibrary/CD4050/PMOS-0.5um.lib new file mode 100644 index 00000000..848e8b05 --- /dev/null +++ b/library/SubcircuitLibrary/CD4050/PMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u ++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 ++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 ++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 ++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 ++ NSUB=1.0E17 )
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4050/analysis b/library/SubcircuitLibrary/CD4050/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4050/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/FCT827/FCT827-cache.lib b/library/SubcircuitLibrary/FCT827/FCT827-cache.lib new file mode 100644 index 00000000..2c79a539 --- /dev/null +++ b/library/SubcircuitLibrary/FCT827/FCT827-cache.lib @@ -0,0 +1,90 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/FCT827/FCT827.cir b/library/SubcircuitLibrary/FCT827/FCT827.cir new file mode 100644 index 00000000..a059c52c --- /dev/null +++ b/library/SubcircuitLibrary/FCT827/FCT827.cir @@ -0,0 +1,24 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\FCT827\FCT827.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/10/24 02:15:36 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U4 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U10-Pad2_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U5 Net-_U1-Pad3_ Net-_U10-Pad2_ Net-_U1-Pad13_ d_tristate +U6 Net-_U1-Pad4_ Net-_U10-Pad2_ Net-_U1-Pad14_ d_tristate +U7 Net-_U1-Pad5_ Net-_U10-Pad2_ Net-_U1-Pad15_ d_tristate +U8 Net-_U1-Pad6_ Net-_U10-Pad2_ Net-_U1-Pad16_ d_tristate +U9 Net-_U1-Pad7_ Net-_U10-Pad2_ Net-_U1-Pad17_ d_tristate +U10 Net-_U1-Pad8_ Net-_U10-Pad2_ Net-_U1-Pad18_ d_tristate +U11 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U1-Pad19_ d_tristate +U12 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U1-Pad20_ d_tristate +U13 Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U1-Pad21_ d_tristate +U14 Net-_U1-Pad12_ Net-_U10-Pad2_ Net-_U1-Pad22_ d_tristate +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ PORT + +.end diff --git a/library/SubcircuitLibrary/FCT827/FCT827.cir.out b/library/SubcircuitLibrary/FCT827/FCT827.cir.out new file mode 100644 index 00000000..8d3b557a --- /dev/null +++ b/library/SubcircuitLibrary/FCT827/FCT827.cir.out @@ -0,0 +1,64 @@ +* c:\fossee\esim\library\subcircuitlibrary\fct827\fct827.cir + +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u10-pad2_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u5 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad13_ d_tristate +* u6 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad14_ d_tristate +* u7 net-_u1-pad5_ net-_u10-pad2_ net-_u1-pad15_ d_tristate +* u8 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad16_ d_tristate +* u9 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad17_ d_tristate +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad18_ d_tristate +* u11 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad19_ d_tristate +* u12 net-_u1-pad10_ net-_u10-pad2_ net-_u1-pad20_ d_tristate +* u13 net-_u1-pad11_ net-_u10-pad2_ net-_u1-pad21_ d_tristate +* u14 net-_u1-pad12_ net-_u10-pad2_ net-_u1-pad22_ d_tristate +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ port +a1 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u10-pad2_ u4 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad13_ u5 +a5 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad14_ u6 +a6 net-_u1-pad5_ net-_u10-pad2_ net-_u1-pad15_ u7 +a7 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad16_ u8 +a8 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad17_ u9 +a9 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad18_ u10 +a10 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad19_ u11 +a11 net-_u1-pad10_ net-_u10-pad2_ net-_u1-pad20_ u12 +a12 net-_u1-pad11_ net-_u10-pad2_ net-_u1-pad21_ u13 +a13 net-_u1-pad12_ net-_u10-pad2_ net-_u1-pad22_ u14 +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u7 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +.tran 10e-03 1e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/FCT827/FCT827.pro b/library/SubcircuitLibrary/FCT827/FCT827.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/FCT827/FCT827.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/FCT827/FCT827.sch b/library/SubcircuitLibrary/FCT827/FCT827.sch new file mode 100644 index 00000000..1ba486c9 --- /dev/null +++ b/library/SubcircuitLibrary/FCT827/FCT827.sch @@ -0,0 +1,518 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U4 +U 1 1 66660FBE +P 3950 1150 +F 0 "U4" H 3950 1150 60 0000 C CNN +F 1 "d_and" H 4000 1250 60 0000 C CNN +F 2 "" H 3950 1150 60 0000 C CNN +F 3 "" H 3950 1150 60 0000 C CNN + 1 3950 1150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 66661000 +P 3200 1050 +F 0 "U2" H 3200 950 60 0000 C CNN +F 1 "d_inverter" H 3200 1200 60 0000 C CNN +F 2 "" H 3250 1000 60 0000 C CNN +F 3 "" H 3250 1000 60 0000 C CNN + 1 3200 1050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 66661029 +P 3200 1150 +F 0 "U3" H 3200 1050 60 0000 C CNN +F 1 "d_inverter" H 3200 1300 60 0000 C CNN +F 2 "" H 3250 1100 60 0000 C CNN +F 3 "" H 3250 1100 60 0000 C CNN + 1 3200 1150 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U5 +U 1 1 66661041 +P 4000 1450 +F 0 "U5" H 3750 1700 60 0000 C CNN +F 1 "d_tristate" H 3800 1900 60 0000 C CNN +F 2 "" H 3900 1800 60 0000 C CNN +F 3 "" H 3900 1800 60 0000 C CNN + 1 4000 1450 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U6 +U 1 1 66661105 +P 4000 2050 +F 0 "U6" H 3750 2300 60 0000 C CNN +F 1 "d_tristate" H 3800 2500 60 0000 C CNN +F 2 "" H 3900 2400 60 0000 C CNN +F 3 "" H 3900 2400 60 0000 C CNN + 1 4000 2050 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U7 +U 1 1 6666119D +P 4000 2650 +F 0 "U7" H 3750 2900 60 0000 C CNN +F 1 "d_tristate" H 3800 3100 60 0000 C CNN +F 2 "" H 3900 3000 60 0000 C CNN +F 3 "" H 3900 3000 60 0000 C CNN + 1 4000 2650 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U8 +U 1 1 666611A5 +P 4000 3250 +F 0 "U8" H 3750 3500 60 0000 C CNN +F 1 "d_tristate" H 3800 3700 60 0000 C CNN +F 2 "" H 3900 3600 60 0000 C CNN +F 3 "" H 3900 3600 60 0000 C CNN + 1 4000 3250 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U9 +U 1 1 66661309 +P 4000 3850 +F 0 "U9" H 3750 4100 60 0000 C CNN +F 1 "d_tristate" H 3800 4300 60 0000 C CNN +F 2 "" H 3900 4200 60 0000 C CNN +F 3 "" H 3900 4200 60 0000 C CNN + 1 4000 3850 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U10 +U 1 1 66661312 +P 4000 4450 +F 0 "U10" H 3750 4700 60 0000 C CNN +F 1 "d_tristate" H 3800 4900 60 0000 C CNN +F 2 "" H 3900 4800 60 0000 C CNN +F 3 "" H 3900 4800 60 0000 C CNN + 1 4000 4450 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U11 +U 1 1 6666131B +P 4000 5050 +F 0 "U11" H 3750 5300 60 0000 C CNN +F 1 "d_tristate" H 3800 5500 60 0000 C CNN +F 2 "" H 3900 5400 60 0000 C CNN +F 3 "" H 3900 5400 60 0000 C CNN + 1 4000 5050 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U12 +U 1 1 66661323 +P 4000 5650 +F 0 "U12" H 3750 5900 60 0000 C CNN +F 1 "d_tristate" H 3800 6100 60 0000 C CNN +F 2 "" H 3900 6000 60 0000 C CNN +F 3 "" H 3900 6000 60 0000 C CNN + 1 4000 5650 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U13 +U 1 1 6666172F +P 4000 6250 +F 0 "U13" H 3750 6500 60 0000 C CNN +F 1 "d_tristate" H 3800 6700 60 0000 C CNN +F 2 "" H 3900 6600 60 0000 C CNN +F 3 "" H 3900 6600 60 0000 C CNN + 1 4000 6250 + 1 0 0 1 +$EndComp +$Comp +L d_tristate U14 +U 1 1 66661737 +P 4000 6850 +F 0 "U14" H 3750 7100 60 0000 C CNN +F 1 "d_tristate" H 3800 7300 60 0000 C CNN +F 2 "" H 3900 7200 60 0000 C CNN +F 3 "" H 3900 7200 60 0000 C CNN + 1 4000 6850 + 1 0 0 1 +$EndComp +Wire Wire Line + 4550 1800 5750 1800 +Wire Wire Line + 4400 1100 4850 1100 +Wire Wire Line + 4850 1100 4850 6900 +Wire Wire Line + 4850 1500 3950 1500 +Wire Wire Line + 3400 1800 2500 1800 +Wire Wire Line + 4550 2400 5750 2400 +Wire Wire Line + 4850 2100 3950 2100 +Wire Wire Line + 3400 2400 2500 2400 +Wire Wire Line + 4550 3000 5750 3000 +Wire Wire Line + 3400 3000 2500 3000 +Wire Wire Line + 4550 3600 5750 3600 +Wire Wire Line + 4850 3300 3950 3300 +Wire Wire Line + 3400 3600 2500 3600 +Wire Wire Line + 4550 4200 5750 4200 +Wire Wire Line + 4850 3900 3950 3900 +Wire Wire Line + 3400 4200 2500 4200 +Wire Wire Line + 4550 4800 5750 4800 +Wire Wire Line + 4850 4500 3950 4500 +Wire Wire Line + 3400 4800 2500 4800 +Wire Wire Line + 4550 5400 5750 5400 +Wire Wire Line + 3400 5400 2500 5400 +Wire Wire Line + 4550 6000 5750 6000 +Wire Wire Line + 4850 5700 3950 5700 +Wire Wire Line + 3400 6000 2500 6000 +Wire Wire Line + 4550 6600 5750 6600 +Wire Wire Line + 3400 6600 2500 6600 +Wire Wire Line + 4550 7200 5750 7200 +Wire Wire Line + 4850 6900 3950 6900 +Wire Wire Line + 3400 7200 2500 7200 +Connection ~ 4850 1500 +Wire Wire Line + 4850 2700 3950 2700 +Connection ~ 4850 2100 +Connection ~ 4850 2700 +Connection ~ 4850 3300 +Connection ~ 4850 3900 +Wire Wire Line + 4850 5100 3950 5100 +Connection ~ 4850 4500 +Connection ~ 4850 5100 +Wire Wire Line + 4850 6300 3950 6300 +Connection ~ 4850 5700 +Connection ~ 4850 6300 +Wire Wire Line + 2500 1150 2900 1150 +Wire Wire Line + 2900 1050 2500 1050 +$Comp +L PORT U1 +U 1 1 666631FF +P 2250 1050 +F 0 "U1" H 2300 1150 30 0000 C CNN +F 1 "PORT" H 2250 1050 30 0000 C CNN +F 2 "" H 2250 1050 60 0000 C CNN +F 3 "" H 2250 1050 60 0000 C CNN + 1 2250 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 66663234 +P 2250 1150 +F 0 "U1" H 2300 1250 30 0000 C CNN +F 1 "PORT" H 2250 1150 30 0000 C CNN +F 2 "" H 2250 1150 60 0000 C CNN +F 3 "" H 2250 1150 60 0000 C CNN + 2 2250 1150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 66663285 +P 2250 1800 +F 0 "U1" H 2300 1900 30 0000 C CNN +F 1 "PORT" H 2250 1800 30 0000 C CNN +F 2 "" H 2250 1800 60 0000 C CNN +F 3 "" H 2250 1800 60 0000 C CNN + 3 2250 1800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 666632F6 +P 2250 2400 +F 0 "U1" H 2300 2500 30 0000 C CNN +F 1 "PORT" H 2250 2400 30 0000 C CNN +F 2 "" H 2250 2400 60 0000 C CNN +F 3 "" H 2250 2400 60 0000 C CNN + 4 2250 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 66663371 +P 2250 3000 +F 0 "U1" H 2300 3100 30 0000 C CNN +F 1 "PORT" H 2250 3000 30 0000 C CNN +F 2 "" H 2250 3000 60 0000 C CNN +F 3 "" H 2250 3000 60 0000 C CNN + 5 2250 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 666633AA +P 2250 3600 +F 0 "U1" H 2300 3700 30 0000 C CNN +F 1 "PORT" H 2250 3600 30 0000 C CNN +F 2 "" H 2250 3600 60 0000 C CNN +F 3 "" H 2250 3600 60 0000 C CNN + 6 2250 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 666634B6 +P 2250 4200 +F 0 "U1" H 2300 4300 30 0000 C CNN +F 1 "PORT" H 2250 4200 30 0000 C CNN +F 2 "" H 2250 4200 60 0000 C CNN +F 3 "" H 2250 4200 60 0000 C CNN + 7 2250 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 666634F3 +P 2250 4800 +F 0 "U1" H 2300 4900 30 0000 C CNN +F 1 "PORT" H 2250 4800 30 0000 C CNN +F 2 "" H 2250 4800 60 0000 C CNN +F 3 "" H 2250 4800 60 0000 C CNN + 8 2250 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 66663532 +P 2250 5400 +F 0 "U1" H 2300 5500 30 0000 C CNN +F 1 "PORT" H 2250 5400 30 0000 C CNN +F 2 "" H 2250 5400 60 0000 C CNN +F 3 "" H 2250 5400 60 0000 C CNN + 9 2250 5400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 66663573 +P 2250 6000 +F 0 "U1" H 2300 6100 30 0000 C CNN +F 1 "PORT" H 2250 6000 30 0000 C CNN +F 2 "" H 2250 6000 60 0000 C CNN +F 3 "" H 2250 6000 60 0000 C CNN + 10 2250 6000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 666635B6 +P 2250 6600 +F 0 "U1" H 2300 6700 30 0000 C CNN +F 1 "PORT" H 2250 6600 30 0000 C CNN +F 2 "" H 2250 6600 60 0000 C CNN +F 3 "" H 2250 6600 60 0000 C CNN + 11 2250 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 66663613 +P 2250 7200 +F 0 "U1" H 2300 7300 30 0000 C CNN +F 1 "PORT" H 2250 7200 30 0000 C CNN +F 2 "" H 2250 7200 60 0000 C CNN +F 3 "" H 2250 7200 60 0000 C CNN + 12 2250 7200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 666636F0 +P 6000 1800 +F 0 "U1" H 6050 1900 30 0000 C CNN +F 1 "PORT" H 6000 1800 30 0000 C CNN +F 2 "" H 6000 1800 60 0000 C CNN +F 3 "" H 6000 1800 60 0000 C CNN + 13 6000 1800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 6666373D +P 6000 2400 +F 0 "U1" H 6050 2500 30 0000 C CNN +F 1 "PORT" H 6000 2400 30 0000 C CNN +F 2 "" H 6000 2400 60 0000 C CNN +F 3 "" H 6000 2400 60 0000 C CNN + 14 6000 2400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 6666378C +P 6000 3000 +F 0 "U1" H 6050 3100 30 0000 C CNN +F 1 "PORT" H 6000 3000 30 0000 C CNN +F 2 "" H 6000 3000 60 0000 C CNN +F 3 "" H 6000 3000 60 0000 C CNN + 15 6000 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 666637DD +P 6000 3600 +F 0 "U1" H 6050 3700 30 0000 C CNN +F 1 "PORT" H 6000 3600 30 0000 C CNN +F 2 "" H 6000 3600 60 0000 C CNN +F 3 "" H 6000 3600 60 0000 C CNN + 16 6000 3600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 17 1 66663887 +P 6000 4200 +F 0 "U1" H 6050 4300 30 0000 C CNN +F 1 "PORT" H 6000 4200 30 0000 C CNN +F 2 "" H 6000 4200 60 0000 C CNN +F 3 "" H 6000 4200 60 0000 C CNN + 17 6000 4200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 18 1 666638DE +P 6000 4800 +F 0 "U1" H 6050 4900 30 0000 C CNN +F 1 "PORT" H 6000 4800 30 0000 C CNN +F 2 "" H 6000 4800 60 0000 C CNN +F 3 "" H 6000 4800 60 0000 C CNN + 18 6000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 19 1 66663935 +P 6000 5400 +F 0 "U1" H 6050 5500 30 0000 C CNN +F 1 "PORT" H 6000 5400 30 0000 C CNN +F 2 "" H 6000 5400 60 0000 C CNN +F 3 "" H 6000 5400 60 0000 C CNN + 19 6000 5400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 20 1 6666398E +P 6000 6000 +F 0 "U1" H 6050 6100 30 0000 C CNN +F 1 "PORT" H 6000 6000 30 0000 C CNN +F 2 "" H 6000 6000 60 0000 C CNN +F 3 "" H 6000 6000 60 0000 C CNN + 20 6000 6000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 21 1 666639E9 +P 6000 6600 +F 0 "U1" H 6050 6700 30 0000 C CNN +F 1 "PORT" H 6000 6600 30 0000 C CNN +F 2 "" H 6000 6600 60 0000 C CNN +F 3 "" H 6000 6600 60 0000 C CNN + 21 6000 6600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 22 1 66663A46 +P 6000 7200 +F 0 "U1" H 6050 7300 30 0000 C CNN +F 1 "PORT" H 6000 7200 30 0000 C CNN +F 2 "" H 6000 7200 60 0000 C CNN +F 3 "" H 6000 7200 60 0000 C CNN + 22 6000 7200 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/FCT827/FCT827.sub b/library/SubcircuitLibrary/FCT827/FCT827.sub new file mode 100644 index 00000000..ba51bdf9 --- /dev/null +++ b/library/SubcircuitLibrary/FCT827/FCT827.sub @@ -0,0 +1,58 @@ +* Subcircuit FCT827 +.subckt FCT827 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ +* c:\fossee\esim\library\subcircuitlibrary\fct827\fct827.cir +* u4 net-_u2-pad2_ net-_u3-pad2_ net-_u10-pad2_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u5 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad13_ d_tristate +* u6 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad14_ d_tristate +* u7 net-_u1-pad5_ net-_u10-pad2_ net-_u1-pad15_ d_tristate +* u8 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad16_ d_tristate +* u9 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad17_ d_tristate +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad18_ d_tristate +* u11 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad19_ d_tristate +* u12 net-_u1-pad10_ net-_u10-pad2_ net-_u1-pad20_ d_tristate +* u13 net-_u1-pad11_ net-_u10-pad2_ net-_u1-pad21_ d_tristate +* u14 net-_u1-pad12_ net-_u10-pad2_ net-_u1-pad22_ d_tristate +a1 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u10-pad2_ u4 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 net-_u1-pad2_ net-_u3-pad2_ u3 +a4 net-_u1-pad3_ net-_u10-pad2_ net-_u1-pad13_ u5 +a5 net-_u1-pad4_ net-_u10-pad2_ net-_u1-pad14_ u6 +a6 net-_u1-pad5_ net-_u10-pad2_ net-_u1-pad15_ u7 +a7 net-_u1-pad6_ net-_u10-pad2_ net-_u1-pad16_ u8 +a8 net-_u1-pad7_ net-_u10-pad2_ net-_u1-pad17_ u9 +a9 net-_u1-pad8_ net-_u10-pad2_ net-_u1-pad18_ u10 +a10 net-_u1-pad9_ net-_u10-pad2_ net-_u1-pad19_ u11 +a11 net-_u1-pad10_ net-_u10-pad2_ net-_u1-pad20_ u12 +a12 net-_u1-pad11_ net-_u10-pad2_ net-_u1-pad21_ u13 +a13 net-_u1-pad12_ net-_u10-pad2_ net-_u1-pad22_ u14 +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u5 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u7 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u9 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Control Statements + +.ends FCT827
\ No newline at end of file diff --git a/library/SubcircuitLibrary/FCT827/FCT827_Previous_Values.xml b/library/SubcircuitLibrary/FCT827/FCT827_Previous_Values.xml new file mode 100644 index 00000000..0677af1e --- /dev/null +++ b/library/SubcircuitLibrary/FCT827/FCT827_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">1</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u4 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u4><u2 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_tristate<field10 name="Enter Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Enable Load (default=1.0e-12)" /></u5><u6 name="type">d_tristate<field13 name="Enter Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Enable Load (default=1.0e-12)" /></u6><u7 name="type">d_tristate<field16 name="Enter Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Enable Load (default=1.0e-12)" /></u7><u8 name="type">d_tristate<field19 name="Enter Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Enable Load (default=1.0e-12)" /></u8><u9 name="type">d_tristate<field22 name="Enter Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Enable Load (default=1.0e-12)" /></u9><u10 name="type">d_tristate<field25 name="Enter Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Enable Load (default=1.0e-12)" /></u10><u11 name="type">d_tristate<field28 name="Enter Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Enable Load (default=1.0e-12)" /></u11><u12 name="type">d_tristate<field31 name="Enter Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Enable Load (default=1.0e-12)" /></u12><u13 name="type">d_tristate<field34 name="Enter Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Enable Load (default=1.0e-12)" /></u13><u14 name="type">d_tristate<field37 name="Enter Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Enable Load (default=1.0e-12)" /></u14></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/FCT827/analysis b/library/SubcircuitLibrary/FCT827/analysis new file mode 100644 index 00000000..55ca3c83 --- /dev/null +++ b/library/SubcircuitLibrary/FCT827/analysis @@ -0,0 +1 @@ +.tran 10e-03 1e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit-cache.lib b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit-cache.lib new file mode 100644 index 00000000..c3224acc --- /dev/null +++ b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit-cache.lib @@ -0,0 +1,142 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.cir b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.cir new file mode 100644 index 00000000..e2f86af7 --- /dev/null +++ b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.cir @@ -0,0 +1,99 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM124_SUBcircuit\LM124_SUBcircuit.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 09/09/24 22:06:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q4 Net-_Q4-Pad1_ Net-_Q2-Pad3_ Net-_I2-Pad2_ eSim_PNP +Q10 Net-_C2-Pad2_ Net-_Q10-Pad2_ Net-_I2-Pad2_ eSim_PNP +Q12 Net-_I10-Pad2_ Net-_Q12-Pad2_ Net-_Q10-Pad2_ eSim_PNP +Q2 Net-_I10-Pad2_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_PNP +Q6 Net-_Q4-Pad1_ Net-_Q4-Pad1_ Net-_I10-Pad2_ eSim_NPN +Q8 Net-_C2-Pad2_ Net-_Q4-Pad1_ Net-_I10-Pad2_ eSim_NPN +R2 Net-_R2-Pad1_ Net-_Q2-Pad2_ 2k +I2 Net-_I1-Pad1_ Net-_I2-Pad2_ 6uA +I4 Net-_I1-Pad1_ Net-_I4-Pad2_ 4uA +I8 Net-_I1-Pad1_ Net-_C2-Pad1_ 100uA +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 20pF +Q14 Net-_I10-Pad2_ Net-_C2-Pad2_ Net-_I4-Pad2_ eSim_PNP +Q16 Net-_I1-Pad1_ Net-_I4-Pad2_ Net-_I6-Pad1_ eSim_NPN +I6 Net-_I6-Pad1_ Net-_I10-Pad2_ 50uA +Q18 Net-_C2-Pad1_ Net-_I6-Pad1_ Net-_I10-Pad2_ eSim_NPN +Q22 Net-_I1-Pad1_ Net-_C2-Pad1_ Net-_Q22-Pad3_ eSim_NPN +Q20 Net-_C2-Pad1_ Net-_Q20-Pad2_ Net-_I10-Pad1_ eSim_NPN +Q25 Net-_I1-Pad1_ Net-_Q22-Pad3_ Net-_Q20-Pad2_ eSim_NPN +I10 Net-_I10-Pad1_ Net-_I10-Pad2_ 50uA +R6 Net-_Q20-Pad2_ Net-_I10-Pad1_ 500 +Q26 Net-_I10-Pad2_ Net-_C2-Pad1_ Net-_I10-Pad1_ eSim_PNP +R4 Net-_Q2-Pad2_ Net-_I10-Pad1_ 10k +Q29 Net-_Q29-Pad1_ Net-_Q27-Pad3_ Net-_I11-Pad2_ eSim_PNP +Q34 Net-_C3-Pad2_ Net-_Q34-Pad2_ Net-_I11-Pad2_ eSim_PNP +Q37 Net-_I10-Pad2_ Net-_Q37-Pad2_ Net-_Q34-Pad2_ eSim_PNP +Q27 Net-_I10-Pad2_ Net-_Q27-Pad2_ Net-_Q27-Pad3_ eSim_PNP +Q30 Net-_Q29-Pad1_ Net-_Q29-Pad1_ Net-_I10-Pad2_ eSim_NPN +Q33 Net-_C3-Pad2_ Net-_Q29-Pad1_ Net-_I10-Pad2_ eSim_NPN +R7 Net-_R7-Pad1_ Net-_Q27-Pad2_ 2k +I11 Net-_I1-Pad1_ Net-_I11-Pad2_ 6uA +I13 Net-_I1-Pad1_ Net-_I13-Pad2_ 4uA +I17 Net-_I1-Pad1_ Net-_C3-Pad1_ 100uA +C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 20pF +Q39 Net-_I10-Pad2_ Net-_C3-Pad2_ Net-_I13-Pad2_ eSim_PNP +Q41 Net-_I1-Pad1_ Net-_I13-Pad2_ Net-_I15-Pad1_ eSim_NPN +I15 Net-_I15-Pad1_ Net-_I10-Pad2_ 50uA +Q43 Net-_C3-Pad1_ Net-_I15-Pad1_ Net-_I10-Pad2_ eSim_NPN +Q47 Net-_I1-Pad1_ Net-_C3-Pad1_ Net-_Q47-Pad3_ eSim_NPN +Q45 Net-_C3-Pad1_ Net-_Q45-Pad2_ Net-_I18-Pad1_ eSim_NPN +Q49 Net-_I1-Pad1_ Net-_Q47-Pad3_ Net-_Q45-Pad2_ eSim_NPN +I18 Net-_I18-Pad1_ Net-_I10-Pad2_ 50uA +R11 Net-_Q45-Pad2_ Net-_I18-Pad1_ 500 +Q50 Net-_I10-Pad2_ Net-_C3-Pad1_ Net-_I18-Pad1_ eSim_PNP +R9 Net-_Q27-Pad2_ Net-_I18-Pad1_ 10k +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad3_ Net-_I1-Pad2_ eSim_PNP +Q9 Net-_C1-Pad2_ Net-_Q11-Pad3_ Net-_I1-Pad2_ eSim_PNP +Q11 Net-_I10-Pad2_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_PNP +Q1 Net-_I10-Pad2_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_Q3-Pad1_ Net-_Q3-Pad1_ Net-_I10-Pad2_ eSim_NPN +Q7 Net-_C1-Pad2_ Net-_Q3-Pad1_ Net-_I10-Pad2_ eSim_NPN +R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 2k +I1 Net-_I1-Pad1_ Net-_I1-Pad2_ 6uA +I3 Net-_I1-Pad1_ Net-_I3-Pad2_ 4uA +I7 Net-_I1-Pad1_ Net-_C1-Pad1_ 100uA +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 20pF +Q13 Net-_I10-Pad2_ Net-_C1-Pad2_ Net-_I3-Pad2_ eSim_PNP +Q15 Net-_I1-Pad1_ Net-_I3-Pad2_ Net-_I5-Pad1_ eSim_NPN +I5 Net-_I5-Pad1_ Net-_I10-Pad2_ 50uA +Q17 Net-_C1-Pad1_ Net-_I5-Pad1_ Net-_I10-Pad2_ eSim_NPN +Q21 Net-_I1-Pad1_ Net-_C1-Pad1_ Net-_Q21-Pad3_ eSim_NPN +Q19 Net-_C1-Pad1_ Net-_Q19-Pad2_ Net-_I9-Pad1_ eSim_NPN +Q23 Net-_I1-Pad1_ Net-_Q21-Pad3_ Net-_Q19-Pad2_ eSim_NPN +I9 Net-_I9-Pad1_ Net-_I10-Pad2_ 50uA +R5 Net-_Q19-Pad2_ Net-_I9-Pad1_ 500 +Q24 Net-_I10-Pad2_ Net-_C1-Pad1_ Net-_I9-Pad1_ eSim_PNP +R3 Net-_Q1-Pad2_ Net-_I9-Pad1_ 10k +Q31 Net-_Q31-Pad1_ Net-_Q28-Pad3_ Net-_I12-Pad2_ eSim_PNP +Q36 Net-_C4-Pad2_ Net-_Q36-Pad2_ Net-_I12-Pad2_ eSim_PNP +Q38 Net-_I10-Pad2_ Net-_Q38-Pad2_ Net-_Q36-Pad2_ eSim_PNP +Q28 Net-_I10-Pad2_ Net-_Q28-Pad2_ Net-_Q28-Pad3_ eSim_PNP +Q32 Net-_Q31-Pad1_ Net-_Q31-Pad1_ Net-_I10-Pad2_ eSim_NPN +Q35 Net-_C4-Pad2_ Net-_Q31-Pad1_ Net-_I10-Pad2_ eSim_NPN +R8 Net-_R8-Pad1_ Net-_Q28-Pad2_ 2k +I12 Net-_I1-Pad1_ Net-_I12-Pad2_ 6uA +I14 Net-_I1-Pad1_ Net-_I14-Pad2_ 4uA +I19 Net-_I1-Pad1_ Net-_C4-Pad1_ 100uA +C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 20pF +Q40 Net-_I10-Pad2_ Net-_C4-Pad2_ Net-_I14-Pad2_ eSim_PNP +Q42 Net-_I1-Pad1_ Net-_I14-Pad2_ Net-_I16-Pad1_ eSim_NPN +I16 Net-_I16-Pad1_ Net-_I10-Pad2_ 50uA +Q44 Net-_C4-Pad1_ Net-_I16-Pad1_ Net-_I10-Pad2_ eSim_NPN +Q48 Net-_I1-Pad1_ Net-_C4-Pad1_ Net-_Q48-Pad3_ eSim_NPN +Q46 Net-_C4-Pad1_ Net-_Q46-Pad2_ Net-_I20-Pad1_ eSim_NPN +Q51 Net-_I1-Pad1_ Net-_Q48-Pad3_ Net-_Q46-Pad2_ eSim_NPN +I20 Net-_I20-Pad1_ Net-_I10-Pad2_ 50uA +R12 Net-_Q46-Pad2_ Net-_I20-Pad1_ 500 +Q52 Net-_I10-Pad2_ Net-_C4-Pad1_ Net-_I20-Pad1_ eSim_PNP +R10 Net-_Q28-Pad2_ Net-_I20-Pad1_ 10k +U1 Net-_I10-Pad1_ Net-_R2-Pad1_ Net-_Q12-Pad2_ Net-_I1-Pad1_ Net-_Q37-Pad2_ Net-_R7-Pad1_ Net-_I18-Pad1_ Net-_I9-Pad1_ Net-_R1-Pad1_ Net-_Q11-Pad2_ Net-_I10-Pad2_ Net-_Q38-Pad2_ Net-_R8-Pad1_ Net-_I20-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.cir.out b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.cir.out new file mode 100644 index 00000000..5fd16761 --- /dev/null +++ b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.cir.out @@ -0,0 +1,102 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm124_subcircuit\lm124_subcircuit.cir + +.include PNP.lib +.include NPN.lib +q4 net-_q4-pad1_ net-_q2-pad3_ net-_i2-pad2_ Q2N2907A +q10 net-_c2-pad2_ net-_q10-pad2_ net-_i2-pad2_ Q2N2907A +q12 net-_i10-pad2_ net-_q12-pad2_ net-_q10-pad2_ Q2N2907A +q2 net-_i10-pad2_ net-_q2-pad2_ net-_q2-pad3_ Q2N2907A +q6 net-_q4-pad1_ net-_q4-pad1_ net-_i10-pad2_ Q2N2222 +q8 net-_c2-pad2_ net-_q4-pad1_ net-_i10-pad2_ Q2N2222 +r2 net-_r2-pad1_ net-_q2-pad2_ 2k +i2 net-_i1-pad1_ net-_i2-pad2_ 6ua +i4 net-_i1-pad1_ net-_i4-pad2_ 4ua +i8 net-_i1-pad1_ net-_c2-pad1_ 100ua +c2 net-_c2-pad1_ net-_c2-pad2_ 20pf +q14 net-_i10-pad2_ net-_c2-pad2_ net-_i4-pad2_ Q2N2907A +q16 net-_i1-pad1_ net-_i4-pad2_ net-_i6-pad1_ Q2N2222 +i6 net-_i6-pad1_ net-_i10-pad2_ 50ua +q18 net-_c2-pad1_ net-_i6-pad1_ net-_i10-pad2_ Q2N2222 +q22 net-_i1-pad1_ net-_c2-pad1_ net-_q22-pad3_ Q2N2222 +q20 net-_c2-pad1_ net-_q20-pad2_ net-_i10-pad1_ Q2N2222 +q25 net-_i1-pad1_ net-_q22-pad3_ net-_q20-pad2_ Q2N2222 +i10 net-_i10-pad1_ net-_i10-pad2_ 50ua +r6 net-_q20-pad2_ net-_i10-pad1_ 500 +q26 net-_i10-pad2_ net-_c2-pad1_ net-_i10-pad1_ Q2N2907A +r4 net-_q2-pad2_ net-_i10-pad1_ 10k +q29 net-_q29-pad1_ net-_q27-pad3_ net-_i11-pad2_ Q2N2907A +q34 net-_c3-pad2_ net-_q34-pad2_ net-_i11-pad2_ Q2N2907A +q37 net-_i10-pad2_ net-_q37-pad2_ net-_q34-pad2_ Q2N2907A +q27 net-_i10-pad2_ net-_q27-pad2_ net-_q27-pad3_ Q2N2907A +q30 net-_q29-pad1_ net-_q29-pad1_ net-_i10-pad2_ Q2N2222 +q33 net-_c3-pad2_ net-_q29-pad1_ net-_i10-pad2_ Q2N2222 +r7 net-_r7-pad1_ net-_q27-pad2_ 2k +i11 net-_i1-pad1_ net-_i11-pad2_ 6ua +i13 net-_i1-pad1_ net-_i13-pad2_ 4ua +i17 net-_i1-pad1_ net-_c3-pad1_ 100ua +c3 net-_c3-pad1_ net-_c3-pad2_ 20pf +q39 net-_i10-pad2_ net-_c3-pad2_ net-_i13-pad2_ Q2N2907A +q41 net-_i1-pad1_ net-_i13-pad2_ net-_i15-pad1_ Q2N2222 +i15 net-_i15-pad1_ net-_i10-pad2_ 50ua +q43 net-_c3-pad1_ net-_i15-pad1_ net-_i10-pad2_ Q2N2222 +q47 net-_i1-pad1_ net-_c3-pad1_ net-_q47-pad3_ Q2N2222 +q45 net-_c3-pad1_ net-_q45-pad2_ net-_i18-pad1_ Q2N2222 +q49 net-_i1-pad1_ net-_q47-pad3_ net-_q45-pad2_ Q2N2222 +i18 net-_i18-pad1_ net-_i10-pad2_ 50ua +r11 net-_q45-pad2_ net-_i18-pad1_ 500 +q50 net-_i10-pad2_ net-_c3-pad1_ net-_i18-pad1_ Q2N2907A +r9 net-_q27-pad2_ net-_i18-pad1_ 10k +q3 net-_q3-pad1_ net-_q1-pad3_ net-_i1-pad2_ Q2N2907A +q9 net-_c1-pad2_ net-_q11-pad3_ net-_i1-pad2_ Q2N2907A +q11 net-_i10-pad2_ net-_q11-pad2_ net-_q11-pad3_ Q2N2907A +q1 net-_i10-pad2_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q5 net-_q3-pad1_ net-_q3-pad1_ net-_i10-pad2_ Q2N2222 +q7 net-_c1-pad2_ net-_q3-pad1_ net-_i10-pad2_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 2k +i1 net-_i1-pad1_ net-_i1-pad2_ 6ua +i3 net-_i1-pad1_ net-_i3-pad2_ 4ua +i7 net-_i1-pad1_ net-_c1-pad1_ 100ua +c1 net-_c1-pad1_ net-_c1-pad2_ 20pf +q13 net-_i10-pad2_ net-_c1-pad2_ net-_i3-pad2_ Q2N2907A +q15 net-_i1-pad1_ net-_i3-pad2_ net-_i5-pad1_ Q2N2222 +i5 net-_i5-pad1_ net-_i10-pad2_ 50ua +q17 net-_c1-pad1_ net-_i5-pad1_ net-_i10-pad2_ Q2N2222 +q21 net-_i1-pad1_ net-_c1-pad1_ net-_q21-pad3_ Q2N2222 +q19 net-_c1-pad1_ net-_q19-pad2_ net-_i9-pad1_ Q2N2222 +q23 net-_i1-pad1_ net-_q21-pad3_ net-_q19-pad2_ Q2N2222 +i9 net-_i9-pad1_ net-_i10-pad2_ 50ua +r5 net-_q19-pad2_ net-_i9-pad1_ 500 +q24 net-_i10-pad2_ net-_c1-pad1_ net-_i9-pad1_ Q2N2907A +r3 net-_q1-pad2_ net-_i9-pad1_ 10k +q31 net-_q31-pad1_ net-_q28-pad3_ net-_i12-pad2_ Q2N2907A +q36 net-_c4-pad2_ net-_q36-pad2_ net-_i12-pad2_ Q2N2907A +q38 net-_i10-pad2_ net-_q38-pad2_ net-_q36-pad2_ Q2N2907A +q28 net-_i10-pad2_ net-_q28-pad2_ net-_q28-pad3_ Q2N2907A +q32 net-_q31-pad1_ net-_q31-pad1_ net-_i10-pad2_ Q2N2222 +q35 net-_c4-pad2_ net-_q31-pad1_ net-_i10-pad2_ Q2N2222 +r8 net-_r8-pad1_ net-_q28-pad2_ 2k +i12 net-_i1-pad1_ net-_i12-pad2_ 6ua +i14 net-_i1-pad1_ net-_i14-pad2_ 4ua +i19 net-_i1-pad1_ net-_c4-pad1_ 100ua +c4 net-_c4-pad1_ net-_c4-pad2_ 20pf +q40 net-_i10-pad2_ net-_c4-pad2_ net-_i14-pad2_ Q2N2907A +q42 net-_i1-pad1_ net-_i14-pad2_ net-_i16-pad1_ Q2N2222 +i16 net-_i16-pad1_ net-_i10-pad2_ 50ua +q44 net-_c4-pad1_ net-_i16-pad1_ net-_i10-pad2_ Q2N2222 +q48 net-_i1-pad1_ net-_c4-pad1_ net-_q48-pad3_ Q2N2222 +q46 net-_c4-pad1_ net-_q46-pad2_ net-_i20-pad1_ Q2N2222 +q51 net-_i1-pad1_ net-_q48-pad3_ net-_q46-pad2_ Q2N2222 +i20 net-_i20-pad1_ net-_i10-pad2_ 50ua +r12 net-_q46-pad2_ net-_i20-pad1_ 500 +q52 net-_i10-pad2_ net-_c4-pad1_ net-_i20-pad1_ Q2N2907A +r10 net-_q28-pad2_ net-_i20-pad1_ 10k +* u1 net-_i10-pad1_ net-_r2-pad1_ net-_q12-pad2_ net-_i1-pad1_ net-_q37-pad2_ net-_r7-pad1_ net-_i18-pad1_ net-_i9-pad1_ net-_r1-pad1_ net-_q11-pad2_ net-_i10-pad2_ net-_q38-pad2_ net-_r8-pad1_ net-_i20-pad1_ port +.tran 0.1e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.pro b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.sch b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.sch new file mode 100644 index 00000000..b53219c3 --- /dev/null +++ b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.sch @@ -0,0 +1,1901 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM124_opamp-cache +EELAYER 25 0 +EELAYER END +$Descr User 24835 17731 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q4 +U 1 1 66DD4C52 +P 3400 4450 +F 0 "Q4" H 3300 4500 50 0000 R CNN +F 1 "eSim_PNP" H 3350 4600 50 0000 R CNN +F 2 "" H 3600 4550 29 0000 C CNN +F 3 "" H 3400 4450 60 0000 C CNN + 1 3400 4450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 66DD4C53 +P 4600 4450 +F 0 "Q10" H 4500 4500 50 0000 R CNN +F 1 "eSim_PNP" H 4550 4600 50 0000 R CNN +F 2 "" H 4800 4550 29 0000 C CNN +F 3 "" H 4600 4450 60 0000 C CNN + 1 4600 4450 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 66DD4C54 +P 5300 5250 +F 0 "Q12" H 5200 5300 50 0000 R CNN +F 1 "eSim_PNP" H 5250 5400 50 0000 R CNN +F 2 "" H 5500 5350 29 0000 C CNN +F 3 "" H 5300 5250 60 0000 C CNN + 1 5300 5250 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 66DD4C55 +P 2600 5200 +F 0 "Q2" H 2500 5250 50 0000 R CNN +F 1 "eSim_PNP" H 2550 5350 50 0000 R CNN +F 2 "" H 2800 5300 29 0000 C CNN +F 3 "" H 2600 5200 60 0000 C CNN + 1 2600 5200 + 1 0 0 1 +$EndComp +Wire Wire Line + 3500 4250 3500 3800 +Wire Wire Line + 3500 3800 4500 3800 +Wire Wire Line + 4500 3800 4500 4250 +Wire Wire Line + 2700 5000 2700 4450 +Wire Wire Line + 2700 4450 3200 4450 +Wire Wire Line + 4800 4450 5200 4450 +Wire Wire Line + 5200 4450 5200 5050 +$Comp +L eSim_NPN Q6 +U 1 1 66DD4C56 +P 3600 6500 +F 0 "Q6" H 3500 6550 50 0000 R CNN +F 1 "eSim_NPN" H 3550 6650 50 0000 R CNN +F 2 "" H 3800 6600 29 0000 C CNN +F 3 "" H 3600 6500 60 0000 C CNN + 1 3600 6500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 66DD4C57 +P 4400 6500 +F 0 "Q8" H 4300 6550 50 0000 R CNN +F 1 "eSim_NPN" H 4350 6650 50 0000 R CNN +F 2 "" H 4600 6600 29 0000 C CNN +F 3 "" H 4400 6500 60 0000 C CNN + 1 4400 6500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 4650 3500 6300 +Wire Wire Line + 4500 4650 4500 6300 +Wire Wire Line + 3800 6500 4200 6500 +Wire Wire Line + 3500 6700 3500 7350 +Wire Wire Line + 2000 7350 10600 7350 +Wire Wire Line + 4500 7350 4500 6700 +Wire Wire Line + 2700 5400 2700 7350 +Connection ~ 3500 7350 +Wire Wire Line + 5200 7350 5200 5450 +Connection ~ 4500 7350 +Wire Wire Line + 5500 5250 6000 5250 +Wire Wire Line + 6000 5250 6000 5850 +Wire Wire Line + 6000 5850 2250 5850 +$Comp +L resistor R2 +U 1 1 66DD4C58 +P 2000 5250 +F 0 "R2" H 2050 5380 50 0000 C CNN +F 1 "2k" H 2050 5200 50 0000 C CNN +F 2 "" H 2050 5230 30 0000 C CNN +F 3 "" V 2050 5300 30 0000 C CNN + 1 2000 5250 + 1 0 0 -1 +$EndComp +$Comp +L dc I2 +U 1 1 66DD4C5C +P 4000 3150 +F 0 "I2" H 3800 3250 60 0000 C CNN +F 1 "6uA" H 3800 3100 60 0000 C CNN +F 2 "R1" H 3700 3150 60 0000 C CNN +F 3 "" H 4000 3150 60 0000 C CNN + 1 4000 3150 + 1 0 0 -1 +$EndComp +$Comp +L dc I4 +U 1 1 66DD4C5D +P 7700 3550 +F 0 "I4" H 7500 3650 60 0000 C CNN +F 1 "4uA" H 7500 3500 60 0000 C CNN +F 2 "R1" H 7400 3550 60 0000 C CNN +F 3 "" H 7700 3550 60 0000 C CNN + 1 7700 3550 + 1 0 0 -1 +$EndComp +$Comp +L dc I8 +U 1 1 66DD4C5E +P 9250 3500 +F 0 "I8" H 9050 3600 60 0000 C CNN +F 1 "100uA" H 9050 3450 60 0000 C CNN +F 2 "R1" H 8950 3500 60 0000 C CNN +F 3 "" H 9250 3500 60 0000 C CNN + 1 9250 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4000 3600 4000 3800 +Connection ~ 4000 3800 +$Comp +L capacitor C2 +U 1 1 66DD4C5F +P 7100 4950 +F 0 "C2" H 7125 5050 50 0000 L CNN +F 1 "20pF" H 7125 4850 50 0000 L CNN +F 2 "" H 7138 4800 30 0000 C CNN +F 3 "" H 7100 4950 60 0000 C CNN + 1 7100 4950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7100 6050 7100 5100 +$Comp +L eSim_PNP Q14 +U 1 1 66DD4C60 +P 7600 6050 +F 0 "Q14" H 7500 6100 50 0000 R CNN +F 1 "eSim_PNP" H 7550 6200 50 0000 R CNN +F 2 "" H 7800 6150 29 0000 C CNN +F 3 "" H 7600 6050 60 0000 C CNN + 1 7600 6050 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 66DD4C61 +P 8250 5400 +F 0 "Q16" H 8150 5450 50 0000 R CNN +F 1 "eSim_NPN" H 8200 5550 50 0000 R CNN +F 2 "" H 8450 5500 29 0000 C CNN +F 3 "" H 8250 5400 60 0000 C CNN + 1 8250 5400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 4000 7700 5850 +Wire Wire Line + 8050 5400 7700 5400 +Connection ~ 7700 5400 +Wire Wire Line + 8350 2100 8350 5200 +Wire Wire Line + 4000 2100 11500 2100 +Wire Wire Line + 4000 2100 4000 2700 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0 -1 +$EndComp +Wire Wire Line + 7550 11850 7550 13700 +Wire Wire Line + 7900 13250 7550 13250 +Connection ~ 7550 13250 +Wire Wire Line + 8200 9950 8200 13050 +Wire Wire Line + 3850 9950 11400 9950 +Wire Wire Line + 3850 9950 3850 10550 +Wire Wire Line + 7550 10950 7550 9950 +Connection ~ 7550 9950 +$Comp +L dc I5 +U 1 1 66DD8A51 +P 8200 14350 +F 0 "I5" H 8000 14450 60 0000 C CNN +F 1 "50uA" H 8000 14300 60 0000 C CNN +F 2 "R1" H 7900 14350 60 0000 C CNN +F 3 "" H 8200 14350 60 0000 C CNN + 1 8200 14350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8200 13450 8200 13900 +Wire Wire Line + 8200 15200 8200 14800 +Connection ~ 5050 15200 +Wire Wire Line + 7550 14100 7550 15200 +Connection ~ 7550 15200 +Connection ~ 6950 13900 +Wire Wire Line + 6950 12050 9750 12050 +Wire Wire Line + 6950 12650 6950 12050 +$Comp +L eSim_NPN Q17 +U 1 1 66DD8A5F +P 8850 13950 +F 0 "Q17" H 8750 14000 50 0000 R CNN +F 1 "eSim_NPN" H 8800 14100 50 0000 R CNN +F 2 "" H 9050 14050 29 0000 C CNN +F 3 "" H 8850 13950 60 0000 C CNN + 1 8850 13950 + 1 0 0 -1 +$EndComp +Connection ~ 8200 13600 +Wire Wire Line + 9100 11800 9100 13400 +Wire Wire Line + 9100 13400 8950 13400 +Connection ~ 8200 15200 +Wire Wire Line + 9100 9950 9100 10900 +Connection ~ 8200 9950 +Connection ~ 9100 12050 +$Comp +L eSim_NPN Q21 +U 1 1 66DD8A6C +P 9950 12050 +F 0 "Q21" H 9850 12100 50 0000 R CNN +F 1 "eSim_NPN" H 9900 12200 50 0000 R CNN +F 2 "" H 10150 12150 29 0000 C CNN +F 3 "" H 9950 12050 60 0000 C CNN + 1 9950 12050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 66DD8A72 +P 9500 12850 +F 0 "Q19" H 9400 12900 50 0000 R CNN +F 1 "eSim_NPN" H 9450 13000 50 0000 R CNN +F 2 "" H 9700 12950 29 0000 C CNN +F 3 "" H 9500 12850 60 0000 C CNN + 1 9500 12850 + -1 0 0 -1 +$EndComp +Connection ~ 9400 12050 +$Comp +L eSim_NPN Q23 +U 1 1 66DD8A79 +P 10350 12550 +F 0 "Q23" H 10250 12600 50 0000 R CNN +F 1 "eSim_NPN" H 10300 12700 50 0000 R CNN +F 2 "" H 10550 12650 29 0000 C CNN +F 3 "" H 10350 12550 60 0000 C CNN + 1 10350 12550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10050 12250 10050 12550 +Wire Wire Line + 10050 12550 10150 12550 +Wire Wire Line + 9400 13050 9400 14150 +$Comp +L dc I9 +U 1 1 66DD8A82 +P 9400 14600 +F 0 "I9" H 9200 14700 60 0000 C CNN +F 1 "50uA" H 9200 14550 60 0000 C CNN +F 2 "R1" H 9100 14600 60 0000 C CNN +F 3 "" H 9400 14600 60 0000 C CNN + 1 9400 14600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9400 15200 9400 15050 +Connection ~ 8950 15200 +Wire Wire Line + 9700 12850 10450 12850 +Wire Wire Line + 10450 12750 10450 13100 +Wire Wire Line + 9400 12650 9400 12050 +Wire Wire Line + 10050 9950 10050 11850 +Connection ~ 9100 9950 +Wire Wire Line + 10450 9950 10450 12350 +Connection ~ 10050 9950 +$Comp +L resistor R5 +U 1 1 66DD8A91 +P 10400 13200 +F 0 "R5" H 10450 13330 50 0000 C CNN +F 1 "500" H 10450 13150 50 0000 C CNN +F 2 "" H 10450 13180 30 0000 C CNN +F 3 "" V 10450 13250 30 0000 C CNN + 1 10400 13200 + 0 1 1 0 +$EndComp +Connection ~ 10450 12850 +$Comp +L eSim_PNP Q24 +U 1 1 66DD8A98 +P 10350 13800 +F 0 "Q24" H 10250 13850 50 0000 R CNN +F 1 "eSim_PNP" H 10300 13950 50 0000 R CNN +F 2 "" H 10550 13900 29 0000 C CNN +F 3 "" H 10350 13800 60 0000 C CNN + 1 10350 13800 + 1 0 0 1 +$EndComp +Wire Wire Line + 10450 13400 10450 13600 +Wire Wire Line + 9650 13800 10150 13800 +Wire Wire Line + 10450 15200 10450 14000 +Connection ~ 9400 15200 +Wire Wire Line + 8950 13400 8950 13750 +Wire Wire Line + 8650 13950 8450 13950 +Wire Wire Line + 8450 13950 8450 13600 +Wire Wire Line + 8450 13600 8200 13600 +Wire Wire Line + 8950 14150 8950 15200 +Wire Wire Line + 9650 13800 9650 13550 +Wire Wire Line + 9650 13550 8950 13550 +Connection ~ 8950 13550 +Wire Wire Line + 9400 13400 10200 13400 +Wire Wire Line + 10200 13400 10200 13500 +Connection ~ 9400 13400 +Connection ~ 10450 13500 +Connection ~ 10450 9950 +Wire Wire Line + 2050 13050 2250 13050 +Wire Wire Line + 2150 13050 2150 9600 +Wire Wire Line + 2150 9600 5450 9600 +Connection ~ 2150 13050 +$Comp +L resistor R3 +U 1 1 66DD8AB3 +P 5550 9650 +F 0 "R3" H 5600 9780 50 0000 C CNN +F 1 "10k" H 5600 9600 50 0000 C CNN +F 2 "" H 5600 9630 30 0000 C CNN +F 3 "" V 5600 9700 30 0000 C CNN + 1 5550 9650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10300 9600 5750 9600 +Wire Wire Line + 10300 9250 10300 9600 +Wire Wire Line + 10300 9250 11800 9250 +Wire Wire Line + 11800 9250 11800 12550 +Wire Wire Line + 11800 12550 10750 12550 +Wire Wire Line + 10750 12550 10750 13500 +Connection ~ 10750 13500 +Connection ~ 2550 15200 +Wire Wire Line + 3350 13900 3900 13900 +Wire Wire Line + 3900 13900 3900 14350 +Connection ~ 3900 14350 +Connection ~ 3350 13900 +Wire Wire Line + 7250 13900 4350 13900 +Connection ~ 4350 13900 +Wire Wire Line + 10200 13500 11000 13500 +Wire Wire Line + 1750 13050 1650 13050 +$Comp +L eSim_PNP Q31 +U 1 1 66DD8ED4 +P 14700 12150 +F 0 "Q31" H 14600 12200 50 0000 R CNN +F 1 "eSim_PNP" H 14650 12300 50 0000 R CNN +F 2 "" H 14900 12250 29 0000 C CNN +F 3 "" H 14700 12150 60 0000 C CNN + 1 14700 12150 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q36 +U 1 1 66DD8EDA +P 15900 12150 +F 0 "Q36" H 15800 12200 50 0000 R CNN +F 1 "eSim_PNP" H 15850 12300 50 0000 R CNN +F 2 "" H 16100 12250 29 0000 C CNN +F 3 "" H 15900 12150 60 0000 C CNN + 1 15900 12150 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q38 +U 1 1 66DD8EE0 +P 16600 12950 +F 0 "Q38" H 16500 13000 50 0000 R CNN +F 1 "eSim_PNP" H 16550 13100 50 0000 R CNN +F 2 "" H 16800 13050 29 0000 C CNN +F 3 "" H 16600 12950 60 0000 C CNN + 1 16600 12950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q28 +U 1 1 66DD8EE6 +P 13900 12900 +F 0 "Q28" H 13800 12950 50 0000 R CNN +F 1 "eSim_PNP" H 13850 13050 50 0000 R CNN +F 2 "" H 14100 13000 29 0000 C CNN +F 3 "" H 13900 12900 60 0000 C CNN + 1 13900 12900 + 1 0 0 1 +$EndComp +Wire Wire Line + 14800 11950 14800 11500 +Wire Wire Line + 14800 11500 15800 11500 +Wire Wire Line + 15800 11500 15800 11950 +Wire Wire Line + 14000 12700 14000 12150 +Wire Wire Line + 14000 12150 14500 12150 +Wire Wire Line + 16100 12150 16500 12150 +Wire Wire Line + 16500 12150 16500 12750 +$Comp +L eSim_NPN Q32 +U 1 1 66DD8EF3 +P 14900 14200 +F 0 "Q32" H 14800 14250 50 0000 R CNN +F 1 "eSim_NPN" H 14850 14350 50 0000 R CNN +F 2 "" H 15100 14300 29 0000 C CNN +F 3 "" H 14900 14200 60 0000 C CNN + 1 14900 14200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q35 +U 1 1 66DD8EF9 +P 15700 14200 +F 0 "Q35" H 15600 14250 50 0000 R CNN +F 1 "eSim_NPN" H 15650 14350 50 0000 R CNN +F 2 "" H 15900 14300 29 0000 C CNN +F 3 "" H 15700 14200 60 0000 C CNN + 1 15700 14200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14800 12350 14800 14000 +Wire Wire Line + 15800 12350 15800 14000 +Wire Wire Line + 15100 14200 15500 14200 +Wire Wire Line + 14800 14400 14800 15050 +Wire Wire Line + 13700 15050 21900 15050 +Wire Wire Line + 15800 15050 15800 14400 +Wire Wire Line + 14000 13100 14000 15050 +Connection ~ 14800 15050 +Wire Wire Line + 16500 15050 16500 13150 +Connection ~ 15800 15050 +Wire Wire Line + 16800 12950 17300 12950 +Wire Wire Line + 17300 12950 17300 13550 +Wire Wire Line + 17300 13550 13550 13550 +$Comp +L resistor R8 +U 1 1 66DD8F0C +P 13300 12950 +F 0 "R8" H 13350 13080 50 0000 C CNN +F 1 "2k" H 13350 12900 50 0000 C CNN +F 2 "" H 13350 12930 30 0000 C CNN +F 3 "" V 13350 13000 30 0000 C CNN + 1 13300 12950 + 1 0 0 -1 +$EndComp +$Comp +L dc I12 +U 1 1 66DD8F12 +P 15300 10850 +F 0 "I12" H 15100 10950 60 0000 C CNN +F 1 "6uA" H 15100 10800 60 0000 C CNN +F 2 "R1" H 15000 10850 60 0000 C CNN +F 3 "" H 15300 10850 60 0000 C CNN + 1 15300 10850 + 1 0 0 -1 +$EndComp +$Comp +L dc I14 +U 1 1 66DD8F18 +P 19000 11250 +F 0 "I14" H 18800 11350 60 0000 C CNN +F 1 "4uA" H 18800 11200 60 0000 C CNN +F 2 "R1" H 18700 11250 60 0000 C CNN +F 3 "" H 19000 11250 60 0000 C CNN + 1 19000 11250 + 1 0 0 -1 +$EndComp +$Comp +L dc I19 +U 1 1 66DD8F1E +P 20550 11200 +F 0 "I19" H 20350 11300 60 0000 C CNN +F 1 "100uA" H 20350 11150 60 0000 C CNN +F 2 "R1" H 20250 11200 60 0000 C CNN +F 3 "" H 20550 11200 60 0000 C CNN + 1 20550 11200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15300 11300 15300 11500 +Connection ~ 15300 11500 +$Comp +L capacitor C4 +U 1 1 66DD8F26 +P 18400 12650 +F 0 "C4" H 18425 12750 50 0000 L CNN +F 1 "20pF" H 18425 12550 50 0000 L CNN +F 2 "" H 18438 12500 30 0000 C CNN +F 3 "" H 18400 12650 60 0000 C CNN + 1 18400 12650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18400 13750 18400 12800 +$Comp +L eSim_PNP Q40 +U 1 1 66DD8F2D +P 18900 13750 +F 0 "Q40" H 18800 13800 50 0000 R CNN +F 1 "eSim_PNP" H 18850 13900 50 0000 R CNN +F 2 "" H 19100 13850 29 0000 C CNN +F 3 "" H 18900 13750 60 0000 C CNN + 1 18900 13750 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q42 +U 1 1 66DD8F33 +P 19550 13100 +F 0 "Q42" H 19450 13150 50 0000 R CNN +F 1 "eSim_NPN" H 19500 13250 50 0000 R CNN +F 2 "" H 19750 13200 29 0000 C CNN +F 3 "" H 19550 13100 60 0000 C CNN + 1 19550 13100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 19000 11700 19000 13550 +Wire Wire Line + 19350 13100 19000 13100 +Connection ~ 19000 13100 +Wire Wire Line + 19650 9800 19650 12900 +Wire Wire Line + 15300 9800 22600 9800 +Wire Wire Line + 15300 9800 15300 10400 +Wire Wire Line + 19000 10800 19000 9800 +Connection ~ 19000 9800 +$Comp +L dc I16 +U 1 1 66DD8F41 +P 19650 14200 +F 0 "I16" H 19450 14300 60 0000 C CNN +F 1 "50uA" H 19450 14150 60 0000 C CNN +F 2 "R1" H 19350 14200 60 0000 C CNN +F 3 "" H 19650 14200 60 0000 C CNN + 1 19650 14200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 19650 13300 19650 13750 +Wire Wire Line + 19650 15050 19650 14650 +Connection ~ 16500 15050 +Wire Wire Line + 19000 13950 19000 15050 +Connection ~ 19000 15050 +Connection ~ 18400 13750 +Wire Wire Line + 18400 11900 21200 11900 +Wire Wire Line + 18400 12500 18400 11900 +$Comp +L eSim_NPN Q44 +U 1 1 66DD8F4F +P 20300 13800 +F 0 "Q44" H 20200 13850 50 0000 R CNN +F 1 "eSim_NPN" H 20250 13950 50 0000 R CNN +F 2 "" H 20500 13900 29 0000 C CNN +F 3 "" H 20300 13800 60 0000 C CNN + 1 20300 13800 + 1 0 0 -1 +$EndComp +Connection ~ 19650 13450 +Wire Wire Line + 20550 11650 20550 13250 +Wire Wire Line + 20550 13250 20400 13250 +Connection ~ 19650 15050 +Wire Wire Line + 20550 9800 20550 10750 +Connection ~ 19650 9800 +Connection ~ 20550 11900 +$Comp +L eSim_NPN Q48 +U 1 1 66DD8F5C +P 21400 11900 +F 0 "Q48" H 21300 11950 50 0000 R CNN +F 1 "eSim_NPN" H 21350 12050 50 0000 R CNN +F 2 "" H 21600 12000 29 0000 C CNN +F 3 "" H 21400 11900 60 0000 C CNN + 1 21400 11900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q46 +U 1 1 66DD8F62 +P 20950 12700 +F 0 "Q46" H 20850 12750 50 0000 R CNN +F 1 "eSim_NPN" H 20900 12850 50 0000 R CNN +F 2 "" H 21150 12800 29 0000 C CNN +F 3 "" H 20950 12700 60 0000 C CNN + 1 20950 12700 + -1 0 0 -1 +$EndComp +Connection ~ 20850 11900 +$Comp +L eSim_NPN Q51 +U 1 1 66DD8F69 +P 21800 12400 +F 0 "Q51" H 21700 12450 50 0000 R CNN +F 1 "eSim_NPN" H 21750 12550 50 0000 R CNN +F 2 "" H 22000 12500 29 0000 C CNN +F 3 "" H 21800 12400 60 0000 C CNN + 1 21800 12400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 21500 12100 21500 12400 +Wire Wire Line + 21500 12400 21600 12400 +Wire Wire Line + 20850 12900 20850 14000 +$Comp +L dc I20 +U 1 1 66DD8F72 +P 20850 14450 +F 0 "I20" H 20650 14550 60 0000 C CNN +F 1 "50uA" H 20650 14400 60 0000 C CNN +F 2 "R1" H 20550 14450 60 0000 C CNN +F 3 "" H 20850 14450 60 0000 C CNN + 1 20850 14450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20850 15050 20850 14900 +Connection ~ 20400 15050 +Wire Wire Line + 21150 12700 21900 12700 +Wire Wire Line + 21900 12600 21900 12950 +Wire Wire Line + 20850 12500 20850 11900 +Wire Wire Line + 21500 9800 21500 11700 +Connection ~ 20550 9800 +Wire Wire Line + 21900 9800 21900 12200 +Connection ~ 21500 9800 +$Comp +L resistor R12 +U 1 1 66DD8F81 +P 21850 13050 +F 0 "R12" H 21900 13180 50 0000 C CNN +F 1 "500" H 21900 13000 50 0000 C CNN +F 2 "" H 21900 13030 30 0000 C CNN +F 3 "" V 21900 13100 30 0000 C CNN + 1 21850 13050 + 0 1 1 0 +$EndComp +Connection ~ 21900 12700 +$Comp +L eSim_PNP Q52 +U 1 1 66DD8F88 +P 21800 13650 +F 0 "Q52" H 21700 13700 50 0000 R CNN +F 1 "eSim_PNP" H 21750 13800 50 0000 R CNN +F 2 "" H 22000 13750 29 0000 C CNN +F 3 "" H 21800 13650 60 0000 C CNN + 1 21800 13650 + 1 0 0 1 +$EndComp +Wire Wire Line + 21900 13250 21900 13450 +Wire Wire Line + 21100 13650 21600 13650 +Wire Wire Line + 21900 15050 21900 13850 +Connection ~ 20850 15050 +Wire Wire Line + 20400 13250 20400 13600 +Wire Wire Line + 20100 13800 19900 13800 +Wire Wire Line + 19900 13800 19900 13450 +Wire Wire Line + 19900 13450 19650 13450 +Wire Wire Line + 20400 14000 20400 15050 +Wire Wire Line + 21100 13650 21100 13400 +Wire Wire Line + 21100 13400 20400 13400 +Connection ~ 20400 13400 +Wire Wire Line + 20850 13250 21650 13250 +Wire Wire Line + 21650 13250 21650 13350 +Connection ~ 20850 13250 +Connection ~ 21900 13350 +Connection ~ 21900 9800 +Wire Wire Line + 13500 12900 13700 12900 +Wire Wire Line + 13600 12900 13600 9450 +Wire Wire Line + 13600 9450 16900 9450 +Connection ~ 13600 12900 +$Comp +L resistor R10 +U 1 1 66DD8FA3 +P 17000 9500 +F 0 "R10" H 17050 9630 50 0000 C CNN +F 1 "10k" H 17050 9450 50 0000 C CNN +F 2 "" H 17050 9480 30 0000 C CNN +F 3 "" V 17050 9550 30 0000 C CNN + 1 17000 9500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 21750 9450 17200 9450 +Wire Wire Line + 21750 9100 21750 9450 +Wire Wire Line + 21750 9100 23250 9100 +Wire Wire Line + 23250 9100 23250 12400 +Wire Wire Line + 23250 12400 22200 12400 +Wire Wire Line + 22200 12400 22200 13350 +Connection ~ 22200 13350 +Wire Wire Line + 13700 15200 13700 15050 +Connection ~ 14000 15050 +Wire Wire Line + 14800 13750 15350 13750 +Wire Wire Line + 15350 13750 15350 14200 +Connection ~ 15350 14200 +Connection ~ 14800 13750 +Wire Wire Line + 18700 13750 15800 13750 +Connection ~ 15800 13750 +Wire Wire Line + 21650 13350 22450 13350 +Wire Wire Line + 13200 12900 13100 12900 +$Comp +L PORT U1 +U 7 1 66DD9014 +P 22400 5700 +F 0 "U1" H 22450 5800 30 0000 C CNN +F 1 "PORT" H 22400 5700 30 0000 C CNN +F 2 "" H 22400 5700 60 0000 C CNN +F 3 "" H 22400 5700 60 0000 C CNN + 7 22400 5700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 66DD93B0 +P 1550 5200 +F 0 "U1" H 1600 5300 30 0000 C CNN +F 1 "PORT" H 1550 5200 30 0000 C CNN +F 2 "" H 1550 5200 60 0000 C CNN +F 3 "" H 1550 5200 60 0000 C CNN + 2 1550 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 66DD9493 +P 13000 5900 +F 0 "U1" H 13050 6000 30 0000 C CNN +F 1 "PORT" H 13000 5900 30 0000 C CNN +F 2 "" H 13000 5900 60 0000 C CNN +F 3 "" H 13000 5900 60 0000 C CNN + 5 13000 5900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 66DD956A +P 2000 5850 +F 0 "U1" H 2050 5950 30 0000 C CNN +F 1 "PORT" H 2000 5850 30 0000 C CNN +F 2 "" H 2000 5850 60 0000 C CNN +F 3 "" H 2000 5850 60 0000 C CNN + 3 2000 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 66DD964B +P 1750 7350 +F 0 "U1" H 1800 7450 30 0000 C CNN +F 1 "PORT" H 1750 7350 30 0000 C CNN +F 2 "" H 1750 7350 60 0000 C CNN +F 3 "" H 1750 7350 60 0000 C CNN + 11 1750 7350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 66DD9738 +P 1400 13050 +F 0 "U1" H 1450 13150 30 0000 C CNN +F 1 "PORT" H 1400 13050 30 0000 C CNN +F 2 "" H 1400 13050 60 0000 C CNN +F 3 "" H 1400 13050 60 0000 C CNN + 9 1400 13050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 66DD981F +P 12850 12900 +F 0 "U1" H 12900 13000 30 0000 C CNN +F 1 "PORT" H 12850 12900 30 0000 C CNN +F 2 "" H 12850 12900 60 0000 C CNN +F 3 "" H 12850 12900 60 0000 C CNN + 13 12850 12900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 66DD98FC +P 12550 5250 +F 0 "U1" H 12600 5350 30 0000 C CNN +F 1 "PORT" H 12550 5250 30 0000 C CNN +F 2 "" H 12550 5250 60 0000 C CNN +F 3 "" H 12550 5250 60 0000 C CNN + 6 12550 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 66DD9A01 +P 11400 5650 +F 0 "U1" H 11450 5750 30 0000 C CNN +F 1 "PORT" H 11400 5650 30 0000 C CNN +F 2 "" H 11400 5650 60 0000 C CNN +F 3 "" H 11400 5650 60 0000 C CNN + 1 11400 5650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 66DD9DA5 +P 11750 2100 +F 0 "U1" H 11800 2200 30 0000 C CNN +F 1 "PORT" H 11750 2100 30 0000 C CNN +F 2 "" H 11750 2100 60 0000 C CNN +F 3 "" H 11750 2100 60 0000 C CNN + 4 11750 2100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 66DD9EFC +P 11250 13500 +F 0 "U1" H 11300 13600 30 0000 C CNN +F 1 "PORT" H 11250 13500 30 0000 C CNN +F 2 "" H 11250 13500 60 0000 C CNN +F 3 "" H 11250 13500 60 0000 C CNN + 8 11250 13500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 66DD9FFB +P 13300 13550 +F 0 "U1" H 13350 13650 30 0000 C CNN +F 1 "PORT" H 13300 13550 30 0000 C CNN +F 2 "" H 13300 13550 60 0000 C CNN +F 3 "" H 13300 13550 60 0000 C CNN + 12 13300 13550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 66DDA0F2 +P 1850 13700 +F 0 "U1" H 1900 13800 30 0000 C CNN +F 1 "PORT" H 1850 13700 30 0000 C CNN +F 2 "" H 1850 13700 60 0000 C CNN +F 3 "" H 1850 13700 60 0000 C CNN + 10 1850 13700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 66DDA1F1 +P 22700 13350 +F 0 "U1" H 22750 13450 30 0000 C CNN +F 1 "PORT" H 22700 13350 30 0000 C CNN +F 2 "" H 22700 13350 60 0000 C CNN +F 3 "" H 22700 13350 60 0000 C CNN + 14 22700 13350 + -1 0 0 1 +$EndComp +Wire Wire Line + 11850 7400 11850 7750 +Wire Wire Line + 11850 7750 2600 7750 +Wire Wire Line + 2600 7750 2600 7350 +Connection ~ 2600 7350 +Wire Wire Line + 1000 15200 1000 9600 +Wire Wire Line + 1000 9600 1950 9600 +Wire Wire Line + 1950 9600 1950 7850 +Wire Wire Line + 1950 7850 2450 7850 +Wire Wire Line + 2450 7850 2450 7350 +Connection ~ 2450 7350 +Wire Wire Line + 12400 15200 13700 15200 +Wire Wire Line + 12400 8000 12400 15200 +Wire Wire Line + 2550 8000 12400 8000 +Wire Wire Line + 2550 8000 2550 7350 +Connection ~ 2550 7350 +Wire Wire Line + 22400 2150 22400 1100 +Wire Wire Line + 22400 1100 11400 1100 +Wire Wire Line + 11400 1100 11400 2100 +Connection ~ 11400 2100 +Wire Wire Line + 11400 9950 11400 6050 +Wire Wire Line + 11400 6050 11650 6050 +Wire Wire Line + 11650 6050 11650 2400 +Wire Wire Line + 11650 2400 11250 2400 +Wire Wire Line + 11250 2400 11250 2100 +Connection ~ 11250 2100 +Wire Wire Line + 22600 9800 22600 8700 +Wire Wire Line + 22600 8700 12200 8700 +Wire Wire Line + 12200 8700 12200 3200 +Wire Wire Line + 12200 3200 11150 3200 +Wire Wire Line + 11150 3200 11150 2100 +Connection ~ 11150 2100 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.sub b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.sub new file mode 100644 index 00000000..2ba32b5f --- /dev/null +++ b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit.sub @@ -0,0 +1,96 @@ +* Subcircuit LM124_SUBcircuit +.subckt LM124_SUBcircuit net-_i10-pad1_ net-_r2-pad1_ net-_q12-pad2_ net-_i1-pad1_ net-_q37-pad2_ net-_r7-pad1_ net-_i18-pad1_ net-_i9-pad1_ net-_r1-pad1_ net-_q11-pad2_ net-_i10-pad2_ net-_q38-pad2_ net-_r8-pad1_ net-_i20-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\lm124_subcircuit\lm124_subcircuit.cir +.include PNP.lib +.include NPN.lib +q4 net-_q4-pad1_ net-_q2-pad3_ net-_i2-pad2_ Q2N2907A +q10 net-_c2-pad2_ net-_q10-pad2_ net-_i2-pad2_ Q2N2907A +q12 net-_i10-pad2_ net-_q12-pad2_ net-_q10-pad2_ Q2N2907A +q2 net-_i10-pad2_ net-_q2-pad2_ net-_q2-pad3_ Q2N2907A +q6 net-_q4-pad1_ net-_q4-pad1_ net-_i10-pad2_ Q2N2222 +q8 net-_c2-pad2_ net-_q4-pad1_ net-_i10-pad2_ Q2N2222 +r2 net-_r2-pad1_ net-_q2-pad2_ 2k +i2 net-_i1-pad1_ net-_i2-pad2_ 6ua +i4 net-_i1-pad1_ net-_i4-pad2_ 4ua +i8 net-_i1-pad1_ net-_c2-pad1_ 100ua +c2 net-_c2-pad1_ net-_c2-pad2_ 20pf +q14 net-_i10-pad2_ net-_c2-pad2_ net-_i4-pad2_ Q2N2907A +q16 net-_i1-pad1_ net-_i4-pad2_ net-_i6-pad1_ Q2N2222 +i6 net-_i6-pad1_ net-_i10-pad2_ 50ua +q18 net-_c2-pad1_ net-_i6-pad1_ net-_i10-pad2_ Q2N2222 +q22 net-_i1-pad1_ net-_c2-pad1_ net-_q22-pad3_ Q2N2222 +q20 net-_c2-pad1_ net-_q20-pad2_ net-_i10-pad1_ Q2N2222 +q25 net-_i1-pad1_ net-_q22-pad3_ net-_q20-pad2_ Q2N2222 +i10 net-_i10-pad1_ net-_i10-pad2_ 50ua +r6 net-_q20-pad2_ net-_i10-pad1_ 500 +q26 net-_i10-pad2_ net-_c2-pad1_ net-_i10-pad1_ Q2N2907A +r4 net-_q2-pad2_ net-_i10-pad1_ 10k +q29 net-_q29-pad1_ net-_q27-pad3_ net-_i11-pad2_ Q2N2907A +q34 net-_c3-pad2_ net-_q34-pad2_ net-_i11-pad2_ Q2N2907A +q37 net-_i10-pad2_ net-_q37-pad2_ net-_q34-pad2_ Q2N2907A +q27 net-_i10-pad2_ net-_q27-pad2_ net-_q27-pad3_ Q2N2907A +q30 net-_q29-pad1_ net-_q29-pad1_ net-_i10-pad2_ Q2N2222 +q33 net-_c3-pad2_ net-_q29-pad1_ net-_i10-pad2_ Q2N2222 +r7 net-_r7-pad1_ net-_q27-pad2_ 2k +i11 net-_i1-pad1_ net-_i11-pad2_ 6ua +i13 net-_i1-pad1_ net-_i13-pad2_ 4ua +i17 net-_i1-pad1_ net-_c3-pad1_ 100ua +c3 net-_c3-pad1_ net-_c3-pad2_ 20pf +q39 net-_i10-pad2_ net-_c3-pad2_ net-_i13-pad2_ Q2N2907A +q41 net-_i1-pad1_ net-_i13-pad2_ net-_i15-pad1_ Q2N2222 +i15 net-_i15-pad1_ net-_i10-pad2_ 50ua +q43 net-_c3-pad1_ net-_i15-pad1_ net-_i10-pad2_ Q2N2222 +q47 net-_i1-pad1_ net-_c3-pad1_ net-_q47-pad3_ Q2N2222 +q45 net-_c3-pad1_ net-_q45-pad2_ net-_i18-pad1_ Q2N2222 +q49 net-_i1-pad1_ net-_q47-pad3_ net-_q45-pad2_ Q2N2222 +i18 net-_i18-pad1_ net-_i10-pad2_ 50ua +r11 net-_q45-pad2_ net-_i18-pad1_ 500 +q50 net-_i10-pad2_ net-_c3-pad1_ net-_i18-pad1_ Q2N2907A +r9 net-_q27-pad2_ net-_i18-pad1_ 10k +q3 net-_q3-pad1_ net-_q1-pad3_ net-_i1-pad2_ Q2N2907A +q9 net-_c1-pad2_ net-_q11-pad3_ net-_i1-pad2_ Q2N2907A +q11 net-_i10-pad2_ net-_q11-pad2_ net-_q11-pad3_ Q2N2907A +q1 net-_i10-pad2_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q5 net-_q3-pad1_ net-_q3-pad1_ net-_i10-pad2_ Q2N2222 +q7 net-_c1-pad2_ net-_q3-pad1_ net-_i10-pad2_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 2k +i1 net-_i1-pad1_ net-_i1-pad2_ 6ua +i3 net-_i1-pad1_ net-_i3-pad2_ 4ua +i7 net-_i1-pad1_ net-_c1-pad1_ 100ua +c1 net-_c1-pad1_ net-_c1-pad2_ 20pf +q13 net-_i10-pad2_ net-_c1-pad2_ net-_i3-pad2_ Q2N2907A +q15 net-_i1-pad1_ net-_i3-pad2_ net-_i5-pad1_ Q2N2222 +i5 net-_i5-pad1_ net-_i10-pad2_ 50ua +q17 net-_c1-pad1_ net-_i5-pad1_ net-_i10-pad2_ Q2N2222 +q21 net-_i1-pad1_ net-_c1-pad1_ net-_q21-pad3_ Q2N2222 +q19 net-_c1-pad1_ net-_q19-pad2_ net-_i9-pad1_ Q2N2222 +q23 net-_i1-pad1_ net-_q21-pad3_ net-_q19-pad2_ Q2N2222 +i9 net-_i9-pad1_ net-_i10-pad2_ 50ua +r5 net-_q19-pad2_ net-_i9-pad1_ 500 +q24 net-_i10-pad2_ net-_c1-pad1_ net-_i9-pad1_ Q2N2907A +r3 net-_q1-pad2_ net-_i9-pad1_ 10k +q31 net-_q31-pad1_ net-_q28-pad3_ net-_i12-pad2_ Q2N2907A +q36 net-_c4-pad2_ net-_q36-pad2_ net-_i12-pad2_ Q2N2907A +q38 net-_i10-pad2_ net-_q38-pad2_ net-_q36-pad2_ Q2N2907A +q28 net-_i10-pad2_ net-_q28-pad2_ net-_q28-pad3_ Q2N2907A +q32 net-_q31-pad1_ net-_q31-pad1_ net-_i10-pad2_ Q2N2222 +q35 net-_c4-pad2_ net-_q31-pad1_ net-_i10-pad2_ Q2N2222 +r8 net-_r8-pad1_ net-_q28-pad2_ 2k +i12 net-_i1-pad1_ net-_i12-pad2_ 6ua +i14 net-_i1-pad1_ net-_i14-pad2_ 4ua +i19 net-_i1-pad1_ net-_c4-pad1_ 100ua +c4 net-_c4-pad1_ net-_c4-pad2_ 20pf +q40 net-_i10-pad2_ net-_c4-pad2_ net-_i14-pad2_ Q2N2907A +q42 net-_i1-pad1_ net-_i14-pad2_ net-_i16-pad1_ Q2N2222 +i16 net-_i16-pad1_ net-_i10-pad2_ 50ua +q44 net-_c4-pad1_ net-_i16-pad1_ net-_i10-pad2_ Q2N2222 +q48 net-_i1-pad1_ net-_c4-pad1_ net-_q48-pad3_ Q2N2222 +q46 net-_c4-pad1_ net-_q46-pad2_ net-_i20-pad1_ Q2N2222 +q51 net-_i1-pad1_ net-_q48-pad3_ net-_q46-pad2_ Q2N2222 +i20 net-_i20-pad1_ net-_i10-pad2_ 50ua +r12 net-_q46-pad2_ net-_i20-pad1_ 500 +q52 net-_i10-pad2_ net-_c4-pad1_ net-_i20-pad1_ Q2N2907A +r10 net-_q28-pad2_ net-_i20-pad1_ 10k +* Control Statements + +.ends LM124_SUBcircuit
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit_Previous_Values.xml b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit_Previous_Values.xml new file mode 100644 index 00000000..cc7e24e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/LM124_SUBcircuit_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><i2 name="Source type">6ua</i2><i4 name="Source type">4ua</i4><i8 name="Source type">100ua</i8><i6 name="Source type">50ua</i6><i10 name="Source type">50ua</i10><i11 name="Source type">6ua</i11><i13 name="Source type">4ua</i13><i17 name="Source type">100ua</i17><i15 name="Source type">50ua</i15><i18 name="Source type">50ua</i18><i1 name="Source type">6ua</i1><i3 name="Source type">4ua</i3><i7 name="Source type">100ua</i7><i5 name="Source type">50ua</i5><i9 name="Source type">50ua</i9><i12 name="Source type">6ua</i12><i14 name="Source type">4ua</i14><i19 name="Source type">100ua</i19><i16 name="Source type">50ua</i16><i20 name="Source type">50ua</i20></source><model /><devicemodel><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q14><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q25><q26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q26><q29><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q29><q34><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q34><q37><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q37><q27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q27><q30><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q30><q33><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q33><q39><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q39><q41><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q41><q43><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q43><q47><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q47><q45><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q45><q49><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q49><q50><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q50><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q11><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q13><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q21><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q23><q24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q24><q31><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q31><q36><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q36><q38><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q38><q28><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q28><q32><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q32><q35><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q35><q40><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q40><q42><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q42><q44><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q44><q48><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q48><q46><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q46><q51><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q51><q52><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q52></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.1</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM124_SUBCIRCUIT/NPN.lib b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM124_SUBCIRCUIT/PNP.lib b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM124_SUBCIRCUIT/analysis b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/analysis new file mode 100644 index 00000000..402d01b4 --- /dev/null +++ b/library/SubcircuitLibrary/LM124_SUBCIRCUIT/analysis @@ -0,0 +1 @@ +.tran 0.1e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM2901_SUB/D.lib b/library/SubcircuitLibrary/LM2901_SUB/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/D.lib b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB-cache.lib b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB-cache.lib new file mode 100644 index 00000000..3dddd3f6 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB-cache.lib @@ -0,0 +1,182 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.cir b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.cir new file mode 100644 index 00000000..613ae896 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.cir @@ -0,0 +1,59 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM109_NEW_SUB\LM109_NEW_SUB.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 10/02/24 19:57:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +J1 Net-_J1-Pad1_ Net-_D1-Pad1_ Net-_J1-Pad3_ jfet_n +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q2 Net-_J1-Pad1_ Net-_Q10-Pad1_ Net-_J1-Pad3_ eSim_NPN +R1 Net-_Q3-Pad3_ Net-_D1-Pad1_ 450 +Q3 Net-_J1-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q6 Net-_J1-Pad3_ Net-_J1-Pad3_ Net-_Q6-Pad3_ eSim_NPN +R4 Net-_J1-Pad3_ Net-_Q6-Pad3_ 3k +R2 Net-_Q6-Pad3_ Net-_Q3-Pad2_ 2.4k +R3 Net-_Q3-Pad2_ Net-_Q5-Pad1_ 25 +Q5 Net-_Q5-Pad1_ Net-_Q3-Pad3_ Net-_D1-Pad1_ eSim_NPN +Q8 Net-_Q11-Pad3_ Net-_Q5-Pad1_ Net-_Q8-Pad3_ eSim_NPN +R5 Net-_Q8-Pad3_ Net-_D1-Pad1_ 12.1k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_Q10-Pad3_ Net-_Q10-Pad3_ Net-_Q11-Pad3_ eSim_NPN +R6 Net-_Q11-Pad3_ Net-_C1-Pad2_ 24k +Q9 Net-_C1-Pad2_ Net-_Q8-Pad3_ Net-_Q9-Pad3_ eSim_NPN +R7 Net-_Q9-Pad3_ Net-_D1-Pad1_ 1k +Q13 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q13-Pad3_ eSim_NPN +Q15 Net-_Q15-Pad1_ Net-_Q15-Pad1_ Net-_D1-Pad1_ eSim_NPN +R10 Net-_Q13-Pad3_ Net-_Q15-Pad1_ 4k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30pF +U1 Net-_D2-Pad1_ Net-_Q12-Pad2_ zener +Q12 Net-_D1-Pad2_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R8 Net-_Q12-Pad3_ Net-_Q14-Pad2_ 3.1k +R9 Net-_Q14-Pad2_ Net-_D1-Pad1_ 200 +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q16 Net-_Q14-Pad1_ Net-_D5-Pad2_ Net-_Q10-Pad1_ eSim_NPN +U2 Net-_D4-Pad1_ Net-_R11-Pad2_ zener +R11 Net-_D1-Pad2_ Net-_R11-Pad2_ 10k +R12 Net-_Q20-Pad3_ Net-_D5-Pad2_ 130 +R13 Net-_Q14-Pad1_ Net-_C1-Pad1_ 4k +Q17 Net-_C1-Pad1_ Net-_Q13-Pad3_ Net-_D1-Pad1_ eSim_NPN +Q18 Net-_D1-Pad1_ Net-_C1-Pad1_ Net-_Q14-Pad1_ eSim_PNP +Q20 Net-_D1-Pad2_ Net-_Q19-Pad3_ Net-_Q20-Pad3_ eSim_NPN +Q19 Net-_D1-Pad2_ Net-_Q14-Pad1_ Net-_Q19-Pad3_ eSim_NPN +R14 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 2k +R15 Net-_Q10-Pad1_ Net-_Q20-Pad3_ 0.3 +R16 Net-_R16-Pad1_ Net-_Q10-Pad1_ 4 +U3 Net-_D6-Pad1_ Net-_R16-Pad1_ zener +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +D3 Net-_D2-Pad2_ Net-_D1-Pad1_ eSim_Diode +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +D5 Net-_D4-Pad2_ Net-_D5-Pad2_ eSim_Diode +D6 Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_Diode +D7 Net-_D6-Pad2_ Net-_D1-Pad1_ eSim_Diode +Q1 Net-_J1-Pad1_ Net-_J1-Pad1_ Net-_D1-Pad2_ eSim_PNP +Q4 Net-_Q14-Pad1_ Net-_J1-Pad1_ Net-_D1-Pad2_ eSim_PNP +Q7 Net-_Q12-Pad2_ Net-_J1-Pad1_ Net-_D1-Pad2_ eSim_PNP +U4 Net-_D1-Pad2_ Net-_Q10-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.cir.out b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.cir.out new file mode 100644 index 00000000..4afa4b32 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.cir.out @@ -0,0 +1,73 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm109_new_sub\lm109_new_sub.cir + +.include NPN.lib +.include PNP.lib +.include D.lib +.include NJF.lib +j1 net-_j1-pad1_ net-_d1-pad1_ net-_j1-pad3_ J2N3819 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q2 net-_j1-pad1_ net-_q10-pad1_ net-_j1-pad3_ Q2N2222 +r1 net-_q3-pad3_ net-_d1-pad1_ 450 +q3 net-_j1-pad3_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q6 net-_j1-pad3_ net-_j1-pad3_ net-_q6-pad3_ Q2N2222 +r4 net-_j1-pad3_ net-_q6-pad3_ 3k +r2 net-_q6-pad3_ net-_q3-pad2_ 2.4k +r3 net-_q3-pad2_ net-_q5-pad1_ 25 +q5 net-_q5-pad1_ net-_q3-pad3_ net-_d1-pad1_ Q2N2222 +q8 net-_q11-pad3_ net-_q5-pad1_ net-_q8-pad3_ Q2N2222 +r5 net-_q8-pad3_ net-_d1-pad1_ 12.1k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ Q2N2222 +q11 net-_q10-pad3_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222 +r6 net-_q11-pad3_ net-_c1-pad2_ 24k +q9 net-_c1-pad2_ net-_q8-pad3_ net-_q9-pad3_ Q2N2222 +r7 net-_q9-pad3_ net-_d1-pad1_ 1k +q13 net-_c1-pad1_ net-_c1-pad2_ net-_q13-pad3_ Q2N2222 +q15 net-_q15-pad1_ net-_q15-pad1_ net-_d1-pad1_ Q2N2222 +r10 net-_q13-pad3_ net-_q15-pad1_ 4k +c1 net-_c1-pad1_ net-_c1-pad2_ 30pf +* u1 net-_d2-pad1_ net-_q12-pad2_ zener +q12 net-_d1-pad2_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r8 net-_q12-pad3_ net-_q14-pad2_ 3.1k +r9 net-_q14-pad2_ net-_d1-pad1_ 200 +q14 net-_q14-pad1_ net-_q14-pad2_ net-_d1-pad1_ Q2N2222 +q16 net-_q14-pad1_ net-_d5-pad2_ net-_q10-pad1_ Q2N2222 +* u2 net-_d4-pad1_ net-_r11-pad2_ zener +r11 net-_d1-pad2_ net-_r11-pad2_ 10k +r12 net-_q20-pad3_ net-_d5-pad2_ 130 +r13 net-_q14-pad1_ net-_c1-pad1_ 4k +q17 net-_c1-pad1_ net-_q13-pad3_ net-_d1-pad1_ Q2N2222 +q18 net-_d1-pad1_ net-_c1-pad1_ net-_q14-pad1_ Q2N2907A +q20 net-_d1-pad2_ net-_q19-pad3_ net-_q20-pad3_ Q2N2222 +q19 net-_d1-pad2_ net-_q14-pad1_ net-_q19-pad3_ Q2N2222 +r14 net-_q20-pad3_ net-_q19-pad3_ 2k +r15 net-_q10-pad1_ net-_q20-pad3_ 0.3 +r16 net-_r16-pad1_ net-_q10-pad1_ 4 +* u3 net-_d6-pad1_ net-_r16-pad1_ zener +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ net-_d1-pad1_ 1N4148 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +d5 net-_d4-pad2_ net-_d5-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d1-pad1_ 1N4148 +q1 net-_j1-pad1_ net-_j1-pad1_ net-_d1-pad2_ Q2N2907A +q4 net-_q14-pad1_ net-_j1-pad1_ net-_d1-pad2_ Q2N2907A +q7 net-_q12-pad2_ net-_j1-pad1_ net-_d1-pad2_ Q2N2907A +* u4 net-_d1-pad2_ net-_q10-pad1_ net-_d1-pad1_ port +a1 net-_d2-pad1_ net-_q12-pad2_ u1 +a2 net-_d4-pad1_ net-_r11-pad2_ u2 +a3 net-_d6-pad1_ net-_r16-pad1_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0.01e-00 0.1e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.pro b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.sch b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.sch new file mode 100644 index 00000000..14ae68db --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.sch @@ -0,0 +1,926 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM109_NEW-cache +EELAYER 25 0 +EELAYER END +$Descr User 17748 11000 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L jfet_n J1 +U 1 1 66FD5568 +P 3100 5200 +F 0 "J1" H 3000 5250 50 0000 R CNN +F 1 "jfet_n" H 3050 5350 50 0000 R CNN +F 2 "" H 3300 5300 29 0000 C CNN +F 3 "" H 3100 5200 60 0000 C CNN + 1 3100 5200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 66FD5569 +P 2700 3450 +F 0 "D1" H 2700 3550 50 0000 C CNN +F 1 "eSim_Diode" H 2700 3350 50 0000 C CNN +F 2 "" H 2700 3450 60 0000 C CNN +F 3 "" H 2700 3450 60 0000 C CNN + 1 2700 3450 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 66FD556A +P 3550 4400 +F 0 "Q2" H 3450 4450 50 0000 R CNN +F 1 "eSim_NPN" H 3500 4550 50 0000 R CNN +F 2 "" H 3750 4500 29 0000 C CNN +F 3 "" H 3550 4400 60 0000 C CNN + 1 3550 4400 + -1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 66FD556B +P 3400 7950 +F 0 "R1" H 3450 8080 50 0000 C CNN +F 1 "450" H 3450 7900 50 0000 C CNN +F 2 "" H 3450 7930 30 0000 C CNN +F 3 "" V 3450 8000 30 0000 C CNN + 1 3400 7950 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 66FD556C +P 3550 7050 +F 0 "Q3" H 3450 7100 50 0000 R CNN +F 1 "eSim_NPN" H 3500 7200 50 0000 R CNN +F 2 "" H 3750 7150 29 0000 C CNN +F 3 "" H 3550 7050 60 0000 C CNN + 1 3550 7050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 66FD556D +P 4150 5100 +F 0 "Q6" H 4050 5150 50 0000 R CNN +F 1 "eSim_NPN" H 4100 5250 50 0000 R CNN +F 2 "" H 4350 5200 29 0000 C CNN +F 3 "" H 4150 5100 60 0000 C CNN + 1 4150 5100 + -1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 66FD556E +P 4400 5450 +F 0 "R4" H 4450 5580 50 0000 C CNN +F 1 "3k" H 4450 5400 50 0000 C CNN +F 2 "" H 4450 5430 30 0000 C CNN +F 3 "" V 4450 5500 30 0000 C CNN + 1 4400 5450 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 66FD556F +P 4000 6050 +F 0 "R2" H 4050 6180 50 0000 C CNN +F 1 "2.4k" H 4050 6000 50 0000 C CNN +F 2 "" H 4050 6030 30 0000 C CNN +F 3 "" V 4050 6100 30 0000 C CNN + 1 4000 6050 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 66FD5570 +P 4000 7350 +F 0 "R3" H 4050 7480 50 0000 C CNN +F 1 "25" H 4050 7300 50 0000 C CNN +F 2 "" H 4050 7330 30 0000 C CNN +F 3 "" V 4050 7400 30 0000 C CNN + 1 4000 7350 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 66FD5571 +P 3950 7850 +F 0 "Q5" H 3850 7900 50 0000 R CNN +F 1 "eSim_NPN" H 3900 8000 50 0000 R CNN +F 2 "" H 4150 7950 29 0000 C CNN +F 3 "" H 3950 7850 60 0000 C CNN + 1 3950 7850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 66FD5572 +P 4450 7600 +F 0 "Q8" H 4350 7650 50 0000 R CNN +F 1 "eSim_NPN" H 4400 7750 50 0000 R CNN +F 2 "" H 4650 7700 29 0000 C CNN +F 3 "" H 4450 7600 60 0000 C CNN + 1 4450 7600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 66FD5573 +P 4500 8050 +F 0 "R5" H 4550 8180 50 0000 C CNN +F 1 "12.1k" H 4550 8000 50 0000 C CNN +F 2 "" H 4550 8030 30 0000 C CNN +F 3 "" V 4550 8100 30 0000 C CNN + 1 4500 8050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 66FD5574 +P 5400 4800 +F 0 "Q10" H 5300 4850 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4950 50 0000 R CNN +F 2 "" H 5600 4900 29 0000 C CNN +F 3 "" H 5400 4800 60 0000 C CNN + 1 5400 4800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 66FD5575 +P 5400 5450 +F 0 "Q11" H 5300 5500 50 0000 R CNN +F 1 "eSim_NPN" H 5350 5600 50 0000 R CNN +F 2 "" H 5600 5550 29 0000 C CNN +F 3 "" H 5400 5450 60 0000 C CNN + 1 5400 5450 + -1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 66FD5576 +P 5250 6200 +F 0 "R6" H 5300 6330 50 0000 C CNN +F 1 "24k" H 5300 6150 50 0000 C CNN +F 2 "" H 5300 6180 30 0000 C CNN +F 3 "" V 5300 6250 30 0000 C CNN + 1 5250 6200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 66FD5577 +P 5200 7550 +F 0 "Q9" H 5100 7600 50 0000 R CNN +F 1 "eSim_NPN" H 5150 7700 50 0000 R CNN +F 2 "" H 5400 7650 29 0000 C CNN +F 3 "" H 5200 7550 60 0000 C CNN + 1 5200 7550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 66FD5578 +P 5250 8000 +F 0 "R7" H 5300 8130 50 0000 C CNN +F 1 "1k" H 5300 7950 50 0000 C CNN +F 2 "" H 5300 7980 30 0000 C CNN +F 3 "" V 5300 8050 30 0000 C CNN + 1 5250 8000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 66FD5579 +P 5850 6850 +F 0 "Q13" H 5750 6900 50 0000 R CNN +F 1 "eSim_NPN" H 5800 7000 50 0000 R CNN +F 2 "" H 6050 6950 29 0000 C CNN +F 3 "" H 5850 6850 60 0000 C CNN + 1 5850 6850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 66FD557A +P 6050 7750 +F 0 "Q15" H 5950 7800 50 0000 R CNN +F 1 "eSim_NPN" H 6000 7900 50 0000 R CNN +F 2 "" H 6250 7850 29 0000 C CNN +F 3 "" H 6050 7750 60 0000 C CNN + 1 6050 7750 + -1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 66FD557B +P 5900 7250 +F 0 "R10" H 5950 7380 50 0000 C CNN +F 1 "4k" H 5950 7200 50 0000 C CNN +F 2 "" H 5950 7230 30 0000 C CNN +F 3 "" V 5950 7300 30 0000 C CNN + 1 5900 7250 + 0 1 1 0 +$EndComp +$Comp +L capacitor C1 +U 1 1 66FD557C +P 5650 6450 +F 0 "C1" H 5675 6550 50 0000 L CNN +F 1 "30pF" H 5675 6350 50 0000 L CNN +F 2 "" H 5688 6300 30 0000 C CNN +F 3 "" H 5650 6450 60 0000 C CNN + 1 5650 6450 + 0 1 1 0 +$EndComp +$Comp +L zener U1 +U 1 1 66FD557D +P 5000 2950 +F 0 "U1" H 4950 2850 60 0000 C CNN +F 1 "zener" H 5000 3050 60 0000 C CNN +F 2 "" H 5050 2950 60 0000 C CNN +F 3 "" H 5050 2950 60 0000 C CNN + 1 5000 2950 + 0 1 -1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 66FD557E +P 5450 3200 +F 0 "Q12" H 5350 3250 50 0000 R CNN +F 1 "eSim_NPN" H 5400 3350 50 0000 R CNN +F 2 "" H 5650 3300 29 0000 C CNN +F 3 "" H 5450 3200 60 0000 C CNN + 1 5450 3200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R8 +U 1 1 66FD557F +P 5500 3600 +F 0 "R8" H 5550 3730 50 0000 C CNN +F 1 "3.1k" H 5550 3550 50 0000 C CNN +F 2 "" H 5550 3580 30 0000 C CNN +F 3 "" V 5550 3650 30 0000 C CNN + 1 5500 3600 + 0 1 1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 66FD5580 +P 5500 4000 +F 0 "R9" H 5550 4130 50 0000 C CNN +F 1 "200" H 5550 3950 50 0000 C CNN +F 2 "" H 5550 3980 30 0000 C CNN +F 3 "" V 5550 4050 30 0000 C CNN + 1 5500 4000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 66FD5581 +P 6000 3850 +F 0 "Q14" H 5900 3900 50 0000 R CNN +F 1 "eSim_NPN" H 5950 4000 50 0000 R CNN +F 2 "" H 6200 3950 29 0000 C CNN +F 3 "" H 6000 3850 60 0000 C CNN + 1 6000 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 66FD5582 +P 6600 4050 +F 0 "Q16" H 6500 4100 50 0000 R CNN +F 1 "eSim_NPN" H 6550 4200 50 0000 R CNN +F 2 "" H 6800 4150 29 0000 C CNN +F 3 "" H 6600 4050 60 0000 C CNN + 1 6600 4050 + -1 0 0 -1 +$EndComp +$Comp +L zener U2 +U 1 1 66FD5583 +P 6950 3100 +F 0 "U2" H 6900 3000 60 0000 C CNN +F 1 "zener" H 6950 3200 60 0000 C CNN +F 2 "" H 7000 3100 60 0000 C CNN +F 3 "" H 7000 3100 60 0000 C CNN + 1 6950 3100 + 0 1 -1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 66FD5584 +P 6900 2550 +F 0 "R11" H 6950 2680 50 0000 C CNN +F 1 "10k" H 6950 2500 50 0000 C CNN +F 2 "" H 6950 2530 30 0000 C CNN +F 3 "" V 6950 2600 30 0000 C CNN + 1 6900 2550 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 66FD5585 +P 7400 3800 +F 0 "R12" H 7450 3930 50 0000 C CNN +F 1 "130" H 7450 3750 50 0000 C CNN +F 2 "" H 7450 3780 30 0000 C CNN +F 3 "" V 7450 3850 30 0000 C CNN + 1 7400 3800 + -1 0 0 1 +$EndComp +$Comp +L resistor R13 +U 1 1 66FD5586 +P 7600 6150 +F 0 "R13" H 7650 6280 50 0000 C CNN +F 1 "4k" H 7650 6100 50 0000 C CNN +F 2 "" H 7650 6130 30 0000 C CNN +F 3 "" V 7650 6200 30 0000 C CNN + 1 7600 6150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 66FD5587 +P 7550 7100 +F 0 "Q17" H 7450 7150 50 0000 R CNN +F 1 "eSim_NPN" H 7500 7250 50 0000 R CNN +F 2 "" H 7750 7200 29 0000 C CNN +F 3 "" H 7550 7100 60 0000 C CNN + 1 7550 7100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q18 +U 1 1 66FD5588 +P 8350 6550 +F 0 "Q18" H 8250 6600 50 0000 R CNN +F 1 "eSim_PNP" H 8300 6700 50 0000 R CNN +F 2 "" H 8550 6650 29 0000 C CNN +F 3 "" H 8350 6550 60 0000 C CNN + 1 8350 6550 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 66FD5589 +P 9250 3200 +F 0 "Q20" H 9150 3250 50 0000 R CNN +F 1 "eSim_NPN" H 9200 3350 50 0000 R CNN +F 2 "" H 9450 3300 29 0000 C CNN +F 3 "" H 9250 3200 60 0000 C CNN + 1 9250 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 66FD558A +P 8650 2850 +F 0 "Q19" H 8550 2900 50 0000 R CNN +F 1 "eSim_NPN" H 8600 3000 50 0000 R CNN +F 2 "" H 8850 2950 29 0000 C CNN +F 3 "" H 8650 2850 60 0000 C CNN + 1 8650 2850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R14 +U 1 1 66FD558B +P 8800 3500 +F 0 "R14" H 8850 3630 50 0000 C CNN +F 1 "2k" H 8850 3450 50 0000 C CNN +F 2 "" H 8850 3480 30 0000 C CNN +F 3 "" V 8850 3550 30 0000 C CNN + 1 8800 3500 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 66FD558C +P 9400 4200 +F 0 "R15" H 9450 4330 50 0000 C CNN +F 1 "0.3" H 9450 4150 50 0000 C CNN +F 2 "" H 9450 4180 30 0000 C CNN +F 3 "" V 9450 4250 30 0000 C CNN + 1 9400 4200 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R16 +U 1 1 66FD558D +P 9400 5150 +F 0 "R16" H 9450 5280 50 0000 C CNN +F 1 "4" H 9450 5100 50 0000 C CNN +F 2 "" H 9450 5130 30 0000 C CNN +F 3 "" V 9450 5200 30 0000 C CNN + 1 9400 5150 + 0 -1 -1 0 +$EndComp +$Comp +L zener U3 +U 1 1 66FD558E +P 9350 6350 +F 0 "U3" H 9300 6250 60 0000 C CNN +F 1 "zener" H 9350 6450 60 0000 C CNN +F 2 "" H 9400 6350 60 0000 C CNN +F 3 "" H 9400 6350 60 0000 C CNN + 1 9350 6350 + 0 1 -1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 66FD5594 +P 5000 3350 +F 0 "D2" H 5000 3450 50 0000 C CNN +F 1 "eSim_Diode" H 5000 3550 50 0000 C CNN +F 2 "" H 5000 3350 60 0000 C CNN +F 3 "" H 5000 3350 60 0000 C CNN + 1 5000 3350 + 0 -1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 66FD5595 +P 5000 3700 +F 0 "D3" H 5000 3800 50 0000 C CNN +F 1 "eSim_Diode" H 5000 3600 50 0000 C CNN +F 2 "" H 5000 3700 60 0000 C CNN +F 3 "" H 5000 3700 60 0000 C CNN + 1 5000 3700 + 0 -1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 66FD5596 +P 6950 3550 +F 0 "D4" H 6950 3650 50 0000 C CNN +F 1 "eSim_Diode" H 6950 3450 50 0000 C CNN +F 2 "" H 6950 3550 60 0000 C CNN +F 3 "" H 6950 3550 60 0000 C CNN + 1 6950 3550 + 0 -1 1 0 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 66FD5597 +P 6950 3950 +F 0 "D5" H 6950 4050 50 0000 C CNN +F 1 "eSim_Diode" H 6950 3850 50 0000 C CNN +F 2 "" H 6950 3950 60 0000 C CNN +F 3 "" H 6950 3950 60 0000 C CNN + 1 6950 3950 + 0 -1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 66FD5598 +P 9350 6950 +F 0 "D6" H 9350 7050 50 0000 C CNN +F 1 "eSim_Diode" H 9350 6850 50 0000 C CNN +F 2 "" H 9350 6950 60 0000 C CNN +F 3 "" H 9350 6950 60 0000 C CNN + 1 9350 6950 + 0 -1 1 0 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 66FD5599 +P 9350 7550 +F 0 "D7" H 9350 7650 50 0000 C CNN +F 1 "eSim_Diode" H 9350 7450 50 0000 C CNN +F 2 "" H 9350 7550 60 0000 C CNN +F 3 "" H 9350 7550 60 0000 C CNN + 1 9350 7550 + 0 -1 1 0 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 66FD559A +P 3150 2850 +F 0 "Q1" H 3050 2900 50 0000 R CNN +F 1 "eSim_PNP" H 3100 3000 50 0000 R CNN +F 2 "" H 3350 2950 29 0000 C CNN +F 3 "" H 3150 2850 60 0000 C CNN + 1 3150 2850 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 66FD559B +P 3750 2850 +F 0 "Q4" H 3650 2900 50 0000 R CNN +F 1 "eSim_PNP" H 3700 3000 50 0000 R CNN +F 2 "" H 3950 2950 29 0000 C CNN +F 3 "" H 3750 2850 60 0000 C CNN + 1 3750 2850 + 0 1 -1 0 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 66FD559C +P 4350 2850 +F 0 "Q7" H 4250 2900 50 0000 R CNN +F 1 "eSim_PNP" H 4300 3000 50 0000 R CNN +F 2 "" H 4550 2950 29 0000 C CNN +F 3 "" H 4350 2850 60 0000 C CNN + 1 4350 2850 + 0 1 -1 0 +$EndComp +Wire Wire Line + 2700 3600 2700 8300 +Wire Wire Line + 2900 5200 2700 5200 +Connection ~ 2700 5200 +Wire Wire Line + 3450 4600 3450 6850 +Wire Wire Line + 3200 5400 3200 6600 +Wire Wire Line + 3200 6600 3450 6600 +Connection ~ 3450 6600 +Wire Wire Line + 3450 7250 3450 7850 +Connection ~ 3450 8300 +Wire Wire Line + 4050 4900 4050 4700 +Wire Wire Line + 3450 4700 4450 4700 +Connection ~ 3450 4700 +Wire Wire Line + 4450 4700 4450 5350 +Connection ~ 4050 4700 +Wire Wire Line + 4050 5300 4050 5950 +Wire Wire Line + 4050 5800 4450 5800 +Wire Wire Line + 4450 5800 4450 5650 +Wire Wire Line + 4350 5100 4450 5100 +Connection ~ 4450 5100 +Connection ~ 4050 5800 +Wire Wire Line + 4050 6250 4050 7250 +Wire Wire Line + 3750 7050 4050 7050 +Connection ~ 4050 7050 +Wire Wire Line + 3450 8150 3450 8300 +Wire Wire Line + 3750 7850 3650 7850 +Wire Wire Line + 3650 7850 3650 7550 +Wire Wire Line + 3650 7550 3450 7550 +Connection ~ 3450 7550 +Wire Wire Line + 4050 7550 4050 7650 +Wire Wire Line + 4050 8050 4050 8300 +Connection ~ 4050 8300 +Wire Wire Line + 4250 7600 4050 7600 +Connection ~ 4050 7600 +Wire Wire Line + 4550 7800 4550 7950 +Wire Wire Line + 4550 8250 4550 8300 +Connection ~ 4550 8300 +Wire Wire Line + 3750 4400 10600 4400 +Wire Wire Line + 4550 7400 4550 5900 +Wire Wire Line + 4550 5900 5300 5900 +Wire Wire Line + 5300 4600 5300 4400 +Connection ~ 5300 4400 +Wire Wire Line + 5300 5000 5300 5250 +Wire Wire Line + 5300 5650 5300 6100 +Wire Wire Line + 5900 4800 5600 4800 +Wire Wire Line + 5900 4350 5900 4800 +Wire Wire Line + 5600 5450 5900 5450 +Wire Wire Line + 5900 5450 5900 5100 +Wire Wire Line + 5900 5100 5300 5100 +Connection ~ 5300 5100 +Connection ~ 5300 5900 +Wire Wire Line + 5300 6400 5300 7350 +Wire Wire Line + 5300 7900 5300 7750 +Wire Wire Line + 5000 7550 4800 7550 +Wire Wire Line + 4800 7550 4800 7850 +Wire Wire Line + 4800 7850 4550 7850 +Connection ~ 4550 7850 +Wire Wire Line + 5300 8200 5300 8300 +Connection ~ 5300 8300 +Wire Wire Line + 5950 8300 5950 7950 +Wire Wire Line + 5950 7050 5950 7150 +Wire Wire Line + 5950 7450 5950 7550 +Wire Wire Line + 5500 6450 5300 6450 +Connection ~ 5300 6450 +Wire Wire Line + 5650 6850 5300 6850 +Connection ~ 5300 6850 +Wire Wire Line + 5950 6650 5950 6550 +Wire Wire Line + 5950 6550 8150 6550 +Wire Wire Line + 5800 6450 6100 6450 +Wire Wire Line + 6100 6450 6100 6550 +Connection ~ 6100 6550 +Wire Wire Line + 5950 7500 6500 7500 +Wire Wire Line + 6500 7500 6500 7750 +Wire Wire Line + 6500 7750 6250 7750 +Connection ~ 5950 7500 +Connection ~ 5950 8300 +Wire Wire Line + 3200 5000 3200 4150 +Wire Wire Line + 3200 4150 3450 4150 +Connection ~ 3450 4150 +Wire Wire Line + 2700 2350 2700 3300 +Connection ~ 2700 4050 +Wire Wire Line + 5000 3850 5000 4300 +Wire Wire Line + 5550 2350 5550 3000 +Wire Wire Line + 5550 3400 5550 3500 +Wire Wire Line + 4700 4300 6100 4300 +Wire Wire Line + 5550 4300 5550 4200 +Wire Wire Line + 5550 3800 5550 3900 +Wire Wire Line + 4700 4300 4700 4050 +Wire Wire Line + 4700 4050 2700 4050 +Connection ~ 5000 4300 +Wire Wire Line + 6100 2450 6100 3650 +Wire Wire Line + 5800 3850 5550 3850 +Connection ~ 5550 3850 +Wire Wire Line + 6100 4300 6100 4050 +Connection ~ 5550 4300 +Wire Wire Line + 6500 3500 6500 3850 +Wire Wire Line + 6500 3500 6100 3500 +Connection ~ 6100 3500 +Connection ~ 5900 4400 +Wire Wire Line + 5900 4350 6500 4350 +Wire Wire Line + 7500 3850 9350 3850 +Wire Wire Line + 7650 6350 7650 6900 +Wire Wire Line + 7650 2450 7650 6050 +Connection ~ 7650 6550 +Wire Wire Line + 7350 7100 5950 7100 +Connection ~ 5950 7100 +Wire Wire Line + 7650 7300 7650 8300 +Connection ~ 7650 8300 +Wire Wire Line + 7650 5950 8450 5950 +Wire Wire Line + 8450 5950 8450 6350 +Connection ~ 7650 5950 +Wire Wire Line + 8450 6750 8450 8300 +Connection ~ 8450 8300 +Wire Wire Line + 2700 2350 10100 2350 +Wire Wire Line + 9350 2350 9350 3000 +Connection ~ 5550 2350 +Connection ~ 6950 2350 +Wire Wire Line + 8750 2650 8750 2350 +Connection ~ 8750 2350 +Wire Wire Line + 8750 3600 8750 3850 +Connection ~ 8750 3850 +Wire Wire Line + 8750 3050 8750 3300 +Wire Wire Line + 9050 3200 8750 3200 +Connection ~ 8750 3200 +Connection ~ 9350 3850 +Wire Wire Line + 9350 3400 9350 4000 +Wire Wire Line + 9350 4300 9350 4950 +Connection ~ 9350 4400 +Wire Wire Line + 9350 5250 9350 6050 +Connection ~ 9350 8300 +Wire Wire Line + 2700 8300 10500 8300 +Connection ~ 9350 2350 +Wire Wire Line + 5150 3200 5250 3200 +Wire Wire Line + 5150 2400 5150 3200 +Wire Wire Line + 5000 2400 5000 2650 +Wire Wire Line + 5000 3150 5000 3200 +Wire Wire Line + 5000 3500 5000 3550 +Wire Wire Line + 6950 2450 6950 2350 +Wire Wire Line + 6950 2750 6950 2800 +Wire Wire Line + 6500 4350 6500 4250 +Wire Wire Line + 6950 3300 6950 3400 +Wire Wire Line + 6950 3700 6950 3800 +Wire Wire Line + 6800 4050 6800 4250 +Wire Wire Line + 6800 4250 7100 4250 +Wire Wire Line + 6950 4250 6950 4100 +Wire Wire Line + 7100 4250 7100 3850 +Wire Wire Line + 7100 3850 7200 3850 +Connection ~ 6950 4250 +Wire Wire Line + 9350 6550 9350 6800 +Wire Wire Line + 9350 7100 9350 7400 +Wire Wire Line + 9350 7700 9350 8300 +Wire Wire Line + 3150 3050 3150 3500 +Wire Wire Line + 3150 3500 4350 3500 +Wire Wire Line + 4350 3500 4350 3050 +Connection ~ 3750 3500 +Wire Wire Line + 4550 2750 4700 2750 +Wire Wire Line + 4700 2750 4700 2400 +Wire Wire Line + 4700 2400 5150 2400 +Connection ~ 5000 2400 +Wire Wire Line + 3450 3700 3450 4200 +Wire Wire Line + 2950 2750 2800 2750 +Wire Wire Line + 2800 2750 2800 3700 +Wire Wire Line + 2800 3700 3750 3700 +Wire Wire Line + 3750 3700 3750 3050 +Connection ~ 3450 3700 +Wire Wire Line + 3550 2750 3500 2750 +Wire Wire Line + 3500 2750 3500 2500 +Wire Wire Line + 3400 2500 4100 2500 +Wire Wire Line + 3350 2750 3400 2750 +Wire Wire Line + 3400 2750 3400 2500 +Connection ~ 3500 2500 +Wire Wire Line + 4150 2750 4100 2750 +Wire Wire Line + 4100 2750 4100 2500 +Wire Wire Line + 3950 2750 3950 2450 +Wire Wire Line + 3950 2450 8450 2450 +Connection ~ 6100 2450 +Wire Wire Line + 8450 2450 8450 2850 +Connection ~ 7650 2450 +Wire Wire Line + 3750 2500 3750 2350 +Connection ~ 3750 2350 +Connection ~ 3750 2500 +$Comp +L PORT U4 +U 1 1 66FD5A9F +P 10350 2350 +F 0 "U4" H 10400 2450 30 0000 C CNN +F 1 "PORT" H 10350 2350 30 0000 C CNN +F 2 "" H 10350 2350 60 0000 C CNN +F 3 "" H 10350 2350 60 0000 C CNN + 1 10350 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 2 1 66FD5B58 +P 10850 4400 +F 0 "U4" H 10900 4500 30 0000 C CNN +F 1 "PORT" H 10850 4400 30 0000 C CNN +F 2 "" H 10850 4400 60 0000 C CNN +F 3 "" H 10850 4400 60 0000 C CNN + 2 10850 4400 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 3 1 66FD5C3D +P 10750 8300 +F 0 "U4" H 10800 8400 30 0000 C CNN +F 1 "PORT" H 10750 8300 30 0000 C CNN +F 2 "" H 10750 8300 60 0000 C CNN +F 3 "" H 10750 8300 60 0000 C CNN + 3 10750 8300 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.sub b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.sub new file mode 100644 index 00000000..8e6f5746 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB.sub @@ -0,0 +1,67 @@ +* Subcircuit LM109_NEW_SUB +.subckt LM109_NEW_SUB net-_d1-pad2_ net-_q10-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\lm109_new_sub\lm109_new_sub.cir +.include NPN.lib +.include PNP.lib +.include D.lib +.include NJF.lib +j1 net-_j1-pad1_ net-_d1-pad1_ net-_j1-pad3_ J2N3819 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q2 net-_j1-pad1_ net-_q10-pad1_ net-_j1-pad3_ Q2N2222 +r1 net-_q3-pad3_ net-_d1-pad1_ 450 +q3 net-_j1-pad3_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q6 net-_j1-pad3_ net-_j1-pad3_ net-_q6-pad3_ Q2N2222 +r4 net-_j1-pad3_ net-_q6-pad3_ 3k +r2 net-_q6-pad3_ net-_q3-pad2_ 2.4k +r3 net-_q3-pad2_ net-_q5-pad1_ 25 +q5 net-_q5-pad1_ net-_q3-pad3_ net-_d1-pad1_ Q2N2222 +q8 net-_q11-pad3_ net-_q5-pad1_ net-_q8-pad3_ Q2N2222 +r5 net-_q8-pad3_ net-_d1-pad1_ 12.1k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ Q2N2222 +q11 net-_q10-pad3_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222 +r6 net-_q11-pad3_ net-_c1-pad2_ 24k +q9 net-_c1-pad2_ net-_q8-pad3_ net-_q9-pad3_ Q2N2222 +r7 net-_q9-pad3_ net-_d1-pad1_ 1k +q13 net-_c1-pad1_ net-_c1-pad2_ net-_q13-pad3_ Q2N2222 +q15 net-_q15-pad1_ net-_q15-pad1_ net-_d1-pad1_ Q2N2222 +r10 net-_q13-pad3_ net-_q15-pad1_ 4k +c1 net-_c1-pad1_ net-_c1-pad2_ 30pf +* u1 net-_d2-pad1_ net-_q12-pad2_ zener +q12 net-_d1-pad2_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r8 net-_q12-pad3_ net-_q14-pad2_ 3.1k +r9 net-_q14-pad2_ net-_d1-pad1_ 200 +q14 net-_q14-pad1_ net-_q14-pad2_ net-_d1-pad1_ Q2N2222 +q16 net-_q14-pad1_ net-_d5-pad2_ net-_q10-pad1_ Q2N2222 +* u2 net-_d4-pad1_ net-_r11-pad2_ zener +r11 net-_d1-pad2_ net-_r11-pad2_ 10k +r12 net-_q20-pad3_ net-_d5-pad2_ 130 +r13 net-_q14-pad1_ net-_c1-pad1_ 4k +q17 net-_c1-pad1_ net-_q13-pad3_ net-_d1-pad1_ Q2N2222 +q18 net-_d1-pad1_ net-_c1-pad1_ net-_q14-pad1_ Q2N2907A +q20 net-_d1-pad2_ net-_q19-pad3_ net-_q20-pad3_ Q2N2222 +q19 net-_d1-pad2_ net-_q14-pad1_ net-_q19-pad3_ Q2N2222 +r14 net-_q20-pad3_ net-_q19-pad3_ 2k +r15 net-_q10-pad1_ net-_q20-pad3_ 0.3 +r16 net-_r16-pad1_ net-_q10-pad1_ 4 +* u3 net-_d6-pad1_ net-_r16-pad1_ zener +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ net-_d1-pad1_ 1N4148 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +d5 net-_d4-pad2_ net-_d5-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d1-pad1_ 1N4148 +q1 net-_j1-pad1_ net-_j1-pad1_ net-_d1-pad2_ Q2N2907A +q4 net-_q14-pad1_ net-_j1-pad1_ net-_d1-pad2_ Q2N2907A +q7 net-_q12-pad2_ net-_j1-pad1_ net-_d1-pad2_ Q2N2907A +a1 net-_d2-pad1_ net-_q12-pad2_ u1 +a2 net-_d4-pad1_ net-_r11-pad2_ u2 +a3 net-_d6-pad1_ net-_r16-pad1_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM109_NEW_SUB
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB_Previous_Values.xml b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB_Previous_Values.xml new file mode 100644 index 00000000..0e8c33a7 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/LM109_NEW_SUB_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)">5.6</field1><field2 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field2><field3 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field3><field4 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field4><field5 name="Enter Switch for Limiting (default=FALSE)">FALSE</field5></u1><u2 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)">5.6</field6><field7 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field7><field8 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field8><field9 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field9><field10 name="Enter Switch for Limiting (default=FALSE)">FALSE</field10></u2><u3 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)">5.6</field11><field12 name="Enter Breakdown Current (default=2.0e-2)">2.0e-2</field12><field13 name="Enter Saturation Current (default=1.0e-12)">1.0e-12</field13><field14 name="Enter Forward Emission Coefficient (default=1.0)">1.0</field14><field15 name="Enter Switch for Limiting (default=FALSE)">FALSE</field15></u3></model><devicemodel><j1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q18><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">0.1</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/NJF.lib b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/NPN.lib b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/PNP.lib b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/analysis b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/analysis new file mode 100644 index 00000000..f709edd1 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM109_NEW_SUB/analysis @@ -0,0 +1 @@ +.tran 0.01e-00 0.1e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub-cache.lib b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub-cache.lib new file mode 100644 index 00000000..d44bda0c --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub-cache.lib @@ -0,0 +1,160 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.cir b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.cir new file mode 100644 index 00000000..40aba0eb --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.cir @@ -0,0 +1,79 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM2901_Sub\LM2901_Sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 09/10/24 18:12:35 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +D3 Net-_D3-Pad1_ Net-_D1-Pad1_ eSim_Diode +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_PNP +Q3 Net-_Q3-Pad1_ Net-_D1-Pad1_ Net-_I3-Pad2_ eSim_PNP +I1 Net-_I1-Pad1_ Net-_D3-Pad1_ 80u +I3 Net-_I1-Pad1_ Net-_I3-Pad2_ 80u +I5 Net-_I1-Pad1_ Net-_D5-Pad1_ 80u +Q8 Net-_Q13-Pad2_ Net-_D5-Pad2_ Net-_I3-Pad2_ eSim_PNP +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +D7 Net-_D7-Pad1_ Net-_D5-Pad2_ eSim_Diode +Q11 GND Net-_D7-Pad1_ Net-_D5-Pad2_ eSim_PNP +Q4 Net-_Q3-Pad1_ Net-_Q3-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q7 Net-_Q13-Pad2_ Net-_Q3-Pad1_ Net-_Q1-Pad1_ eSim_NPN +I7 Net-_I1-Pad1_ Net-_I7-Pad2_ 80u +Q13 Net-_I7-Pad2_ Net-_Q13-Pad2_ Net-_Q1-Pad1_ eSim_NPN +Q15 Net-_Q15-Pad1_ Net-_I7-Pad2_ Net-_Q1-Pad1_ eSim_NPN +R1 Net-_I1-Pad1_ Net-_Q15-Pad1_ 18k +D12 Net-_D12-Pad1_ Net-_D10-Pad1_ eSim_Diode +D10 Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_Diode +Q18 Net-_Q1-Pad1_ Net-_D10-Pad2_ Net-_D10-Pad1_ eSim_PNP +Q20 Net-_Q20-Pad1_ Net-_D10-Pad1_ Net-_I12-Pad2_ eSim_PNP +I10 Net-_I1-Pad1_ Net-_D12-Pad1_ 80u +I12 Net-_I1-Pad1_ Net-_I12-Pad2_ 80u +I14 Net-_I1-Pad1_ Net-_D14-Pad1_ 80u +Q26 Net-_Q24-Pad1_ Net-_D14-Pad2_ Net-_I12-Pad2_ eSim_PNP +D14 Net-_D14-Pad1_ Net-_D14-Pad2_ eSim_Diode +D16 Net-_D16-Pad1_ Net-_D14-Pad2_ eSim_Diode +Q28 GND Net-_D16-Pad1_ Net-_D14-Pad2_ eSim_PNP +Q22 Net-_Q20-Pad1_ Net-_Q20-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q24 Net-_Q24-Pad1_ Net-_Q20-Pad1_ Net-_Q1-Pad1_ eSim_NPN +I16 Net-_I1-Pad1_ Net-_I16-Pad2_ 80u +Q30 Net-_I16-Pad2_ Net-_Q24-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q32 Net-_Q32-Pad1_ Net-_I16-Pad2_ Net-_Q1-Pad1_ eSim_NPN +R4 Net-_I1-Pad1_ Net-_Q32-Pad1_ 18k +D4 Net-_D4-Pad1_ Net-_D2-Pad1_ eSim_Diode +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q2 Net-_Q1-Pad1_ Net-_D2-Pad2_ Net-_D2-Pad1_ eSim_PNP +Q5 Net-_Q5-Pad1_ Net-_D2-Pad1_ Net-_I4-Pad2_ eSim_PNP +I2 Net-_I1-Pad1_ Net-_D4-Pad1_ 80u +I4 Net-_I1-Pad1_ Net-_I4-Pad2_ 80u +I6 Net-_I1-Pad1_ Net-_D6-Pad1_ 80u +Q10 Net-_Q10-Pad1_ Net-_D6-Pad2_ Net-_I4-Pad2_ eSim_PNP +D6 Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_Diode +D8 Net-_D8-Pad1_ Net-_D6-Pad2_ eSim_Diode +Q12 GND Net-_D8-Pad1_ Net-_D6-Pad2_ eSim_PNP +Q6 Net-_Q5-Pad1_ Net-_Q5-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q9 Net-_Q10-Pad1_ Net-_Q5-Pad1_ Net-_Q1-Pad1_ eSim_NPN +I8 Net-_I1-Pad1_ Net-_I8-Pad2_ 80u +Q14 Net-_I8-Pad2_ Net-_Q10-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q16 Net-_Q16-Pad1_ Net-_I8-Pad2_ Net-_Q1-Pad1_ eSim_NPN +R2 Net-_I1-Pad1_ Net-_Q16-Pad1_ 18k +D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode +D9 Net-_D11-Pad2_ Net-_D9-Pad2_ eSim_Diode +Q17 Net-_Q1-Pad1_ Net-_D9-Pad2_ Net-_D11-Pad2_ eSim_PNP +Q19 Net-_Q19-Pad1_ Net-_D11-Pad2_ Net-_I11-Pad2_ eSim_PNP +I9 Net-_I1-Pad1_ Net-_D11-Pad1_ 80u +I11 Net-_I1-Pad1_ Net-_I11-Pad2_ 80u +I13 Net-_I1-Pad1_ Net-_D13-Pad1_ 80u +Q25 Net-_Q23-Pad1_ Net-_D13-Pad2_ Net-_I11-Pad2_ eSim_PNP +D13 Net-_D13-Pad1_ Net-_D13-Pad2_ eSim_Diode +D15 Net-_D15-Pad1_ Net-_D13-Pad2_ eSim_Diode +Q27 GND Net-_D15-Pad1_ Net-_D13-Pad2_ eSim_PNP +Q21 Net-_Q19-Pad1_ Net-_Q19-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q23 Net-_Q23-Pad1_ Net-_Q19-Pad1_ Net-_Q1-Pad1_ eSim_NPN +I15 Net-_I1-Pad1_ Net-_I15-Pad2_ 80u +Q29 Net-_I15-Pad2_ Net-_Q23-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q31 Net-_Q31-Pad1_ Net-_I15-Pad2_ Net-_Q1-Pad1_ eSim_NPN +R3 Net-_I1-Pad1_ Net-_Q31-Pad1_ 18k +U1 Net-_Q15-Pad1_ Net-_Q32-Pad1_ Net-_I1-Pad1_ Net-_D16-Pad1_ Net-_D10-Pad2_ Net-_D7-Pad1_ Net-_D1-Pad2_ Net-_D8-Pad1_ Net-_D2-Pad2_ Net-_D15-Pad1_ Net-_D9-Pad2_ Net-_Q1-Pad1_ Net-_Q31-Pad1_ Net-_Q16-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.cir.out b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.cir.out new file mode 100644 index 00000000..a043de64 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.cir.out @@ -0,0 +1,83 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm2901_sub\lm2901_sub.cir + +.include D.lib +.include PNP.lib +.include NPN.lib +d3 net-_d3-pad1_ net-_d1-pad1_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2907A +q3 net-_q3-pad1_ net-_d1-pad1_ net-_i3-pad2_ Q2N2907A +i1 net-_i1-pad1_ net-_d3-pad1_ 80u +i3 net-_i1-pad1_ net-_i3-pad2_ 80u +i5 net-_i1-pad1_ net-_d5-pad1_ 80u +q8 net-_q13-pad2_ net-_d5-pad2_ net-_i3-pad2_ Q2N2907A +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +d7 net-_d7-pad1_ net-_d5-pad2_ 1N4148 +q11 gnd net-_d7-pad1_ net-_d5-pad2_ Q2N2907A +q4 net-_q3-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2222 +q7 net-_q13-pad2_ net-_q3-pad1_ net-_q1-pad1_ Q2N2222 +i7 net-_i1-pad1_ net-_i7-pad2_ 80u +q13 net-_i7-pad2_ net-_q13-pad2_ net-_q1-pad1_ Q2N2222 +q15 net-_q15-pad1_ net-_i7-pad2_ net-_q1-pad1_ Q2N2222 +r1 net-_i1-pad1_ net-_q15-pad1_ 18k +d12 net-_d12-pad1_ net-_d10-pad1_ 1N4148 +d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148 +q18 net-_q1-pad1_ net-_d10-pad2_ net-_d10-pad1_ Q2N2907A +q20 net-_q20-pad1_ net-_d10-pad1_ net-_i12-pad2_ Q2N2907A +i10 net-_i1-pad1_ net-_d12-pad1_ 80u +i12 net-_i1-pad1_ net-_i12-pad2_ 80u +i14 net-_i1-pad1_ net-_d14-pad1_ 80u +q26 net-_q24-pad1_ net-_d14-pad2_ net-_i12-pad2_ Q2N2907A +d14 net-_d14-pad1_ net-_d14-pad2_ 1N4148 +d16 net-_d16-pad1_ net-_d14-pad2_ 1N4148 +q28 gnd net-_d16-pad1_ net-_d14-pad2_ Q2N2907A +q22 net-_q20-pad1_ net-_q20-pad1_ net-_q1-pad1_ Q2N2222 +q24 net-_q24-pad1_ net-_q20-pad1_ net-_q1-pad1_ Q2N2222 +i16 net-_i1-pad1_ net-_i16-pad2_ 80u +q30 net-_i16-pad2_ net-_q24-pad1_ net-_q1-pad1_ Q2N2222 +q32 net-_q32-pad1_ net-_i16-pad2_ net-_q1-pad1_ Q2N2222 +r4 net-_i1-pad1_ net-_q32-pad1_ 18k +d4 net-_d4-pad1_ net-_d2-pad1_ 1N4148 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +q2 net-_q1-pad1_ net-_d2-pad2_ net-_d2-pad1_ Q2N2907A +q5 net-_q5-pad1_ net-_d2-pad1_ net-_i4-pad2_ Q2N2907A +i2 net-_i1-pad1_ net-_d4-pad1_ 80u +i4 net-_i1-pad1_ net-_i4-pad2_ 80u +i6 net-_i1-pad1_ net-_d6-pad1_ 80u +q10 net-_q10-pad1_ net-_d6-pad2_ net-_i4-pad2_ Q2N2907A +d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148 +d8 net-_d8-pad1_ net-_d6-pad2_ 1N4148 +q12 gnd net-_d8-pad1_ net-_d6-pad2_ Q2N2907A +q6 net-_q5-pad1_ net-_q5-pad1_ net-_q1-pad1_ Q2N2222 +q9 net-_q10-pad1_ net-_q5-pad1_ net-_q1-pad1_ Q2N2222 +i8 net-_i1-pad1_ net-_i8-pad2_ 80u +q14 net-_i8-pad2_ net-_q10-pad1_ net-_q1-pad1_ Q2N2222 +q16 net-_q16-pad1_ net-_i8-pad2_ net-_q1-pad1_ Q2N2222 +r2 net-_i1-pad1_ net-_q16-pad1_ 18k +d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148 +d9 net-_d11-pad2_ net-_d9-pad2_ 1N4148 +q17 net-_q1-pad1_ net-_d9-pad2_ net-_d11-pad2_ Q2N2907A +q19 net-_q19-pad1_ net-_d11-pad2_ net-_i11-pad2_ Q2N2907A +i9 net-_i1-pad1_ net-_d11-pad1_ 80u +i11 net-_i1-pad1_ net-_i11-pad2_ 80u +i13 net-_i1-pad1_ net-_d13-pad1_ 80u +q25 net-_q23-pad1_ net-_d13-pad2_ net-_i11-pad2_ Q2N2907A +d13 net-_d13-pad1_ net-_d13-pad2_ 1N4148 +d15 net-_d15-pad1_ net-_d13-pad2_ 1N4148 +q27 gnd net-_d15-pad1_ net-_d13-pad2_ Q2N2907A +q21 net-_q19-pad1_ net-_q19-pad1_ net-_q1-pad1_ Q2N2222 +q23 net-_q23-pad1_ net-_q19-pad1_ net-_q1-pad1_ Q2N2222 +i15 net-_i1-pad1_ net-_i15-pad2_ 80u +q29 net-_i15-pad2_ net-_q23-pad1_ net-_q1-pad1_ Q2N2222 +q31 net-_q31-pad1_ net-_i15-pad2_ net-_q1-pad1_ Q2N2222 +r3 net-_i1-pad1_ net-_q31-pad1_ 18k +* u1 net-_q15-pad1_ net-_q32-pad1_ net-_i1-pad1_ net-_d16-pad1_ net-_d10-pad2_ net-_d7-pad1_ net-_d1-pad2_ net-_d8-pad1_ net-_d2-pad2_ net-_d15-pad1_ net-_d9-pad2_ net-_q1-pad1_ net-_q31-pad1_ net-_q16-pad1_ port +.tran 0.01e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.pro b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.sch b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.sch new file mode 100644 index 00000000..bb58a70f --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.sch @@ -0,0 +1,1517 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM2901_Sub-cache +EELAYER 25 0 +EELAYER END +$Descr User 19717 19701 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_Diode D3 +U 1 1 66DF394F +P 2600 3550 +F 0 "D3" H 2600 3650 50 0000 C CNN +F 1 "eSim_Diode" H 2600 3450 50 0000 C CNN +F 2 "" H 2600 3550 60 0000 C CNN +F 3 "" H 2600 3550 60 0000 C CNN + 1 2600 3550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 66DF3950 +P 2200 4100 +F 0 "D1" H 2200 4200 50 0000 C CNN +F 1 "eSim_Diode" H 2200 4000 50 0000 C CNN +F 2 "" H 2200 4100 60 0000 C CNN +F 3 "" H 2200 4100 60 0000 C CNN + 1 2200 4100 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 66DF3951 +P 2500 4500 +F 0 "Q1" H 2400 4550 50 0000 R CNN +F 1 "eSim_PNP" H 2450 4650 50 0000 R CNN +F 2 "" H 2700 4600 29 0000 C CNN +F 3 "" H 2500 4500 60 0000 C CNN + 1 2500 4500 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 66DF3952 +P 3200 4100 +F 0 "Q3" H 3100 4150 50 0000 R CNN +F 1 "eSim_PNP" H 3150 4250 50 0000 R CNN +F 2 "" H 3400 4200 29 0000 C CNN +F 3 "" H 3200 4100 60 0000 C CNN + 1 3200 4100 + 1 0 0 1 +$EndComp +$Comp +L dc I1 +U 1 1 66DF3953 +P 2550 2700 +F 0 "I1" H 2350 2800 60 0000 C CNN +F 1 "80u" H 2350 2650 60 0000 C CNN +F 2 "R1" H 2250 2700 60 0000 C CNN +F 3 "" H 2550 2700 60 0000 C CNN + 1 2550 2700 + 1 0 0 -1 +$EndComp +$Comp +L dc I3 +U 1 1 66DF3954 +P 4000 2700 +F 0 "I3" H 3800 2800 60 0000 C CNN +F 1 "80u" H 3800 2650 60 0000 C CNN +F 2 "R1" H 3700 2700 60 0000 C CNN +F 3 "" H 4000 2700 60 0000 C CNN + 1 4000 2700 + 1 0 0 -1 +$EndComp +$Comp +L dc I5 +U 1 1 66DF3955 +P 5400 2700 +F 0 "I5" H 5200 2800 60 0000 C CNN +F 1 "80u" H 5200 2650 60 0000 C CNN +F 2 "R1" H 5100 2700 60 0000 C CNN +F 3 "" H 5400 2700 60 0000 C CNN + 1 5400 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 66DF3956 +P 4850 4100 +F 0 "Q8" H 4750 4150 50 0000 R CNN +F 1 "eSim_PNP" H 4800 4250 50 0000 R CNN +F 2 "" H 5050 4200 29 0000 C CNN +F 3 "" H 4850 4100 60 0000 C CNN + 1 4850 4100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 66DF3957 +P 5400 3550 +F 0 "D5" H 5400 3650 50 0000 C CNN +F 1 "eSim_Diode" H 5400 3450 50 0000 C CNN +F 2 "" H 5400 3550 60 0000 C CNN +F 3 "" H 5400 3550 60 0000 C CNN + 1 5400 3550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 66DF3958 +P 5800 4100 +F 0 "D7" H 5800 4200 50 0000 C CNN +F 1 "eSim_Diode" H 5800 4000 50 0000 C CNN +F 2 "" H 5800 4100 60 0000 C CNN +F 3 "" H 5800 4100 60 0000 C CNN + 1 5800 4100 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 66DF3959 +P 5500 4850 +F 0 "Q11" H 5400 4900 50 0000 R CNN +F 1 "eSim_PNP" H 5450 5000 50 0000 R CNN +F 2 "" H 5700 4950 29 0000 C CNN +F 3 "" H 5500 4850 60 0000 C CNN + 1 5500 4850 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 66DF395A +P 3400 7300 +F 0 "Q4" H 3300 7350 50 0000 R CNN +F 1 "eSim_NPN" H 3350 7450 50 0000 R CNN +F 2 "" H 3600 7400 29 0000 C CNN +F 3 "" H 3400 7300 60 0000 C CNN + 1 3400 7300 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 66DF395B +P 4700 7300 +F 0 "Q7" H 4600 7350 50 0000 R CNN +F 1 "eSim_NPN" H 4650 7450 50 0000 R CNN +F 2 "" H 4900 7400 29 0000 C CNN +F 3 "" H 4700 7300 60 0000 C CNN + 1 4700 7300 + 1 0 0 -1 +$EndComp +$Comp +L dc I7 +U 1 1 66DF395C +P 7350 2800 +F 0 "I7" H 7150 2900 60 0000 C CNN +F 1 "80u" H 7150 2750 60 0000 C CNN +F 2 "R1" H 7050 2800 60 0000 C CNN +F 3 "" H 7350 2800 60 0000 C CNN + 1 7350 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 66DF395D +P 7250 6350 +F 0 "Q13" H 7150 6400 50 0000 R CNN +F 1 "eSim_NPN" H 7200 6500 50 0000 R CNN +F 2 "" H 7450 6450 29 0000 C CNN +F 3 "" H 7250 6350 60 0000 C CNN + 1 7250 6350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 66DF395E +P 8000 5600 +F 0 "Q15" H 7900 5650 50 0000 R CNN +F 1 "eSim_NPN" H 7950 5750 50 0000 R CNN +F 2 "" H 8200 5700 29 0000 C CNN +F 3 "" H 8000 5600 60 0000 C CNN + 1 8000 5600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR01 +U 1 1 66DF3967 +P 5400 5250 +F 0 "#PWR01" H 5400 5000 50 0001 C CNN +F 1 "eSim_GND" H 5400 5100 50 0000 C CNN +F 2 "" H 5400 5250 50 0001 C CNN +F 3 "" H 5400 5250 50 0001 C CNN + 1 5400 5250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 3900 3300 3700 +Wire Wire Line + 3300 3700 4750 3700 +Wire Wire Line + 4750 3700 4750 3900 +Wire Wire Line + 4000 3150 4000 3700 +Connection ~ 4000 3700 +Wire Wire Line + 2350 4100 3000 4100 +Wire Wire Line + 2600 3700 2600 4300 +Connection ~ 2600 4100 +Wire Wire Line + 2550 3150 2550 3400 +Wire Wire Line + 2550 3400 2600 3400 +Wire Wire Line + 5400 3150 5400 3400 +Wire Wire Line + 5950 4100 6150 4100 +Wire Wire Line + 6150 4100 6150 5550 +Wire Wire Line + 6150 4850 5700 4850 +Wire Wire Line + 3600 7300 4500 7300 +Wire Wire Line + 3300 4300 3300 7100 +Wire Wire Line + 4750 4300 4750 7100 +Wire Wire Line + 4750 7100 4800 7100 +Wire Wire Line + 3300 6650 3900 6650 +Wire Wire Line + 3900 6650 3900 7300 +Connection ~ 3900 7300 +Connection ~ 3300 6650 +Connection ~ 6150 4850 +Wire Wire Line + 1750 4500 2300 4500 +Wire Wire Line + 2600 4700 2600 7800 +Wire Wire Line + 1950 7800 8100 7800 +Wire Wire Line + 3300 7500 3300 7800 +Connection ~ 3300 7800 +Wire Wire Line + 4800 7500 4800 7800 +Connection ~ 4800 7800 +Connection ~ 2600 7800 +Wire Wire Line + 7350 3250 7350 6150 +Wire Wire Line + 7350 7800 7350 6550 +Wire Wire Line + 2550 2250 2550 2050 +Wire Wire Line + 7350 2050 7350 2350 +Wire Wire Line + 5400 2250 5400 2050 +Connection ~ 5400 2050 +Wire Wire Line + 4000 2250 4000 2050 +Connection ~ 4000 2050 +Wire Wire Line + 7800 5600 7350 5600 +Connection ~ 7350 5600 +Wire Wire Line + 8100 7800 8100 5800 +Connection ~ 7350 7800 +Wire Wire Line + 8100 5400 8100 4700 +Wire Wire Line + 8100 4700 9050 4700 +Wire Wire Line + 2050 4100 2000 4100 +Wire Wire Line + 2000 4100 2000 4500 +Connection ~ 2000 4500 +Wire Wire Line + 2550 2050 8450 2050 +Connection ~ 7350 2050 +Wire Wire Line + 8450 2050 8450 2300 +Wire Wire Line + 5400 3700 5400 4650 +Wire Wire Line + 5050 4100 5400 4100 +Connection ~ 5400 4100 +Wire Wire Line + 5650 4100 5550 4100 +Wire Wire Line + 5550 4100 5550 3950 +Wire Wire Line + 5550 3950 5400 3950 +Connection ~ 5400 3950 +Wire Wire Line + 7050 6350 4750 6350 +Connection ~ 4750 6350 +Wire Wire Line + 5400 5050 5400 5250 +Wire Wire Line + 6150 5550 1950 5550 +Connection ~ 7900 2050 +Connection ~ 8300 4700 +Wire Wire Line + 8300 3400 8300 4700 +Wire Wire Line + 8300 2900 8300 3100 +Wire Wire Line + 7900 2900 7900 2050 +Wire Wire Line + 8300 2900 7900 2900 +$Comp +L resistor R1 +U 1 1 66DF3969 +P 8250 3200 +F 0 "R1" H 8300 3330 50 0000 C CNN +F 1 "18k" H 8300 3150 50 0000 C CNN +F 2 "" H 8300 3180 30 0000 C CNN +F 3 "" V 8300 3250 30 0000 C CNN + 1 8250 3200 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D12 +U 1 1 66DF422D +P 11850 3350 +F 0 "D12" H 11850 3450 50 0000 C CNN +F 1 "eSim_Diode" H 11850 3250 50 0000 C CNN +F 2 "" H 11850 3350 60 0000 C CNN +F 3 "" H 11850 3350 60 0000 C CNN + 1 11850 3350 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D10 +U 1 1 66DF4233 +P 11450 3900 +F 0 "D10" H 11450 4000 50 0000 C CNN +F 1 "eSim_Diode" H 11450 3800 50 0000 C CNN +F 2 "" H 11450 3900 60 0000 C CNN +F 3 "" H 11450 3900 60 0000 C CNN + 1 11450 3900 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q18 +U 1 1 66DF4239 +P 11750 4300 +F 0 "Q18" H 11650 4350 50 0000 R CNN +F 1 "eSim_PNP" H 11700 4450 50 0000 R CNN +F 2 "" H 11950 4400 29 0000 C CNN +F 3 "" H 11750 4300 60 0000 C CNN + 1 11750 4300 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q20 +U 1 1 66DF423F +P 12450 3900 +F 0 "Q20" H 12350 3950 50 0000 R CNN +F 1 "eSim_PNP" H 12400 4050 50 0000 R CNN +F 2 "" H 12650 4000 29 0000 C CNN +F 3 "" H 12450 3900 60 0000 C CNN + 1 12450 3900 + 1 0 0 1 +$EndComp +$Comp +L dc I10 +U 1 1 66DF4245 +P 11800 2500 +F 0 "I10" H 11600 2600 60 0000 C CNN +F 1 "80u" H 11600 2450 60 0000 C CNN +F 2 "R1" H 11500 2500 60 0000 C CNN +F 3 "" H 11800 2500 60 0000 C CNN + 1 11800 2500 + 1 0 0 -1 +$EndComp +$Comp +L dc I12 +U 1 1 66DF424B +P 13250 2500 +F 0 "I12" H 13050 2600 60 0000 C CNN +F 1 "80u" H 13050 2450 60 0000 C CNN +F 2 "R1" H 12950 2500 60 0000 C CNN +F 3 "" H 13250 2500 60 0000 C CNN + 1 13250 2500 + 1 0 0 -1 +$EndComp +$Comp +L dc I14 +U 1 1 66DF4251 +P 14650 2500 +F 0 "I14" H 14450 2600 60 0000 C CNN +F 1 "80u" H 14450 2450 60 0000 C CNN +F 2 "R1" H 14350 2500 60 0000 C CNN +F 3 "" H 14650 2500 60 0000 C CNN + 1 14650 2500 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15600 13900 15900 +Connection ~ 13900 15900 +Connection ~ 11700 15900 +Wire Wire Line + 16450 11350 16450 14250 +Wire Wire Line + 16450 15900 16450 14650 +Wire Wire Line + 11650 10350 11650 10150 +Wire Wire Line + 16450 10150 16450 10450 +Wire Wire Line + 14500 10350 14500 10150 +Connection ~ 14500 10150 +Wire Wire Line + 13100 10350 13100 10150 +Connection ~ 13100 10150 +Wire Wire Line + 16900 13700 16450 13700 +Connection ~ 16450 13700 +Wire Wire Line + 17200 15900 17200 13900 +Connection ~ 16450 15900 +Wire Wire Line + 17200 13500 17200 12800 +Wire Wire Line + 17200 12800 18150 12800 +Wire Wire Line + 11150 12200 11100 12200 +Wire Wire Line + 11100 12200 11100 12600 +Connection ~ 11100 12600 +Wire Wire Line + 11650 10150 17550 10150 +Connection ~ 16450 10150 +Wire Wire Line + 17550 10150 17550 10250 +Wire Wire Line + 14500 11800 14500 12750 +Wire Wire Line + 14150 12200 14500 12200 +Connection ~ 14500 12200 +Wire Wire Line + 14750 12200 14650 12200 +Wire Wire Line + 14650 12200 14650 12050 +Wire Wire Line + 14650 12050 14500 12050 +Connection ~ 14500 12050 +Wire Wire Line + 16150 14450 13850 14450 +Connection ~ 13850 14450 +Wire Wire Line + 14500 13150 14500 13350 +Wire Wire Line + 15250 13650 11050 13650 +Connection ~ 17000 10150 +Connection ~ 17400 12800 +Wire Wire Line + 17400 11500 17400 12800 +Wire Wire Line + 17400 11000 17400 11200 +Wire Wire Line + 17000 11000 17000 10150 +Wire Wire Line + 17400 11000 17000 11000 +$Comp +L resistor R3 +U 1 1 66DF4C95 +P 17350 11300 +F 0 "R3" H 17400 11430 50 0000 C CNN +F 1 "18k" H 17400 11250 50 0000 C CNN +F 2 "" H 17400 11280 30 0000 C CNN +F 3 "" V 17400 11350 30 0000 C CNN + 1 17350 11300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 66DF4D3B +P 18550 4500 +F 0 "U1" H 18600 4600 30 0000 C CNN +F 1 "PORT" H 18550 4500 30 0000 C CNN +F 2 "" H 18550 4500 60 0000 C CNN +F 3 "" H 18550 4500 60 0000 C CNN + 2 18550 4500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 66DF5588 +P 9500 13150 +F 0 "U1" H 9550 13250 30 0000 C CNN +F 1 "PORT" H 9500 13150 30 0000 C CNN +F 2 "" H 9500 13150 60 0000 C CNN +F 3 "" H 9500 13150 60 0000 C CNN + 14 9500 13150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 66DF562F +P 1500 4500 +F 0 "U1" H 1550 4600 30 0000 C CNN +F 1 "PORT" H 1500 4500 30 0000 C CNN +F 2 "" H 1500 4500 60 0000 C CNN +F 3 "" H 1500 4500 60 0000 C CNN + 7 1500 4500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 66DF56EC +P 10800 13650 +F 0 "U1" H 10850 13750 30 0000 C CNN +F 1 "PORT" H 10800 13650 30 0000 C CNN +F 2 "" H 10800 13650 60 0000 C CNN +F 3 "" H 10800 13650 60 0000 C CNN + 10 10800 13650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 66DF5878 +P 9300 4700 +F 0 "U1" H 9350 4800 30 0000 C CNN +F 1 "PORT" H 9300 4700 30 0000 C CNN +F 2 "" H 9300 4700 60 0000 C CNN +F 3 "" H 9300 4700 60 0000 C CNN + 1 9300 4700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 66DF596F +P 10950 5350 +F 0 "U1" H 11000 5450 30 0000 C CNN +F 1 "PORT" H 10950 5350 30 0000 C CNN +F 2 "" H 10950 5350 60 0000 C CNN +F 3 "" H 10950 5350 60 0000 C CNN + 4 10950 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 66DF5A30 +P 1700 12950 +F 0 "U1" H 1750 13050 30 0000 C CNN +F 1 "PORT" H 1700 12950 30 0000 C CNN +F 2 "" H 1700 12950 60 0000 C CNN +F 3 "" H 1700 12950 60 0000 C CNN + 9 1700 12950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 66DF5B01 +P 1700 5550 +F 0 "U1" H 1750 5650 30 0000 C CNN +F 1 "PORT" H 1700 5550 30 0000 C CNN +F 2 "" H 1700 5550 60 0000 C CNN +F 3 "" H 1700 5550 60 0000 C CNN + 6 1700 5550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 66DF5BEA +P 10750 4300 +F 0 "U1" H 10800 4400 30 0000 C CNN +F 1 "PORT" H 10750 4300 30 0000 C CNN +F 2 "" H 10750 4300 60 0000 C CNN +F 3 "" H 10750 4300 60 0000 C CNN + 5 10750 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 66DF5CD9 +P 10600 12600 +F 0 "U1" H 10650 12700 30 0000 C CNN +F 1 "PORT" H 10600 12600 30 0000 C CNN +F 2 "" H 10600 12600 60 0000 C CNN +F 3 "" H 10600 12600 60 0000 C CNN + 11 10600 12600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 66DF5DB8 +P 18400 12800 +F 0 "U1" H 18450 12900 30 0000 C CNN +F 1 "PORT" H 18400 12800 30 0000 C CNN +F 2 "" H 18400 12800 60 0000 C CNN +F 3 "" H 18400 12800 60 0000 C CNN + 13 18400 12800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 66DF5E81 +P 1900 14000 +F 0 "U1" H 1950 14100 30 0000 C CNN +F 1 "PORT" H 1900 14000 30 0000 C CNN +F 2 "" H 1900 14000 60 0000 C CNN +F 3 "" H 1900 14000 60 0000 C CNN + 8 1900 14000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 66DF5F66 +P 1700 7800 +F 0 "U1" H 1750 7900 30 0000 C CNN +F 1 "PORT" H 1700 7800 30 0000 C CNN +F 2 "" H 1700 7800 60 0000 C CNN +F 3 "" H 1700 7800 60 0000 C CNN + 12 1700 7800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 66DF605B +P 8450 2550 +F 0 "U1" H 8500 2650 30 0000 C CNN +F 1 "PORT" H 8450 2550 30 0000 C CNN +F 2 "" H 8450 2550 60 0000 C CNN +F 3 "" H 8450 2550 60 0000 C CNN + 3 8450 2550 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 10350 7600 10350 8100 +Wire Wire Line + 10350 8100 2400 8100 +Wire Wire Line + 2400 8100 2400 7800 +Connection ~ 2400 7800 +Wire Wire Line + 1450 16250 1450 9150 +Wire Wire Line + 1450 9150 2350 9150 +Wire Wire Line + 2350 9150 2350 7800 +Connection ~ 2350 7800 +Wire Wire Line + 10100 15900 10100 8250 +Wire Wire Line + 10100 8250 2250 8250 +Wire Wire Line + 2250 8250 2250 7800 +Connection ~ 2250 7800 +Wire Wire Line + 17700 1850 17700 1550 +Wire Wire Line + 17700 1550 9200 1550 +Wire Wire Line + 9200 1550 9200 2250 +Wire Wire Line + 9200 2250 8450 2250 +Connection ~ 8450 2250 +Wire Wire Line + 9300 10500 9300 5450 +Wire Wire Line + 9300 5450 10000 5450 +Wire Wire Line + 10000 5450 10000 2200 +Wire Wire Line + 10000 2200 8450 2200 +Connection ~ 8450 2200 +Wire Wire Line + 17550 10250 17900 10250 +Wire Wire Line + 17900 10250 17900 9250 +Wire Wire Line + 17900 9250 9700 9250 +Wire Wire Line + 9700 9250 9700 2150 +Wire Wire Line + 9700 2150 8450 2150 +Connection ~ 8450 2150 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.sub b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.sub new file mode 100644 index 00000000..da8ee237 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub.sub @@ -0,0 +1,77 @@ +* Subcircuit LM2901_Sub +.subckt LM2901_Sub net-_q15-pad1_ net-_q32-pad1_ net-_i1-pad1_ net-_d16-pad1_ net-_d10-pad2_ net-_d7-pad1_ net-_d1-pad2_ net-_d8-pad1_ net-_d2-pad2_ net-_d15-pad1_ net-_d9-pad2_ net-_q1-pad1_ net-_q31-pad1_ net-_q16-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\lm2901_sub\lm2901_sub.cir +.include D.lib +.include PNP.lib +.include NPN.lib +d3 net-_d3-pad1_ net-_d1-pad1_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2907A +q3 net-_q3-pad1_ net-_d1-pad1_ net-_i3-pad2_ Q2N2907A +i1 net-_i1-pad1_ net-_d3-pad1_ 80u +i3 net-_i1-pad1_ net-_i3-pad2_ 80u +i5 net-_i1-pad1_ net-_d5-pad1_ 80u +q8 net-_q13-pad2_ net-_d5-pad2_ net-_i3-pad2_ Q2N2907A +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +d7 net-_d7-pad1_ net-_d5-pad2_ 1N4148 +q11 gnd net-_d7-pad1_ net-_d5-pad2_ Q2N2907A +q4 net-_q3-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2222 +q7 net-_q13-pad2_ net-_q3-pad1_ net-_q1-pad1_ Q2N2222 +i7 net-_i1-pad1_ net-_i7-pad2_ 80u +q13 net-_i7-pad2_ net-_q13-pad2_ net-_q1-pad1_ Q2N2222 +q15 net-_q15-pad1_ net-_i7-pad2_ net-_q1-pad1_ Q2N2222 +r1 net-_i1-pad1_ net-_q15-pad1_ 18k +d12 net-_d12-pad1_ net-_d10-pad1_ 1N4148 +d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148 +q18 net-_q1-pad1_ net-_d10-pad2_ net-_d10-pad1_ Q2N2907A +q20 net-_q20-pad1_ net-_d10-pad1_ net-_i12-pad2_ Q2N2907A +i10 net-_i1-pad1_ net-_d12-pad1_ 80u +i12 net-_i1-pad1_ net-_i12-pad2_ 80u +i14 net-_i1-pad1_ net-_d14-pad1_ 80u +q26 net-_q24-pad1_ net-_d14-pad2_ net-_i12-pad2_ Q2N2907A +d14 net-_d14-pad1_ net-_d14-pad2_ 1N4148 +d16 net-_d16-pad1_ net-_d14-pad2_ 1N4148 +q28 gnd net-_d16-pad1_ net-_d14-pad2_ Q2N2907A +q22 net-_q20-pad1_ net-_q20-pad1_ net-_q1-pad1_ Q2N2222 +q24 net-_q24-pad1_ net-_q20-pad1_ net-_q1-pad1_ Q2N2222 +i16 net-_i1-pad1_ net-_i16-pad2_ 80u +q30 net-_i16-pad2_ net-_q24-pad1_ net-_q1-pad1_ Q2N2222 +q32 net-_q32-pad1_ net-_i16-pad2_ net-_q1-pad1_ Q2N2222 +r4 net-_i1-pad1_ net-_q32-pad1_ 18k +d4 net-_d4-pad1_ net-_d2-pad1_ 1N4148 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +q2 net-_q1-pad1_ net-_d2-pad2_ net-_d2-pad1_ Q2N2907A +q5 net-_q5-pad1_ net-_d2-pad1_ net-_i4-pad2_ Q2N2907A +i2 net-_i1-pad1_ net-_d4-pad1_ 80u +i4 net-_i1-pad1_ net-_i4-pad2_ 80u +i6 net-_i1-pad1_ net-_d6-pad1_ 80u +q10 net-_q10-pad1_ net-_d6-pad2_ net-_i4-pad2_ Q2N2907A +d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148 +d8 net-_d8-pad1_ net-_d6-pad2_ 1N4148 +q12 gnd net-_d8-pad1_ net-_d6-pad2_ Q2N2907A +q6 net-_q5-pad1_ net-_q5-pad1_ net-_q1-pad1_ Q2N2222 +q9 net-_q10-pad1_ net-_q5-pad1_ net-_q1-pad1_ Q2N2222 +i8 net-_i1-pad1_ net-_i8-pad2_ 80u +q14 net-_i8-pad2_ net-_q10-pad1_ net-_q1-pad1_ Q2N2222 +q16 net-_q16-pad1_ net-_i8-pad2_ net-_q1-pad1_ Q2N2222 +r2 net-_i1-pad1_ net-_q16-pad1_ 18k +d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148 +d9 net-_d11-pad2_ net-_d9-pad2_ 1N4148 +q17 net-_q1-pad1_ net-_d9-pad2_ net-_d11-pad2_ Q2N2907A +q19 net-_q19-pad1_ net-_d11-pad2_ net-_i11-pad2_ Q2N2907A +i9 net-_i1-pad1_ net-_d11-pad1_ 80u +i11 net-_i1-pad1_ net-_i11-pad2_ 80u +i13 net-_i1-pad1_ net-_d13-pad1_ 80u +q25 net-_q23-pad1_ net-_d13-pad2_ net-_i11-pad2_ Q2N2907A +d13 net-_d13-pad1_ net-_d13-pad2_ 1N4148 +d15 net-_d15-pad1_ net-_d13-pad2_ 1N4148 +q27 gnd net-_d15-pad1_ net-_d13-pad2_ Q2N2907A +q21 net-_q19-pad1_ net-_q19-pad1_ net-_q1-pad1_ Q2N2222 +q23 net-_q23-pad1_ net-_q19-pad1_ net-_q1-pad1_ Q2N2222 +i15 net-_i1-pad1_ net-_i15-pad2_ 80u +q29 net-_i15-pad2_ net-_q23-pad1_ net-_q1-pad1_ Q2N2222 +q31 net-_q31-pad1_ net-_i15-pad2_ net-_q1-pad1_ Q2N2222 +r3 net-_i1-pad1_ net-_q31-pad1_ 18k +* Control Statements + +.ends LM2901_Sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub_Previous_Values.xml b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub_Previous_Values.xml new file mode 100644 index 00000000..1247fea0 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/LM2901_Sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><i1 name="Source type">80u</i1><i3 name="Source type">80u</i3><i5 name="Source type">80u</i5><i7 name="Source type">80u</i7><i9 name="Source type">80u</i9><i11 name="Source type">80u</i11><i13 name="Source type">80u</i13><i15 name="Source type">80u</i15><i2 name="Source type">80u</i2><i4 name="Source type">80u</i4><i6 name="Source type">80u</i6><i8 name="Source type">80u</i8><i10 name="Source type">80u</i10><i12 name="Source type">80u</i12><i14 name="Source type">80u</i14><i16 name="Source type">80u</i16><i17 name="Source type">80u</i17><i19 name="Source type">80u</i19><i21 name="Source type">80u</i21><i23 name="Source type">80u</i23><i25 name="Source type">80u</i25><i27 name="Source type">80u</i27><i29 name="Source type">80u</i29><i31 name="Source type">80u</i31><i18 name="Source type">80u</i18><i20 name="Source type">80u</i20><i22 name="Source type">80u</i22><i24 name="Source type">80u</i24><i26 name="Source type">80u</i26><i28 name="Source type">80u</i28><i30 name="Source type">80u</i30><i32 name="Source type">80u</i32></source><model /><devicemodel><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q11><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><d12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d12><d10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d10><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q18><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q20><q26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q26><d14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d14><d16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d16><q28><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q28><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q24><q30><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q30><q32><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q32><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><d11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d11><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q19><q25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q25><d13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d13><d15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d15><q27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q27><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q21><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q23><q29><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q29><q31><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q31></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM2901_SUB/NPN.lib b/library/SubcircuitLibrary/LM2901_SUB/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM2901_SUB/PNP.lib b/library/SubcircuitLibrary/LM2901_SUB/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM2901_SUB/analysis b/library/SubcircuitLibrary/LM2901_SUB/analysis new file mode 100644 index 00000000..db9906e6 --- /dev/null +++ b/library/SubcircuitLibrary/LM2901_SUB/analysis @@ -0,0 +1 @@ +.tran 0.01e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM317_sub/LM317_sub-cache.lib b/library/SubcircuitLibrary/LM317_sub/LM317_sub-cache.lib new file mode 100644 index 00000000..c28cbe9d --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/LM317_sub-cache.lib @@ -0,0 +1,158 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM317_sub/LM317_sub.cir b/library/SubcircuitLibrary/LM317_sub/LM317_sub.cir new file mode 100644 index 00000000..28c7599b --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/LM317_sub.cir @@ -0,0 +1,73 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM317_sub\LM317_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/27/24 14:52:45 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +J1 Net-_J1-Pad1_ Net-_C1-Pad2_ Net-_J1-Pad3_ eSim_NJF +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q3 Net-_Q2-Pad2_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_PNP +Q4 Net-_Q4-Pad1_ Net-_Q2-Pad2_ Net-_C1-Pad2_ eSim_NPN +Q7 Net-_Q7-Pad1_ Net-_Q4-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q5 Net-_C1-Pad2_ Net-_Q4-Pad1_ Net-_Q5-Pad3_ eSim_PNP +Q6 Net-_Q6-Pad1_ Net-_Q1-Pad1_ Net-_Q6-Pad3_ eSim_PNP +Q8 Net-_Q10-Pad2_ Net-_Q7-Pad1_ Net-_Q5-Pad3_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_C1-Pad2_ Net-_Q11-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q1-Pad1_ Net-_Q9-Pad3_ eSim_PNP +Q13 Net-_Q12-Pad2_ Net-_Q1-Pad1_ Net-_Q13-Pad3_ eSim_PNP +Q12 Net-_J1-Pad1_ Net-_Q12-Pad2_ Net-_Q11-Pad2_ eSim_NPN +Q14 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_Q12-Pad2_ eSim_PNP +Q16 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q16-Pad3_ eSim_NPN +Q18 Net-_Q15-Pad2_ Net-_C1-Pad2_ Net-_Q18-Pad3_ eSim_NPN +Q15 Net-_C1-Pad1_ Net-_Q15-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q17 Net-_Q15-Pad2_ Net-_Q15-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q19 Net-_C1-Pad2_ Net-_C3-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q20 Net-_C3-Pad1_ Net-_C3-Pad2_ Net-_C1-Pad2_ eSim_NPN +Q23 Net-_Q21-Pad2_ Net-_Q10-Pad1_ Net-_Q23-Pad3_ eSim_NPN +Q26 Net-_J1-Pad1_ Net-_Q26-Pad2_ Net-_Q26-Pad3_ eSim_NPN +Q27 Net-_J1-Pad1_ Net-_Q26-Pad3_ Net-_Q27-Pad3_ eSim_NPN +Q22 Net-_Q22-Pad1_ Net-_Q22-Pad2_ Net-_Q22-Pad3_ eSim_NPN +Q25 Net-_Q22-Pad1_ Net-_Q22-Pad2_ Net-_Q25-Pad3_ eSim_NPN +Q21 Net-_Q10-Pad1_ Net-_Q21-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q24 Net-_Q21-Pad2_ Net-_Q21-Pad2_ Net-_J1-Pad1_ eSim_PNP +U5 Net-_J1-Pad1_ Net-_C1-Pad2_ Net-_R16-Pad2_ PORT +U3 Net-_R26-Pad1_ Net-_J1-Pad1_ zener +U4 Net-_Q25-Pad3_ Net-_R26-Pad2_ zener +U2 Net-_C2-Pad2_ Net-_C1-Pad2_ zener +U1 Net-_C1-Pad2_ Net-_J1-Pad3_ zener +R13 Net-_J1-Pad1_ Net-_Q13-Pad3_ 5.6k +R10 Net-_J1-Pad1_ Net-_Q9-Pad3_ 82 +R6 Net-_J1-Pad1_ Net-_Q6-Pad3_ 190 +R4 Net-_J1-Pad1_ Net-_Q3-Pad3_ 310 +R2 Net-_J1-Pad1_ Net-_Q1-Pad3_ 310 +R1 Net-_J1-Pad3_ Net-_Q2-Pad2_ 200k +R5 Net-_Q2-Pad2_ Net-_Q4-Pad1_ 130 +R3 Net-_Q2-Pad3_ Net-_C1-Pad2_ 180 +R7 Net-_Q6-Pad1_ Net-_Q7-Pad1_ 12.4k +R21 Net-_Q10-Pad1_ Net-_Q26-Pad2_ 370 +R22 Net-_Q23-Pad3_ Net-_Q26-Pad3_ 130 +R19 Net-_Q10-Pad1_ Net-_Q22-Pad2_ 12k +R18 Net-_C3-Pad2_ Net-_Q22-Pad1_ 13k +R20 Net-_Q22-Pad2_ Net-_Q22-Pad1_ 400 +R23 Net-_Q26-Pad3_ Net-_C1-Pad2_ 160 +R27 Net-_Q25-Pad3_ Net-_Q22-Pad3_ 160 +R25 Net-_Q27-Pad3_ Net-_Q22-Pad3_ 3 +R24 Net-_Q27-Pad3_ Net-_C1-Pad2_ 0.14 +R26 Net-_R26-Pad1_ Net-_R26-Pad2_ 18k +R8 Net-_Q7-Pad3_ Net-_C1-Pad2_ 4.1k +R9 Net-_Q10-Pad2_ Net-_C1-Pad2_ 5.8k +R11 Net-_Q10-Pad3_ Net-_C1-Pad2_ 72 +R12 Net-_Q11-Pad2_ Net-_C1-Pad2_ 5.1k +R14 Net-_Q16-Pad3_ Net-_C2-Pad2_ 12k +R15 Net-_Q18-Pad3_ Net-_Q16-Pad3_ 2.4k +R16 Net-_C2-Pad2_ Net-_R16-Pad2_ 50 +R17 Net-_Q10-Pad1_ Net-_C3-Pad1_ 6.7k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30pF +C2 Net-_C1-Pad1_ Net-_C2-Pad2_ 30pF +C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 5pF + +.end diff --git a/library/SubcircuitLibrary/LM317_sub/LM317_sub.cir.out b/library/SubcircuitLibrary/LM317_sub/LM317_sub.cir.out new file mode 100644 index 00000000..2356a6de --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/LM317_sub.cir.out @@ -0,0 +1,89 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm317_sub\lm317_sub.cir + +.include NPN.lib +.include PNP.lib +.include NJF.lib +j1 net-_j1-pad1_ net-_c1-pad2_ net-_j1-pad3_ J2N3819 +q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q3 net-_q2-pad2_ net-_q1-pad1_ net-_q3-pad3_ Q2N2907A +q4 net-_q4-pad1_ net-_q2-pad2_ net-_c1-pad2_ Q2N2222 +q7 net-_q7-pad1_ net-_q4-pad1_ net-_q7-pad3_ Q2N2222 +q5 net-_c1-pad2_ net-_q4-pad1_ net-_q5-pad3_ Q2N2907A +q6 net-_q6-pad1_ net-_q1-pad1_ net-_q6-pad3_ Q2N2907A +q8 net-_q10-pad2_ net-_q7-pad1_ net-_q5-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad2_ net-_q11-pad2_ net-_q10-pad1_ Q2N2907A +q9 net-_q10-pad1_ net-_q1-pad1_ net-_q9-pad3_ Q2N2907A +q13 net-_q12-pad2_ net-_q1-pad1_ net-_q13-pad3_ Q2N2907A +q12 net-_j1-pad1_ net-_q12-pad2_ net-_q11-pad2_ Q2N2222 +q14 net-_c1-pad2_ net-_c1-pad1_ net-_q12-pad2_ Q2N2907A +q16 net-_c1-pad1_ net-_c1-pad2_ net-_q16-pad3_ Q2N2222 +q18 net-_q15-pad2_ net-_c1-pad2_ net-_q18-pad3_ Q2N2222 +q15 net-_c1-pad1_ net-_q15-pad2_ net-_q10-pad1_ Q2N2907A +q17 net-_q15-pad2_ net-_q15-pad2_ net-_q10-pad1_ Q2N2907A +q19 net-_c1-pad2_ net-_c3-pad1_ net-_q10-pad1_ Q2N2907A +q20 net-_c3-pad1_ net-_c3-pad2_ net-_c1-pad2_ Q2N2222 +q23 net-_q21-pad2_ net-_q10-pad1_ net-_q23-pad3_ Q2N2222 +q26 net-_j1-pad1_ net-_q26-pad2_ net-_q26-pad3_ Q2N2222 +q27 net-_j1-pad1_ net-_q26-pad3_ net-_q27-pad3_ Q2N2222 +q22 net-_q22-pad1_ net-_q22-pad2_ net-_q22-pad3_ Q2N2222 +q25 net-_q22-pad1_ net-_q22-pad2_ net-_q25-pad3_ Q2N2222 +q21 net-_q10-pad1_ net-_q21-pad2_ net-_j1-pad1_ Q2N2907A +q24 net-_q21-pad2_ net-_q21-pad2_ net-_j1-pad1_ Q2N2907A +* u5 net-_j1-pad1_ net-_c1-pad2_ net-_r16-pad2_ port +* u3 net-_r26-pad1_ net-_j1-pad1_ zener +* u4 net-_q25-pad3_ net-_r26-pad2_ zener +* u2 net-_c2-pad2_ net-_c1-pad2_ zener +* u1 net-_c1-pad2_ net-_j1-pad3_ zener +r13 net-_j1-pad1_ net-_q13-pad3_ 5.6k +r10 net-_j1-pad1_ net-_q9-pad3_ 82 +r6 net-_j1-pad1_ net-_q6-pad3_ 190 +r4 net-_j1-pad1_ net-_q3-pad3_ 310 +r2 net-_j1-pad1_ net-_q1-pad3_ 310 +r1 net-_j1-pad3_ net-_q2-pad2_ 200k +r5 net-_q2-pad2_ net-_q4-pad1_ 130 +r3 net-_q2-pad3_ net-_c1-pad2_ 180 +r7 net-_q6-pad1_ net-_q7-pad1_ 12.4k +r21 net-_q10-pad1_ net-_q26-pad2_ 370 +r22 net-_q23-pad3_ net-_q26-pad3_ 130 +r19 net-_q10-pad1_ net-_q22-pad2_ 12k +r18 net-_c3-pad2_ net-_q22-pad1_ 13k +r20 net-_q22-pad2_ net-_q22-pad1_ 400 +r23 net-_q26-pad3_ net-_c1-pad2_ 160 +r27 net-_q25-pad3_ net-_q22-pad3_ 160 +r25 net-_q27-pad3_ net-_q22-pad3_ 3 +r24 net-_q27-pad3_ net-_c1-pad2_ 0.14 +r26 net-_r26-pad1_ net-_r26-pad2_ 18k +r8 net-_q7-pad3_ net-_c1-pad2_ 4.1k +r9 net-_q10-pad2_ net-_c1-pad2_ 5.8k +r11 net-_q10-pad3_ net-_c1-pad2_ 72 +r12 net-_q11-pad2_ net-_c1-pad2_ 5.1k +r14 net-_q16-pad3_ net-_c2-pad2_ 12k +r15 net-_q18-pad3_ net-_q16-pad3_ 2.4k +r16 net-_c2-pad2_ net-_r16-pad2_ 50 +r17 net-_q10-pad1_ net-_c3-pad1_ 6.7k +c1 net-_c1-pad1_ net-_c1-pad2_ 30pf +c2 net-_c1-pad1_ net-_c2-pad2_ 30pf +c3 net-_c3-pad1_ net-_c3-pad2_ 5pf +a1 net-_r26-pad1_ net-_j1-pad1_ u3 +a2 net-_q25-pad3_ net-_r26-pad2_ u4 +a3 net-_c2-pad2_ net-_c1-pad2_ u2 +a4 net-_c1-pad2_ net-_j1-pad3_ u1 +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM317_sub/LM317_sub.pro b/library/SubcircuitLibrary/LM317_sub/LM317_sub.pro new file mode 100644 index 00000000..2581a099 --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/LM317_sub.pro @@ -0,0 +1,83 @@ +update=05/31/24 13:01:32 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/LM317_sub/LM317_sub.sch b/library/SubcircuitLibrary/LM317_sub/LM317_sub.sch new file mode 100644 index 00000000..ac1a8ff3 --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/LM317_sub.sch @@ -0,0 +1,1113 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM317_sub-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NJF J1 +U 1 1 66506AEF +P 900 2950 +F 0 "J1" H 800 3000 50 0000 R CNN +F 1 "eSim_NJF" H 850 3100 50 0000 R CNN +F 2 "" H 1100 3050 29 0000 C CNN +F 3 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"" H 10250 3300 60 0000 C CNN +F 3 "" H 10250 3300 60 0000 C CNN + 1 10200 3300 + 0 1 -1 0 +$EndComp +$Comp +L zener U4 +U 1 1 665409EE +P 10200 4250 +F 0 "U4" H 10150 4150 60 0000 C CNN +F 1 "zener" H 10200 4350 60 0000 C CNN +F 2 "" H 10250 4250 60 0000 C CNN +F 3 "" H 10250 4250 60 0000 C CNN + 1 10200 4250 + 0 1 -1 0 +$EndComp +$Comp +L zener U2 +U 1 1 66543707 +P 6150 5400 +F 0 "U2" H 6100 5300 60 0000 C CNN +F 1 "zener" H 6150 5500 60 0000 C CNN +F 2 "" H 6200 5400 60 0000 C CNN +F 3 "" H 6200 5400 60 0000 C CNN + 1 6150 5400 + -1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 66546061 +P 1000 4450 +F 0 "U1" H 950 4350 60 0000 C CNN +F 1 "zener" H 1000 4550 60 0000 C CNN +F 2 "" H 1050 4450 60 0000 C CNN +F 3 "" H 1050 4450 60 0000 C CNN + 1 1000 4450 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 665450CE +P 5650 2400 +F 0 "R13" H 5700 2530 50 0000 C CNN +F 1 "5.6k" H 5700 2350 50 0000 C CNN +F 2 "" H 5700 2380 30 0000 C CNN +F 3 "" V 5700 2450 30 0000 C CNN + 1 5650 2400 + 0 1 1 0 +$EndComp +Wire Wire Line + 5700 2300 5700 2250 +$Comp +L resistor R10 +U 1 1 665479CB +P 4450 2350 +F 0 "R10" H 4500 2480 50 0000 C CNN +F 1 "82" H 4500 2300 50 0000 C CNN +F 2 "" H 4500 2330 30 0000 C CNN +F 3 "" V 4500 2400 30 0000 C CNN + 1 4450 2350 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 66547C26 +P 3400 2350 +F 0 "R6" H 3450 2480 50 0000 C CNN +F 1 "190" H 3450 2300 50 0000 C CNN +F 2 "" H 3450 2330 30 0000 C CNN +F 3 "" V 3450 2400 30 0000 C CNN + 1 3400 2350 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 66549453 +P 2150 2350 +F 0 "R4" H 2200 2480 50 0000 C CNN +F 1 "310" H 2200 2300 50 0000 C CNN +F 2 "" H 2200 2330 30 0000 C CNN +F 3 "" V 2200 2400 30 0000 C CNN + 1 2150 2350 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 665497C5 +P 1450 2350 +F 0 "R2" H 1500 2480 50 0000 C CNN +F 1 "310" H 1500 2300 50 0000 C CNN +F 2 "" H 1500 2330 30 0000 C CNN +F 3 "" V 1500 2400 30 0000 C CNN + 1 1450 2350 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 6654AA03 +P 1250 3800 +F 0 "R1" H 1300 3930 50 0000 C CNN +F 1 "200k" H 1300 3750 50 0000 C CNN +F 2 "" H 1300 3780 30 0000 C CNN +F 3 "" V 1300 3850 30 0000 C CNN + 1 1250 3800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 6654AC77 +P 2150 3900 +F 0 "R5" H 2200 4030 50 0000 C CNN +F 1 "130" H 2200 3850 50 0000 C CNN +F 2 "" H 2200 3880 30 0000 C CNN +F 3 "" V 2200 3950 30 0000 C CNN + 1 2150 3900 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 6654C0FB +P 1450 4750 +F 0 "R3" H 1500 4880 50 0000 C CNN +F 1 "180" H 1500 4700 50 0000 C CNN +F 2 "" H 1500 4730 30 0000 C CNN +F 3 "" V 1500 4800 30 0000 C CNN + 1 1450 4750 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 6654FCB5 +P 3400 3550 +F 0 "R7" H 3450 3680 50 0000 C CNN +F 1 "12.4k" H 3450 3500 50 0000 C CNN +F 2 "" H 3450 3530 30 0000 C CNN +F 3 "" V 3450 3600 30 0000 C CNN + 1 3400 3550 + 0 1 1 0 +$EndComp +$Comp +L resistor R21 +U 1 1 66557F91 +P 8950 3100 +F 0 "R21" H 9000 3230 50 0000 C CNN +F 1 "370" H 9000 3050 50 0000 C CNN +F 2 "" H 9000 3080 30 0000 C CNN +F 3 "" V 9000 3150 30 0000 C CNN + 1 8950 3100 + 1 0 0 -1 +$EndComp +$Comp +L resistor R22 +U 1 1 665581F6 +P 9000 3400 +F 0 "R22" H 9050 3530 50 0000 C CNN +F 1 "130" H 9050 3350 50 0000 C CNN +F 2 "" H 9050 3380 30 0000 C CNN +F 3 "" V 9050 3450 30 0000 C CNN + 1 9000 3400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R19 +U 1 1 66558CE5 +P 8250 3150 +F 0 "R19" H 8300 3280 50 0000 C CNN +F 1 "12k" H 8300 3100 50 0000 C CNN +F 2 "" H 8300 3130 30 0000 C CNN +F 3 "" V 8300 3200 30 0000 C CNN + 1 8250 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R18 +U 1 1 6655986F +P 8200 3850 +F 0 "R18" H 8250 3980 50 0000 C CNN +F 1 "13k" H 8250 3800 50 0000 C CNN +F 2 "" H 8250 3830 30 0000 C CNN +F 3 "" V 8250 3900 30 0000 C CNN + 1 8200 3850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R20 +U 1 1 6655994E +P 8450 3550 +F 0 "R20" H 8500 3680 50 0000 C CNN +F 1 "400" H 8500 3500 50 0000 C CNN +F 2 "" H 8500 3530 30 0000 C CNN +F 3 "" V 8500 3600 30 0000 C CNN + 1 8450 3550 + 0 1 1 0 +$EndComp +$Comp +L resistor R23 +U 1 1 66559A2E +P 9450 3600 +F 0 "R23" H 9500 3730 50 0000 C CNN +F 1 "160" H 9500 3550 50 0000 C CNN +F 2 "" H 9500 3580 30 0000 C CNN +F 3 "" V 9500 3650 30 0000 C CNN + 1 9450 3600 + 0 1 1 0 +$EndComp +$Comp +L resistor R27 +U 1 1 6655C370 +P 10150 4650 +F 0 "R27" H 10200 4780 50 0000 C CNN +F 1 "160" H 10200 4600 50 0000 C CNN +F 2 "" H 10200 4630 30 0000 C CNN +F 3 "" V 10200 4700 30 0000 C CNN + 1 10150 4650 + 0 1 1 0 +$EndComp +$Comp +L resistor R25 +U 1 1 6655C6FD +P 10000 5150 +F 0 "R25" H 10050 5280 50 0000 C CNN +F 1 "3" H 10050 5100 50 0000 C CNN +F 2 "" H 10050 5130 30 0000 C CNN +F 3 "" V 10050 5200 30 0000 C CNN + 1 10000 5150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R24 +U 1 1 6655C946 +P 9750 4950 +F 0 "R24" H 9800 5080 50 0000 C CNN +F 1 "0.14" H 9800 4900 50 0000 C CNN +F 2 "" H 9800 4930 30 0000 C CNN +F 3 "" V 9800 5000 30 0000 C CNN + 1 9750 4950 + 0 1 1 0 +$EndComp +$Comp +L resistor R26 +U 1 1 6655DC8E +P 10150 3650 +F 0 "R26" H 10200 3780 50 0000 C CNN +F 1 "18k" H 10200 3600 50 0000 C CNN +F 2 "" H 10200 3630 30 0000 C CNN +F 3 "" V 10200 3700 30 0000 C CNN + 1 10150 3650 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 6656252B +P 3400 4700 +F 0 "R8" H 3450 4830 50 0000 C CNN +F 1 "4.1k" H 3450 4650 50 0000 C CNN +F 2 "" H 3450 4680 30 0000 C CNN +F 3 "" V 3450 4750 30 0000 C CNN + 1 3400 4700 + 0 1 1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 66562858 +P 4050 4700 +F 0 "R9" H 4100 4830 50 0000 C CNN +F 1 "5.8k" H 4100 4650 50 0000 C CNN +F 2 "" H 4100 4680 30 0000 C CNN +F 3 "" V 4100 4750 30 0000 C CNN + 1 4050 4700 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 66562A20 +P 4450 4700 +F 0 "R11" H 4500 4830 50 0000 C CNN +F 1 "72" H 4500 4650 50 0000 C CNN +F 2 "" H 4500 4680 30 0000 C CNN +F 3 "" V 4500 4750 30 0000 C CNN + 1 4450 4700 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 66562C6D +P 5250 4700 +F 0 "R12" H 5300 4830 50 0000 C CNN +F 1 "5.1k" H 5300 4650 50 0000 C CNN +F 2 "" H 5300 4680 30 0000 C CNN +F 3 "" V 5300 4750 30 0000 C CNN + 1 5250 4700 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 66562F78 +P 6550 4950 +F 0 "R14" H 6600 5080 50 0000 C CNN +F 1 "12k" H 6600 4900 50 0000 C CNN +F 2 "" H 6600 4930 30 0000 C CNN +F 3 "" V 6600 5000 30 0000 C CNN + 1 6550 4950 + 0 1 1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 665631A5 +P 6950 4600 +F 0 "R15" H 7000 4730 50 0000 C CNN +F 1 "2.4k" H 7000 4550 50 0000 C CNN +F 2 "" H 7000 4580 30 0000 C CNN +F 3 "" V 7000 4650 30 0000 C CNN + 1 6950 4600 + 0 1 1 0 +$EndComp +$Comp +L resistor R16 +U 1 1 66563564 +P 7000 5450 +F 0 "R16" H 7050 5580 50 0000 C CNN +F 1 "50" H 7050 5400 50 0000 C CNN +F 2 "" H 7050 5430 30 0000 C CNN +F 3 "" V 7050 5500 30 0000 C CNN + 1 7000 5450 + 1 0 0 -1 +$EndComp +$Comp +L resistor R17 +U 1 1 66563996 +P 7650 3150 +F 0 "R17" H 7700 3280 50 0000 C CNN +F 1 "6.7k" H 7700 3100 50 0000 C CNN +F 2 "" H 7700 3130 30 0000 C CNN +F 3 "" V 7700 3200 30 0000 C CNN + 1 7650 3150 + 0 1 1 0 +$EndComp +$Comp +L capacitor C1 +U 1 1 66566EB0 +P 6100 4350 +F 0 "C1" H 6125 4450 50 0000 L CNN +F 1 "30pF" H 6125 4250 50 0000 L CNN +F 2 "" H 6138 4200 30 0000 C CNN +F 3 "" H 6100 4350 60 0000 C CNN + 1 6100 4350 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 665670BB +P 6350 4700 +F 0 "C2" H 6375 4800 50 0000 L CNN +F 1 "30pF" H 6375 4600 50 0000 L CNN +F 2 "" H 6388 4550 30 0000 C CNN +F 3 "" H 6350 4700 60 0000 C CNN + 1 6350 4700 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C3 +U 1 1 66567315 +P 8050 3550 +F 0 "C3" H 8075 3650 50 0000 L CNN +F 1 "5pF" H 8075 3450 50 0000 L CNN +F 2 "" H 8088 3400 30 0000 C CNN +F 3 "" H 8050 3550 60 0000 C CNN + 1 8050 3550 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM317_sub/LM317_sub.sub b/library/SubcircuitLibrary/LM317_sub/LM317_sub.sub new file mode 100644 index 00000000..ffd8e037 --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/LM317_sub.sub @@ -0,0 +1,83 @@ +* Subcircuit LM317_sub +.subckt LM317_sub net-_j1-pad1_ net-_c1-pad2_ net-_r16-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\lm317_sub\lm317_sub.cir +.include NPN.lib +.include PNP.lib +.include NJF.lib +j1 net-_j1-pad1_ net-_c1-pad2_ net-_j1-pad3_ J2N3819 +q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222 +q3 net-_q2-pad2_ net-_q1-pad1_ net-_q3-pad3_ Q2N2907A +q4 net-_q4-pad1_ net-_q2-pad2_ net-_c1-pad2_ Q2N2222 +q7 net-_q7-pad1_ net-_q4-pad1_ net-_q7-pad3_ Q2N2222 +q5 net-_c1-pad2_ net-_q4-pad1_ net-_q5-pad3_ Q2N2907A +q6 net-_q6-pad1_ net-_q1-pad1_ net-_q6-pad3_ Q2N2907A +q8 net-_q10-pad2_ net-_q7-pad1_ net-_q5-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_c1-pad2_ net-_q11-pad2_ net-_q10-pad1_ Q2N2907A +q9 net-_q10-pad1_ net-_q1-pad1_ net-_q9-pad3_ Q2N2907A +q13 net-_q12-pad2_ net-_q1-pad1_ net-_q13-pad3_ Q2N2907A +q12 net-_j1-pad1_ net-_q12-pad2_ net-_q11-pad2_ Q2N2222 +q14 net-_c1-pad2_ net-_c1-pad1_ net-_q12-pad2_ Q2N2907A +q16 net-_c1-pad1_ net-_c1-pad2_ net-_q16-pad3_ Q2N2222 +q18 net-_q15-pad2_ net-_c1-pad2_ net-_q18-pad3_ Q2N2222 +q15 net-_c1-pad1_ net-_q15-pad2_ net-_q10-pad1_ Q2N2907A +q17 net-_q15-pad2_ net-_q15-pad2_ net-_q10-pad1_ Q2N2907A +q19 net-_c1-pad2_ net-_c3-pad1_ net-_q10-pad1_ Q2N2907A +q20 net-_c3-pad1_ net-_c3-pad2_ net-_c1-pad2_ Q2N2222 +q23 net-_q21-pad2_ net-_q10-pad1_ net-_q23-pad3_ Q2N2222 +q26 net-_j1-pad1_ net-_q26-pad2_ net-_q26-pad3_ Q2N2222 +q27 net-_j1-pad1_ net-_q26-pad3_ net-_q27-pad3_ Q2N2222 +q22 net-_q22-pad1_ net-_q22-pad2_ net-_q22-pad3_ Q2N2222 +q25 net-_q22-pad1_ net-_q22-pad2_ net-_q25-pad3_ Q2N2222 +q21 net-_q10-pad1_ net-_q21-pad2_ net-_j1-pad1_ Q2N2907A +q24 net-_q21-pad2_ net-_q21-pad2_ net-_j1-pad1_ Q2N2907A +* u3 net-_r26-pad1_ net-_j1-pad1_ zener +* u4 net-_q25-pad3_ net-_r26-pad2_ zener +* u2 net-_c2-pad2_ net-_c1-pad2_ zener +* u1 net-_c1-pad2_ net-_j1-pad3_ zener +r13 net-_j1-pad1_ net-_q13-pad3_ 5.6k +r10 net-_j1-pad1_ net-_q9-pad3_ 82 +r6 net-_j1-pad1_ net-_q6-pad3_ 190 +r4 net-_j1-pad1_ net-_q3-pad3_ 310 +r2 net-_j1-pad1_ net-_q1-pad3_ 310 +r1 net-_j1-pad3_ net-_q2-pad2_ 200k +r5 net-_q2-pad2_ net-_q4-pad1_ 130 +r3 net-_q2-pad3_ net-_c1-pad2_ 180 +r7 net-_q6-pad1_ net-_q7-pad1_ 12.4k +r21 net-_q10-pad1_ net-_q26-pad2_ 370 +r22 net-_q23-pad3_ net-_q26-pad3_ 130 +r19 net-_q10-pad1_ net-_q22-pad2_ 12k +r18 net-_c3-pad2_ net-_q22-pad1_ 13k +r20 net-_q22-pad2_ net-_q22-pad1_ 400 +r23 net-_q26-pad3_ net-_c1-pad2_ 160 +r27 net-_q25-pad3_ net-_q22-pad3_ 160 +r25 net-_q27-pad3_ net-_q22-pad3_ 3 +r24 net-_q27-pad3_ net-_c1-pad2_ 0.14 +r26 net-_r26-pad1_ net-_r26-pad2_ 18k +r8 net-_q7-pad3_ net-_c1-pad2_ 4.1k +r9 net-_q10-pad2_ net-_c1-pad2_ 5.8k +r11 net-_q10-pad3_ net-_c1-pad2_ 72 +r12 net-_q11-pad2_ net-_c1-pad2_ 5.1k +r14 net-_q16-pad3_ net-_c2-pad2_ 12k +r15 net-_q18-pad3_ net-_q16-pad3_ 2.4k +r16 net-_c2-pad2_ net-_r16-pad2_ 50 +r17 net-_q10-pad1_ net-_c3-pad1_ 6.7k +c1 net-_c1-pad1_ net-_c1-pad2_ 30pf +c2 net-_c1-pad1_ net-_c2-pad2_ 30pf +c3 net-_c3-pad1_ net-_c3-pad2_ 5pf +a1 net-_r26-pad1_ net-_j1-pad1_ u3 +a2 net-_q25-pad3_ net-_r26-pad2_ u4 +a3 net-_c2-pad2_ net-_c1-pad2_ u2 +a4 net-_c1-pad2_ net-_j1-pad3_ u1 +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM317_sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM317_sub/LM317_sub_Previous_Values.xml b/library/SubcircuitLibrary/LM317_sub/LM317_sub_Previous_Values.xml new file mode 100644 index 00000000..73c8daf0 --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/LM317_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u3><u4 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u4><u2 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)" /><field12 name="Enter Breakdown Current (default=2.0e-2)" /><field13 name="Enter Saturation Current (default=1.0e-12)" /><field14 name="Enter Forward Emission Coefficient (default=1.0)" /><field15 name="Enter Switch for Limiting (default=FALSE)" /></u2><u1 name="type">zener<field16 name="Enter Breakdown Voltage (default=5.6)" /><field17 name="Enter Breakdown Current (default=2.0e-2)" /><field18 name="Enter Saturation Current (default=1.0e-12)" /><field19 name="Enter Forward Emission Coefficient (default=1.0)" /><field20 name="Enter Switch for Limiting (default=FALSE)" /></u1></model><devicemodel><j1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q11><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q13><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q14><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q19><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q23><q26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q26><q27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q27><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q25><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q21><q24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q24></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM317_sub/NJF.lib b/library/SubcircuitLibrary/LM317_sub/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM317_sub/NPN.lib b/library/SubcircuitLibrary/LM317_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM317_sub/PNP.lib b/library/SubcircuitLibrary/LM317_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM317_sub/analysis b/library/SubcircuitLibrary/LM317_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM317_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM342/LM342-cache.lib b/library/SubcircuitLibrary/LM342/LM342-cache.lib new file mode 100644 index 00000000..dd93a8cb --- /dev/null +++ b/library/SubcircuitLibrary/LM342/LM342-cache.lib @@ -0,0 +1,171 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM342/LM342.cir b/library/SubcircuitLibrary/LM342/LM342.cir new file mode 100644 index 00000000..d5ac4fe7 --- /dev/null +++ b/library/SubcircuitLibrary/LM342/LM342.cir @@ -0,0 +1,49 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM342\LM342.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/10/24 17:45:07 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +J1 Net-_J1-Pad1_ GND Net-_J1-Pad3_ jfet_n +R1 Net-_J1-Pad1_ Net-_Q2-Pad3_ 418 +Q2 Net-_Q1-Pad3_ Net-_Q1-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q8 Net-_Q12-Pad3_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q1 Net-_Q1-Pad1_ Net-_J1-Pad3_ Net-_Q1-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad3_ Net-_Q4-Pad3_ eSim_NPN +R2 Net-_Q4-Pad3_ Net-_Q7-Pad2_ 576 +R3 Net-_Q7-Pad2_ Net-_R3-Pad2_ 3.41k +Q7 Net-_Q7-Pad1_ Net-_Q7-Pad2_ Net-_Q4-Pad3_ eSim_PNP +U1 GND Net-_J1-Pad3_ zener +U2 GND Net-_Q1-Pad3_ zener +R4 Net-_R3-Pad2_ Net-_Q11-Pad2_ 3.89k +R5 Net-_Q7-Pad1_ GND 7.8k +Q9 Net-_Q12-Pad3_ Net-_Q7-Pad1_ GND eSim_NPN +R6 Net-_Q10-Pad2_ Net-_R3-Pad2_ 13k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q5 Net-_Q11-Pad2_ Net-_Q11-Pad2_ Net-_Q5-Pad3_ eSim_NPN +Q6 Net-_Q5-Pad3_ Net-_Q5-Pad3_ GND eSim_NPN +Q11 Net-_Q10-Pad3_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R7 Net-_Q11-Pad3_ GND 2.84k +Q12 GND Net-_C1-Pad2_ Net-_Q12-Pad3_ eSim_PNP +Q13 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R8 Net-_C1-Pad2_ Net-_Q12-Pad3_ 5.76k +Q14 Net-_Q12-Pad3_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R9 Net-_R13-Pad1_ Net-_Q14-Pad3_ 100 +Q15 Net-_J1-Pad1_ Net-_Q12-Pad3_ Net-_Q10-Pad1_ eSim_NPN +U4 Net-_Q14-Pad2_ Net-_R10-Pad1_ zener +R10 Net-_R10-Pad1_ Net-_R10-Pad2_ 5k +U3 Net-_R10-Pad2_ Net-_J1-Pad1_ zener +Q16 Net-_J1-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN +R13 Net-_R13-Pad1_ Net-_Q10-Pad1_ 2.5k +R15 Net-_R13-Pad1_ Net-_Q16-Pad3_ 1.9 +R11 Net-_Q14-Pad2_ Net-_Q16-Pad3_ 100 +R16 Net-_R12-Pad2_ Net-_R13-Pad1_ 1.4K +R12 Net-_C1-Pad1_ Net-_R12-Pad2_ 15k +R14 Net-_R12-Pad2_ GND 2.23k +U5 Net-_J1-Pad1_ Net-_R13-Pad1_ GND PORT +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 5pF + +.end diff --git a/library/SubcircuitLibrary/LM342/LM342.cir.out b/library/SubcircuitLibrary/LM342/LM342.cir.out new file mode 100644 index 00000000..5704bb53 --- /dev/null +++ b/library/SubcircuitLibrary/LM342/LM342.cir.out @@ -0,0 +1,65 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm342\lm342.cir + +.include NPN.lib +.include PNP.lib +.include NJF.lib +j1 net-_j1-pad1_ gnd net-_j1-pad3_ J2N3819 +r1 net-_j1-pad1_ net-_q2-pad3_ 418 +q2 net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ Q2N2907A +q3 net-_q1-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q8 net-_q12-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q1 net-_q1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q4 net-_q1-pad1_ net-_q1-pad3_ net-_q4-pad3_ Q2N2222 +r2 net-_q4-pad3_ net-_q7-pad2_ 576 +r3 net-_q7-pad2_ net-_r3-pad2_ 3.41k +q7 net-_q7-pad1_ net-_q7-pad2_ net-_q4-pad3_ Q2N2907A +* u1 gnd net-_j1-pad3_ zener +* u2 gnd net-_q1-pad3_ zener +r4 net-_r3-pad2_ net-_q11-pad2_ 3.89k +r5 net-_q7-pad1_ gnd 7.8k +q9 net-_q12-pad3_ net-_q7-pad1_ gnd Q2N2222 +r6 net-_q10-pad2_ net-_r3-pad2_ 13k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q5 net-_q11-pad2_ net-_q11-pad2_ net-_q5-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q5-pad3_ gnd Q2N2222 +q11 net-_q10-pad3_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +r7 net-_q11-pad3_ gnd 2.84k +q12 gnd net-_c1-pad2_ net-_q12-pad3_ Q2N2907A +q13 net-_c1-pad2_ net-_c1-pad1_ net-_q10-pad3_ Q2N2222 +r8 net-_c1-pad2_ net-_q12-pad3_ 5.76k +q14 net-_q12-pad3_ net-_q14-pad2_ net-_q14-pad3_ Q2N2222 +r9 net-_r13-pad1_ net-_q14-pad3_ 100 +q15 net-_j1-pad1_ net-_q12-pad3_ net-_q10-pad1_ Q2N2222 +* u4 net-_q14-pad2_ net-_r10-pad1_ zener +r10 net-_r10-pad1_ net-_r10-pad2_ 5k +* u3 net-_r10-pad2_ net-_j1-pad1_ zener +q16 net-_j1-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +r13 net-_r13-pad1_ net-_q10-pad1_ 2.5k +r15 net-_r13-pad1_ net-_q16-pad3_ 1.9 +r11 net-_q14-pad2_ net-_q16-pad3_ 100 +r16 net-_r12-pad2_ net-_r13-pad1_ 1.4k +r12 net-_c1-pad1_ net-_r12-pad2_ 15k +r14 net-_r12-pad2_ gnd 2.23k +* u5 net-_j1-pad1_ net-_r13-pad1_ gnd port +c1 net-_c1-pad1_ net-_c1-pad2_ 5pf +a1 gnd net-_j1-pad3_ u1 +a2 gnd net-_q1-pad3_ u2 +a3 net-_q14-pad2_ net-_r10-pad1_ u4 +a4 net-_r10-pad2_ net-_j1-pad1_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM342/LM342.pro b/library/SubcircuitLibrary/LM342/LM342.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM342/LM342.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM342/LM342.proj b/library/SubcircuitLibrary/LM342/LM342.proj new file mode 100644 index 00000000..0b64de5c --- /dev/null +++ b/library/SubcircuitLibrary/LM342/LM342.proj @@ -0,0 +1 @@ +schematicFile IC.sch diff --git a/library/SubcircuitLibrary/LM342/LM342.sch b/library/SubcircuitLibrary/LM342/LM342.sch new file mode 100644 index 00000000..fe16e900 --- /dev/null +++ b/library/SubcircuitLibrary/LM342/LM342.sch @@ -0,0 +1,712 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM342-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L jfet_n J1 +U 1 1 6654C123 +P 2900 2550 +F 0 "J1" H 2800 2600 50 0000 R CNN +F 1 "jfet_n" H 2850 2700 50 0000 R CNN +F 2 "" H 3100 2650 29 0000 C CNN +F 3 "" H 2900 2550 60 0000 C CNN + 1 2900 2550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 6654C17C +P 3650 1950 +F 0 "R1" H 3700 2080 50 0000 C CNN +F 1 "418" H 3700 1900 50 0000 C CNN +F 2 "" H 3700 1930 30 0000 C CNN +F 3 "" V 3700 2000 30 0000 C CNN + 1 3650 1950 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 6654C272 +P 3800 2350 +F 0 "Q2" H 3700 2400 50 0000 R CNN +F 1 "eSim_PNP" H 3750 2500 50 0000 R CNN +F 2 "" H 4000 2450 29 0000 C CNN +F 3 "" H 3800 2350 60 0000 C CNN + 1 3800 2350 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 6654C2A6 +P 4200 2350 +F 0 "Q3" H 4100 2400 50 0000 R CNN +F 1 "eSim_PNP" H 4150 2500 50 0000 R CNN +F 2 "" H 4400 2450 29 0000 C CNN +F 3 "" H 4200 2350 60 0000 C CNN + 1 4200 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 6654C2E2 +P 4650 2350 +F 0 "Q8" H 4550 2400 50 0000 R CNN +F 1 "eSim_PNP" H 4600 2500 50 0000 R CNN +F 2 "" H 4850 2450 29 0000 C CNN +F 3 "" H 4650 2350 60 0000 C CNN + 1 4650 2350 + 1 0 0 1 +$EndComp +Wire Wire Line + 4450 2350 4450 2050 +Wire Wire Line + 4450 2050 4000 2050 +Wire Wire Line + 4000 2050 4000 2650 +Wire Wire Line + 4300 2150 4300 1950 +Wire Wire Line + 4300 1950 4750 1950 +Wire Wire Line + 4750 1950 4750 2150 +Wire Wire Line + 4500 1850 4500 1950 +Wire Wire Line + 3000 1850 8900 1850 +Connection ~ 4500 1950 +Wire Wire Line + 3000 2350 3000 1850 +Connection ~ 3700 1850 +Connection ~ 4000 2350 +$Comp +L eSim_NPN Q1 +U 1 1 6654C341 +P 3200 3000 +F 0 "Q1" H 3100 3050 50 0000 R CNN +F 1 "eSim_NPN" H 3150 3150 50 0000 R CNN +F 2 "" H 3400 3100 29 0000 C CNN +F 3 "" H 3200 3000 60 0000 C CNN + 1 3200 3000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 6654C386 +P 4200 3000 +F 0 "Q4" H 4100 3050 50 0000 R CNN +F 1 "eSim_NPN" H 4150 3150 50 0000 R CNN +F 2 "" H 4400 3100 29 0000 C CNN +F 3 "" H 4200 3000 60 0000 C CNN + 1 4200 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 2550 4300 2800 +Wire Wire Line + 4000 2650 4300 2650 +Connection ~ 4300 2650 +Wire Wire Line + 4300 2800 3300 2800 +Wire Wire Line + 3000 2750 3000 4000 +Wire Wire Line + 3300 3200 3300 3250 +Wire Wire Line + 3300 3250 4000 3250 +Wire Wire Line + 4000 3250 4000 3000 +$Comp +L resistor R2 +U 1 1 6654C4BA +P 4250 3450 +F 0 "R2" H 4300 3580 50 0000 C CNN +F 1 "576" H 4300 3400 50 0000 C CNN +F 2 "" H 4300 3430 30 0000 C CNN +F 3 "" V 4300 3500 30 0000 C CNN + 1 4250 3450 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 6654C52C +P 4250 3950 +F 0 "R3" H 4300 4080 50 0000 C CNN +F 1 "3.41k" H 4300 3900 50 0000 C CNN +F 2 "" H 4300 3930 30 0000 C CNN +F 3 "" V 4300 4000 30 0000 C CNN + 1 4250 3950 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 6654C567 +P 4500 3750 +F 0 "Q7" H 4400 3800 50 0000 R CNN +F 1 "eSim_PNP" H 4450 3900 50 0000 R CNN +F 2 "" H 4700 3850 29 0000 C CNN +F 3 "" H 4500 3750 60 0000 C CNN + 1 4500 3750 + 1 0 0 1 +$EndComp +Wire Wire Line + 4300 3200 4300 3350 +Wire Wire Line + 4300 3650 4300 3850 +Connection ~ 4300 3750 +Wire Wire Line + 4600 3550 4600 3250 +Wire Wire Line + 4600 3250 4300 3250 +Connection ~ 4300 3250 +$Comp +L zener U1 +U 1 1 6654C7D3 +P 3000 4300 +F 0 "U1" H 2950 4200 60 0000 C CNN +F 1 "zener" H 3000 4400 60 0000 C CNN +F 2 "" H 3050 4300 60 0000 C CNN +F 3 "" H 3050 4300 60 0000 C CNN + 1 3000 4300 + 0 -1 -1 0 +$EndComp +$Comp +L zener U2 +U 1 1 6654C819 +P 3550 4300 +F 0 "U2" H 3500 4200 60 0000 C CNN +F 1 "zener" H 3550 4400 60 0000 C CNN +F 2 "" H 3600 4300 60 0000 C CNN +F 3 "" H 3600 4300 60 0000 C CNN + 1 3550 4300 + 0 1 -1 0 +$EndComp +Connection ~ 3000 3000 +$Comp +L resistor R4 +U 1 1 6654C8AF +P 4250 4750 +F 0 "R4" H 4300 4880 50 0000 C CNN +F 1 "3.89k" H 4300 4700 50 0000 C CNN +F 2 "" H 4300 4730 30 0000 C CNN +F 3 "" V 4300 4800 30 0000 C CNN + 1 4250 4750 + 0 1 1 0 +$EndComp +Wire Wire Line + 4300 4650 4300 4150 +$Comp +L resistor R5 +U 1 1 6654C938 +P 4550 4750 +F 0 "R5" H 4600 4880 50 0000 C CNN +F 1 "7.8k" H 4600 4700 50 0000 C CNN +F 2 "" H 4600 4730 30 0000 C CNN +F 3 "" V 4600 4800 30 0000 C CNN + 1 4550 4750 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 6654C986 +P 4800 4400 +F 0 "Q9" H 4700 4450 50 0000 R CNN +F 1 "eSim_NPN" H 4750 4550 50 0000 R CNN +F 2 "" H 5000 4500 29 0000 C CNN +F 3 "" H 4800 4400 60 0000 C CNN + 1 4800 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4750 2550 7550 2550 +Wire Wire Line + 4900 2550 4900 4200 +Wire Wire Line + 4600 3950 4600 4650 +Connection ~ 4600 4400 +$Comp +L resistor R6 +U 1 1 6654CBA7 +P 5400 4100 +F 0 "R6" H 5450 4230 50 0000 C CNN +F 1 "13k" H 5450 4050 50 0000 C CNN +F 2 "" H 5450 4080 30 0000 C CNN +F 3 "" V 5450 4150 30 0000 C CNN + 1 5400 4100 + -1 0 0 1 +$EndComp +Wire Wire Line + 4300 4150 5200 4150 +$Comp +L eSim_NPN Q10 +U 1 1 6654CC43 +P 5700 4150 +F 0 "Q10" H 5600 4200 50 0000 R CNN +F 1 "eSim_NPN" H 5650 4300 50 0000 R CNN +F 2 "" H 5900 4250 29 0000 C CNN +F 3 "" H 5700 4150 60 0000 C CNN + 1 5700 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3550 2550 3550 4000 +Connection ~ 3550 3250 +Wire Wire Line + 3550 2550 3700 2550 +$Comp +L eSim_NPN Q5 +U 1 1 6654D001 +P 4200 5250 +F 0 "Q5" H 4100 5300 50 0000 R CNN +F 1 "eSim_NPN" H 4150 5400 50 0000 R CNN +F 2 "" H 4400 5350 29 0000 C CNN +F 3 "" H 4200 5250 60 0000 C CNN + 1 4200 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 6654D077 +P 4200 5750 +F 0 "Q6" H 4100 5800 50 0000 R CNN +F 1 "eSim_NPN" H 4150 5900 50 0000 R CNN +F 2 "" H 4400 5850 29 0000 C CNN +F 3 "" H 4200 5750 60 0000 C CNN + 1 4200 5750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4000 5750 4000 5500 +Wire Wire Line + 4000 5500 4300 5500 +Wire Wire Line + 4300 5450 4300 5550 +Connection ~ 4300 5500 +Wire Wire Line + 4000 5000 4300 5000 +Wire Wire Line + 4300 4950 4300 5050 +Connection ~ 4300 5000 +$Comp +L eSim_NPN Q11 +U 1 1 6654D1D8 +P 5700 5250 +F 0 "Q11" H 5600 5300 50 0000 R CNN +F 1 "eSim_NPN" H 5650 5400 50 0000 R CNN +F 2 "" H 5900 5350 29 0000 C CNN +F 3 "" H 5700 5250 60 0000 C CNN + 1 5700 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 6654D303 +P 5750 5700 +F 0 "R7" H 5800 5830 50 0000 C CNN +F 1 "2.84k" H 5800 5650 50 0000 C CNN +F 2 "" H 5800 5680 30 0000 C CNN +F 3 "" V 5800 5750 30 0000 C CNN + 1 5750 5700 + 0 1 1 0 +$EndComp +Wire Wire Line + 5800 5600 5800 5450 +Wire Wire Line + 4300 6100 4300 5950 +Wire Wire Line + 2600 6100 8850 6100 +Wire Wire Line + 3000 6100 3000 4500 +Wire Wire Line + 3550 4500 3550 6100 +Connection ~ 3550 6100 +Wire Wire Line + 4600 6100 4600 4950 +Connection ~ 4300 6100 +Wire Wire Line + 4900 6100 4900 4600 +Connection ~ 4600 6100 +Wire Wire Line + 5800 6100 5800 5900 +Connection ~ 4900 6100 +Wire Wire Line + 2600 6100 2600 2550 +Wire Wire Line + 2600 2550 2700 2550 +Connection ~ 3000 6100 +Wire Wire Line + 5800 4350 5800 5050 +$Comp +L eSim_PNP Q12 +U 1 1 6654DE46 +P 6200 3050 +F 0 "Q12" H 6100 3100 50 0000 R CNN +F 1 "eSim_PNP" H 6150 3200 50 0000 R CNN +F 2 "" H 6400 3150 29 0000 C CNN +F 3 "" H 6200 3050 60 0000 C CNN + 1 6200 3050 + -1 0 0 1 +$EndComp +Connection ~ 4900 2550 +Wire Wire Line + 6100 6100 6100 3250 +Connection ~ 5800 6100 +$Comp +L eSim_NPN Q13 +U 1 1 6654EC26 +P 6550 4150 +F 0 "Q13" H 6450 4200 50 0000 R CNN +F 1 "eSim_NPN" H 6500 4300 50 0000 R CNN +F 2 "" H 6750 4250 29 0000 C CNN +F 3 "" H 6550 4150 60 0000 C CNN + 1 6550 4150 + -1 0 0 -1 +$EndComp +Wire Wire Line + 6450 4350 5800 4350 +Connection ~ 5800 4350 +Wire Wire Line + 6450 2900 6450 3950 +Wire Wire Line + 6450 3850 6800 3850 +Wire Wire Line + 7250 3850 7250 4150 +Wire Wire Line + 6750 4150 7800 4150 +Connection ~ 6450 3850 +Wire Wire Line + 6400 3050 6450 3050 +$Comp +L resistor R8 +U 1 1 6654F024 +P 6500 2800 +F 0 "R8" H 6550 2930 50 0000 C CNN +F 1 "5.76k" H 6550 2750 50 0000 C CNN +F 2 "" H 6550 2780 30 0000 C CNN +F 3 "" V 6550 2850 30 0000 C CNN + 1 6500 2800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6100 2550 6100 2850 +Wire Wire Line + 6450 2550 6450 2600 +Connection ~ 6100 2550 +Connection ~ 6450 3050 +$Comp +L eSim_NPN Q14 +U 1 1 6654FDD3 +P 6950 2850 +F 0 "Q14" H 6850 2900 50 0000 R CNN +F 1 "eSim_NPN" H 6900 3000 50 0000 R CNN +F 2 "" H 7150 2950 29 0000 C CNN +F 3 "" H 6950 2850 60 0000 C CNN + 1 6950 2850 + -1 0 0 -1 +$EndComp +Wire Wire Line + 6850 2550 6850 2650 +Connection ~ 6450 2550 +$Comp +L resistor R9 +U 1 1 6654FECC +P 6900 3250 +F 0 "R9" H 6950 3380 50 0000 C CNN +F 1 "100" H 6950 3200 50 0000 C CNN +F 2 "" H 6950 3230 30 0000 C CNN +F 3 "" V 6950 3300 30 0000 C CNN + 1 6900 3250 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 66550825 +P 7750 2550 +F 0 "Q15" H 7650 2600 50 0000 R CNN +F 1 "eSim_NPN" H 7700 2700 50 0000 R CNN +F 2 "" H 7950 2650 29 0000 C CNN +F 3 "" H 7750 2550 60 0000 C CNN + 1 7750 2550 + 1 0 0 -1 +$EndComp +$Comp +L zener U4 +U 1 1 665508B7 +P 7350 3100 +F 0 "U4" H 7300 3000 60 0000 C CNN +F 1 "zener" H 7350 3200 60 0000 C CNN +F 2 "" H 7400 3100 60 0000 C CNN +F 3 "" H 7400 3100 60 0000 C CNN + 1 7350 3100 + 0 1 -1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 66550937 +P 7400 2700 +F 0 "R10" H 7450 2830 50 0000 C CNN +F 1 "5k" H 7450 2650 50 0000 C CNN +F 2 "" H 7450 2680 30 0000 C CNN +F 3 "" V 7450 2750 30 0000 C CNN + 1 7400 2700 + 0 -1 -1 0 +$EndComp +$Comp +L zener U3 +U 1 1 665509D5 +P 7350 2300 +F 0 "U3" H 7300 2200 60 0000 C CNN +F 1 "zener" H 7350 2400 60 0000 C CNN +F 2 "" H 7400 2300 60 0000 C CNN +F 3 "" H 7400 2300 60 0000 C CNN + 1 7350 2300 + 0 1 -1 0 +$EndComp +Wire Wire Line + 7150 2850 7150 3300 +Wire Wire Line + 7150 3300 7450 3300 +Connection ~ 6850 2550 +Wire Wire Line + 7350 1850 7350 2000 +Connection ~ 4500 1850 +Wire Wire Line + 7850 1850 7850 2350 +Connection ~ 7350 1850 +$Comp +L eSim_NPN Q16 +U 1 1 6655252E +P 8600 2750 +F 0 "Q16" H 8500 2800 50 0000 R CNN +F 1 "eSim_NPN" H 8550 2900 50 0000 R CNN +F 2 "" H 8800 2850 29 0000 C CNN +F 3 "" H 8600 2750 60 0000 C CNN + 1 8600 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8700 1850 8700 2550 +Connection ~ 7850 1850 +Wire Wire Line + 7850 2750 8400 2750 +Wire Wire Line + 8050 2750 8050 3700 +Wire Wire Line + 8050 3700 5800 3700 +Wire Wire Line + 5800 3700 5800 3950 +Connection ~ 8050 2750 +$Comp +L resistor R13 +U 1 1 66552759 +P 8350 3200 +F 0 "R13" H 8400 3330 50 0000 C CNN +F 1 "2.5k" H 8400 3150 50 0000 C CNN +F 2 "" H 8400 3180 30 0000 C CNN +F 3 "" V 8400 3250 30 0000 C CNN + 1 8350 3200 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8300 3000 8300 2750 +Connection ~ 8300 2750 +Wire Wire Line + 8300 3300 8300 3500 +Wire Wire Line + 6850 3500 8900 3500 +Wire Wire Line + 6850 3500 6850 3350 +$Comp +L resistor R15 +U 1 1 66552912 +P 8750 3200 +F 0 "R15" H 8800 3330 50 0000 C CNN +F 1 "1.9" H 8800 3150 50 0000 C CNN +F 2 "" H 8800 3180 30 0000 C CNN +F 3 "" V 8800 3250 30 0000 C CNN + 1 8750 3200 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 66552994 +P 7550 3350 +F 0 "R11" H 7600 3480 50 0000 C CNN +F 1 "100" H 7600 3300 50 0000 C CNN +F 2 "" H 7600 3330 30 0000 C CNN +F 3 "" V 7600 3400 30 0000 C CNN + 1 7550 3350 + 1 0 0 -1 +$EndComp +Connection ~ 7350 3300 +Wire Wire Line + 7750 3300 7750 3000 +Wire Wire Line + 7750 3000 8700 3000 +Wire Wire Line + 8700 3000 8700 2950 +Wire Wire Line + 8700 3300 8700 3650 +Connection ~ 8300 3500 +Connection ~ 8900 3500 +Connection ~ 8700 3500 +$Comp +L resistor R16 +U 1 1 665532F1 +P 8750 3850 +F 0 "R16" H 8800 3980 50 0000 C CNN +F 1 "1.4K" H 8800 3800 50 0000 C CNN +F 2 "" H 8800 3830 30 0000 C CNN +F 3 "" V 8800 3900 30 0000 C CNN + 1 8750 3850 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 66553383 +P 7900 4200 +F 0 "R12" H 7950 4330 50 0000 C CNN +F 1 "15k" H 7950 4150 50 0000 C CNN +F 2 "" H 7950 4180 30 0000 C CNN +F 3 "" V 7950 4250 30 0000 C CNN + 1 7900 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8100 4150 8700 4150 +Wire Wire Line + 8700 3950 8700 4950 +$Comp +L resistor R14 +U 1 1 66553D5B +P 8650 5050 +F 0 "R14" H 8700 5180 50 0000 C CNN +F 1 "2.23k" H 8700 5000 50 0000 C CNN +F 2 "" H 8700 5030 30 0000 C CNN +F 3 "" V 8700 5100 30 0000 C CNN + 1 8650 5050 + 0 1 1 0 +$EndComp +Connection ~ 8700 4150 +Wire Wire Line + 8700 6100 8700 5250 +Connection ~ 6100 6100 +Connection ~ 8850 6100 +Connection ~ 8700 6100 +Connection ~ 8900 1850 +Connection ~ 8700 1850 +Connection ~ 7250 4150 +Wire Wire Line + 7100 3850 7250 3850 +$Comp +L PORT U5 +U 2 1 66558894 +P 9150 3500 +F 0 "U5" H 9200 3600 30 0000 C CNN +F 1 "PORT" H 9150 3500 30 0000 C CNN +F 2 "" H 9150 3500 60 0000 C CNN +F 3 "" H 9150 3500 60 0000 C CNN + 2 9150 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 3 1 66558905 +P 9100 6100 +F 0 "U5" H 9150 6200 30 0000 C CNN +F 1 "PORT" H 9100 6100 30 0000 C CNN +F 2 "" H 9100 6100 60 0000 C CNN +F 3 "" H 9100 6100 60 0000 C CNN + 3 9100 6100 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 1 1 66558976 +P 9150 1850 +F 0 "U5" H 9200 1950 30 0000 C CNN +F 1 "PORT" H 9150 1850 30 0000 C CNN +F 2 "" H 9150 1850 60 0000 C CNN +F 3 "" H 9150 1850 60 0000 C CNN + 1 9150 1850 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 6666F3E4 +P 7950 6100 +F 0 "#PWR1" H 7950 5850 50 0001 C CNN +F 1 "GND" H 7950 5950 50 0000 C CNN +F 2 "" H 7950 6100 50 0001 C CNN +F 3 "" H 7950 6100 50 0001 C CNN + 1 7950 6100 + 1 0 0 -1 +$EndComp +Connection ~ 7950 6100 +Wire Wire Line + 4000 5000 4000 5250 +Wire Wire Line + 4000 5250 5500 5250 +$Comp +L capacitor C1 +U 1 1 666705BB +P 6950 3850 +F 0 "C1" H 6975 3950 50 0000 L CNN +F 1 "5pF" H 6975 3750 50 0000 L CNN +F 2 "" H 6988 3700 30 0000 C CNN +F 3 "" H 6950 3850 60 0000 C CNN + 1 6950 3850 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM342/LM342.sub b/library/SubcircuitLibrary/LM342/LM342.sub new file mode 100644 index 00000000..470429b5 --- /dev/null +++ b/library/SubcircuitLibrary/LM342/LM342.sub @@ -0,0 +1,59 @@ +* Subcircuit LM342 +.subckt LM342 net-_j1-pad1_ net-_r13-pad1_ gnd +* c:\fossee\esim\library\subcircuitlibrary\lm342\lm342.cir +.include NPN.lib +.include PNP.lib +.include NJF.lib +j1 net-_j1-pad1_ gnd net-_j1-pad3_ J2N3819 +r1 net-_j1-pad1_ net-_q2-pad3_ 418 +q2 net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ Q2N2907A +q3 net-_q1-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q8 net-_q12-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q1 net-_q1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q4 net-_q1-pad1_ net-_q1-pad3_ net-_q4-pad3_ Q2N2222 +r2 net-_q4-pad3_ net-_q7-pad2_ 576 +r3 net-_q7-pad2_ net-_r3-pad2_ 3.41k +q7 net-_q7-pad1_ net-_q7-pad2_ net-_q4-pad3_ Q2N2907A +* u1 gnd net-_j1-pad3_ zener +* u2 gnd net-_q1-pad3_ zener +r4 net-_r3-pad2_ net-_q11-pad2_ 3.89k +r5 net-_q7-pad1_ gnd 7.8k +q9 net-_q12-pad3_ net-_q7-pad1_ gnd Q2N2222 +r6 net-_q10-pad2_ net-_r3-pad2_ 13k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q5 net-_q11-pad2_ net-_q11-pad2_ net-_q5-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q5-pad3_ gnd Q2N2222 +q11 net-_q10-pad3_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +r7 net-_q11-pad3_ gnd 2.84k +q12 gnd net-_c1-pad2_ net-_q12-pad3_ Q2N2907A +q13 net-_c1-pad2_ net-_c1-pad1_ net-_q10-pad3_ Q2N2222 +r8 net-_c1-pad2_ net-_q12-pad3_ 5.76k +q14 net-_q12-pad3_ net-_q14-pad2_ net-_q14-pad3_ Q2N2222 +r9 net-_r13-pad1_ net-_q14-pad3_ 100 +q15 net-_j1-pad1_ net-_q12-pad3_ net-_q10-pad1_ Q2N2222 +* u4 net-_q14-pad2_ net-_r10-pad1_ zener +r10 net-_r10-pad1_ net-_r10-pad2_ 5k +* u3 net-_r10-pad2_ net-_j1-pad1_ zener +q16 net-_j1-pad1_ net-_q10-pad1_ net-_q16-pad3_ Q2N2222 +r13 net-_r13-pad1_ net-_q10-pad1_ 2.5k +r15 net-_r13-pad1_ net-_q16-pad3_ 1.9 +r11 net-_q14-pad2_ net-_q16-pad3_ 100 +r16 net-_r12-pad2_ net-_r13-pad1_ 1.4k +r12 net-_c1-pad1_ net-_r12-pad2_ 15k +r14 net-_r12-pad2_ gnd 2.23k +c1 net-_c1-pad1_ net-_c1-pad2_ 5pf +a1 gnd net-_j1-pad3_ u1 +a2 gnd net-_q1-pad3_ u2 +a3 net-_q14-pad2_ net-_r10-pad1_ u4 +a4 net-_r10-pad2_ net-_j1-pad1_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM342
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM342/LM342_Previous_Values.xml b/library/SubcircuitLibrary/LM342/LM342_Previous_Values.xml new file mode 100644 index 00000000..94df9ec5 --- /dev/null +++ b/library/SubcircuitLibrary/LM342/LM342_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2><u4 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)" /><field12 name="Enter Breakdown Current (default=2.0e-2)" /><field13 name="Enter Saturation Current (default=1.0e-12)" /><field14 name="Enter Forward Emission Coefficient (default=1.0)" /><field15 name="Enter Switch for Limiting (default=FALSE)" /></u4><u3 name="type">zener<field16 name="Enter Breakdown Voltage (default=5.6)" /><field17 name="Enter Breakdown Current (default=2.0e-2)" /><field18 name="Enter Saturation Current (default=1.0e-12)" /><field19 name="Enter Forward Emission Coefficient (default=1.0)" /><field20 name="Enter Switch for Limiting (default=FALSE)" /></u3></model><devicemodel><j1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM342/NJF.lib b/library/SubcircuitLibrary/LM342/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/LM342/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM342/NPN.lib b/library/SubcircuitLibrary/LM342/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM342/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM342/PNP.lib b/library/SubcircuitLibrary/LM342/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM342/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM342/analysis b/library/SubcircuitLibrary/LM342/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM342/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC74HC238/3_and-cache.lib b/library/SubcircuitLibrary/MC74HC238/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC74HC238/3_and.cir b/library/SubcircuitLibrary/MC74HC238/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC74HC238/3_and.cir.out b/library/SubcircuitLibrary/MC74HC238/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC74HC238/3_and.pro b/library/SubcircuitLibrary/MC74HC238/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/MC74HC238/3_and.sch b/library/SubcircuitLibrary/MC74HC238/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC74HC238/3_and.sub b/library/SubcircuitLibrary/MC74HC238/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC74HC238/3_and_Previous_Values.xml b/library/SubcircuitLibrary/MC74HC238/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238-cache.lib b/library/SubcircuitLibrary/MC74HC238/MC74HC238-cache.lib new file mode 100644 index 00000000..c42bbd93 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238-cache.lib @@ -0,0 +1,110 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir b/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir new file mode 100644 index 00000000..0c204b7c --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir @@ -0,0 +1,61 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC74HC238\MC74HC238.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/24 07:37:01 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U37 Net-_U21-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad7_ d_and +U21 Net-_U18-Pad2_ Net-_U21-Pad2_ d_inverter +U22 Net-_U17-Pad3_ Net-_U22-Pad2_ d_inverter +U38 Net-_U23-Pad2_ Net-_U24-Pad2_ Net-_U1-Pad8_ d_and +U23 Net-_U19-Pad2_ Net-_U23-Pad2_ d_inverter +U24 Net-_U17-Pad3_ Net-_U24-Pad2_ d_inverter +U39 Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U1-Pad9_ d_and +U25 Net-_U20-Pad2_ Net-_U25-Pad2_ d_inverter +U26 Net-_U17-Pad3_ Net-_U26-Pad2_ d_inverter +U40 Net-_U27-Pad2_ Net-_U28-Pad2_ Net-_U1-Pad10_ d_and +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter +U28 Net-_U17-Pad3_ Net-_U28-Pad2_ d_inverter +U41 Net-_U29-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad11_ d_and +U29 Net-_U29-Pad1_ Net-_U29-Pad2_ d_inverter +U30 Net-_U17-Pad3_ Net-_U30-Pad2_ d_inverter +U42 Net-_U31-Pad2_ Net-_U32-Pad2_ Net-_U1-Pad12_ d_and +U31 Net-_U31-Pad1_ Net-_U31-Pad2_ d_inverter +U32 Net-_U17-Pad3_ Net-_U32-Pad2_ d_inverter +U43 Net-_U33-Pad2_ Net-_U34-Pad2_ Net-_U1-Pad13_ d_and +U33 Net-_U33-Pad1_ Net-_U33-Pad2_ d_inverter +U34 Net-_U17-Pad3_ Net-_U34-Pad2_ d_inverter +U44 Net-_U35-Pad2_ Net-_U36-Pad2_ Net-_U1-Pad14_ d_and +U35 Net-_U35-Pad1_ Net-_U35-Pad2_ d_inverter +U36 Net-_U17-Pad3_ Net-_U36-Pad2_ d_inverter +U10 Net-_U1-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U1-Pad2_ Net-_U11-Pad2_ d_inverter +U12 Net-_U1-Pad3_ Net-_U12-Pad2_ d_inverter +U14 Net-_U10-Pad2_ Net-_U14-Pad2_ d_inverter +U15 Net-_U11-Pad2_ Net-_U15-Pad2_ d_inverter +U16 Net-_U12-Pad2_ Net-_U16-Pad2_ d_inverter +U17 Net-_U13-Pad3_ Net-_U1-Pad6_ Net-_U17-Pad3_ d_nand +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U8 Net-_U1-Pad4_ Net-_U13-Pad1_ d_inverter +U9 Net-_U1-Pad5_ Net-_U13-Pad2_ d_inverter +X1 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U18-Pad1_ 3_and +X2 Net-_U14-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U19-Pad1_ 3_and +X3 Net-_U10-Pad2_ Net-_U15-Pad2_ Net-_U12-Pad2_ Net-_U20-Pad1_ 3_and +X4 Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U12-Pad2_ Net-_U54-Pad1_ 3_and +X5 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U16-Pad2_ Net-_U55-Pad1_ 3_and +X6 Net-_U11-Pad2_ Net-_U16-Pad2_ Net-_U10-Pad2_ Net-_U56-Pad1_ 3_and +X8 Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U58-Pad1_ 3_and +X7 Net-_U10-Pad2_ Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U57-Pad1_ 3_and +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter +U54 Net-_U54-Pad1_ Net-_U27-Pad1_ d_inverter +U55 Net-_U55-Pad1_ Net-_U29-Pad1_ d_inverter +U56 Net-_U56-Pad1_ Net-_U31-Pad1_ d_inverter +U57 Net-_U57-Pad1_ Net-_U33-Pad1_ d_inverter +U58 Net-_U58-Pad1_ Net-_U35-Pad1_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir.out b/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir.out new file mode 100644 index 00000000..ed1f4eaf --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir.out @@ -0,0 +1,189 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc74hc238\mc74hc238.cir + +.include 3_and.sub +* u37 net-_u21-pad2_ net-_u22-pad2_ net-_u1-pad7_ d_and +* u21 net-_u18-pad2_ net-_u21-pad2_ d_inverter +* u22 net-_u17-pad3_ net-_u22-pad2_ d_inverter +* u38 net-_u23-pad2_ net-_u24-pad2_ net-_u1-pad8_ d_and +* u23 net-_u19-pad2_ net-_u23-pad2_ d_inverter +* u24 net-_u17-pad3_ net-_u24-pad2_ d_inverter +* u39 net-_u25-pad2_ net-_u26-pad2_ net-_u1-pad9_ d_and +* u25 net-_u20-pad2_ net-_u25-pad2_ d_inverter +* u26 net-_u17-pad3_ net-_u26-pad2_ d_inverter +* u40 net-_u27-pad2_ net-_u28-pad2_ net-_u1-pad10_ d_and +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u17-pad3_ net-_u28-pad2_ d_inverter +* u41 net-_u29-pad2_ net-_u30-pad2_ net-_u1-pad11_ d_and +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u30 net-_u17-pad3_ net-_u30-pad2_ d_inverter +* u42 net-_u31-pad2_ net-_u32-pad2_ net-_u1-pad12_ d_and +* u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter +* u32 net-_u17-pad3_ net-_u32-pad2_ d_inverter +* u43 net-_u33-pad2_ net-_u34-pad2_ net-_u1-pad13_ d_and +* u33 net-_u33-pad1_ net-_u33-pad2_ d_inverter +* u34 net-_u17-pad3_ net-_u34-pad2_ d_inverter +* u44 net-_u35-pad2_ net-_u36-pad2_ net-_u1-pad14_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u36 net-_u17-pad3_ net-_u36-pad2_ d_inverter +* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad2_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter +* u14 net-_u10-pad2_ net-_u14-pad2_ d_inverter +* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u16 net-_u12-pad2_ net-_u16-pad2_ d_inverter +* u17 net-_u13-pad3_ net-_u1-pad6_ net-_u17-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u8 net-_u1-pad4_ net-_u13-pad1_ d_inverter +* u9 net-_u1-pad5_ net-_u13-pad2_ d_inverter +x1 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u18-pad1_ 3_and +x2 net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u19-pad1_ 3_and +x3 net-_u10-pad2_ net-_u15-pad2_ net-_u12-pad2_ net-_u20-pad1_ 3_and +x4 net-_u14-pad2_ net-_u15-pad2_ net-_u12-pad2_ net-_u54-pad1_ 3_and +x5 net-_u10-pad2_ net-_u11-pad2_ net-_u16-pad2_ net-_u55-pad1_ 3_and +x6 net-_u11-pad2_ net-_u16-pad2_ net-_u10-pad2_ net-_u56-pad1_ 3_and +x8 net-_u14-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u58-pad1_ 3_and +x7 net-_u10-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u57-pad1_ 3_and +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u54 net-_u54-pad1_ net-_u27-pad1_ d_inverter +* u55 net-_u55-pad1_ net-_u29-pad1_ d_inverter +* u56 net-_u56-pad1_ net-_u31-pad1_ d_inverter +* u57 net-_u57-pad1_ net-_u33-pad1_ d_inverter +* u58 net-_u58-pad1_ net-_u35-pad1_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u21-pad2_ net-_u22-pad2_ ] net-_u1-pad7_ u37 +a2 net-_u18-pad2_ net-_u21-pad2_ u21 +a3 net-_u17-pad3_ net-_u22-pad2_ u22 +a4 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u1-pad8_ u38 +a5 net-_u19-pad2_ net-_u23-pad2_ u23 +a6 net-_u17-pad3_ net-_u24-pad2_ u24 +a7 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u1-pad9_ u39 +a8 net-_u20-pad2_ net-_u25-pad2_ u25 +a9 net-_u17-pad3_ net-_u26-pad2_ u26 +a10 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u1-pad10_ u40 +a11 net-_u27-pad1_ net-_u27-pad2_ u27 +a12 net-_u17-pad3_ net-_u28-pad2_ u28 +a13 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u1-pad11_ u41 +a14 net-_u29-pad1_ net-_u29-pad2_ u29 +a15 net-_u17-pad3_ net-_u30-pad2_ u30 +a16 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u1-pad12_ u42 +a17 net-_u31-pad1_ net-_u31-pad2_ u31 +a18 net-_u17-pad3_ net-_u32-pad2_ u32 +a19 [net-_u33-pad2_ net-_u34-pad2_ ] net-_u1-pad13_ u43 +a20 net-_u33-pad1_ net-_u33-pad2_ u33 +a21 net-_u17-pad3_ net-_u34-pad2_ u34 +a22 [net-_u35-pad2_ net-_u36-pad2_ ] net-_u1-pad14_ u44 +a23 net-_u35-pad1_ net-_u35-pad2_ u35 +a24 net-_u17-pad3_ net-_u36-pad2_ u36 +a25 net-_u1-pad1_ net-_u10-pad2_ u10 +a26 net-_u1-pad2_ net-_u11-pad2_ u11 +a27 net-_u1-pad3_ net-_u12-pad2_ u12 +a28 net-_u10-pad2_ net-_u14-pad2_ u14 +a29 net-_u11-pad2_ net-_u15-pad2_ u15 +a30 net-_u12-pad2_ net-_u16-pad2_ u16 +a31 [net-_u13-pad3_ net-_u1-pad6_ ] net-_u17-pad3_ u17 +a32 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a33 net-_u1-pad4_ net-_u13-pad1_ u8 +a34 net-_u1-pad5_ net-_u13-pad2_ u9 +a35 net-_u18-pad1_ net-_u18-pad2_ u18 +a36 net-_u19-pad1_ net-_u19-pad2_ u19 +a37 net-_u20-pad1_ net-_u20-pad2_ u20 +a38 net-_u54-pad1_ net-_u27-pad1_ u54 +a39 net-_u55-pad1_ net-_u29-pad1_ u55 +a40 net-_u56-pad1_ net-_u31-pad1_ u56 +a41 net-_u57-pad1_ net-_u33-pad1_ u57 +a42 net-_u58-pad1_ net-_u35-pad1_ u58 +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-03 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.pro b/library/SubcircuitLibrary/MC74HC238/MC74HC238.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.proj b/library/SubcircuitLibrary/MC74HC238/MC74HC238.proj new file mode 100644 index 00000000..41b4387c --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.proj @@ -0,0 +1 @@ +schematicFile 74238.sch diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.sch b/library/SubcircuitLibrary/MC74HC238/MC74HC238.sch new file mode 100644 index 00000000..57020d36 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.sch @@ -0,0 +1,1048 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MC74HC238-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U37 +U 1 1 665E55B4 +P 10500 4450 +F 0 "U37" H 10500 4450 60 0000 C CNN +F 1 "d_and" H 10550 4550 60 0000 C CNN +F 2 "" H 10500 4450 60 0000 C CNN +F 3 "" H 10500 4450 60 0000 C CNN + 1 10500 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 665E560E +P 9750 4350 +F 0 "U21" H 9750 4250 60 0000 C CNN +F 1 "d_inverter" H 9750 4500 60 0000 C CNN +F 2 "" H 9800 4300 60 0000 C CNN +F 3 "" H 9800 4300 60 0000 C CNN + 1 9750 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 665E5671 +P 9750 4450 +F 0 "U22" H 9750 4350 60 0000 C CNN +F 1 "d_inverter" H 9750 4600 60 0000 C CNN +F 2 "" H 9800 4400 60 0000 C CNN +F 3 "" H 9800 4400 60 0000 C CNN + 1 9750 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U38 +U 1 1 665E5826 +P 10500 4900 +F 0 "U38" H 10500 4900 60 0000 C CNN +F 1 "d_and" H 10550 5000 60 0000 C CNN +F 2 "" H 10500 4900 60 0000 C CNN +F 3 "" H 10500 4900 60 0000 C CNN + 1 10500 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 665E5832 +P 9750 4800 +F 0 "U23" H 9750 4700 60 0000 C CNN +F 1 "d_inverter" H 9750 4950 60 0000 C CNN +F 2 "" H 9800 4750 60 0000 C CNN +F 3 "" H 9800 4750 60 0000 C CNN + 1 9750 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 665E5838 +P 9750 4900 +F 0 "U24" H 9750 4800 60 0000 C CNN +F 1 "d_inverter" H 9750 5050 60 0000 C CNN +F 2 "" H 9800 4850 60 0000 C CNN +F 3 "" H 9800 4850 60 0000 C CNN + 1 9750 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U39 +U 1 1 665E592A +P 10500 5300 +F 0 "U39" H 10500 5300 60 0000 C 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"" H 9800 5600 60 0000 C CNN +F 3 "" H 9800 5600 60 0000 C CNN + 1 9750 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U28 +U 1 1 665E5956 +P 9750 5750 +F 0 "U28" H 9750 5650 60 0000 C CNN +F 1 "d_inverter" H 9750 5900 60 0000 C CNN +F 2 "" H 9800 5700 60 0000 C CNN +F 3 "" H 9800 5700 60 0000 C CNN + 1 9750 5750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U41 +U 1 1 665E600B +P 10500 6200 +F 0 "U41" H 10500 6200 60 0000 C CNN +F 1 "d_and" H 10550 6300 60 0000 C CNN +F 2 "" H 10500 6200 60 0000 C CNN +F 3 "" H 10500 6200 60 0000 C CNN + 1 10500 6200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 665E6017 +P 9750 6100 +F 0 "U29" H 9750 6000 60 0000 C CNN +F 1 "d_inverter" H 9750 6250 60 0000 C CNN +F 2 "" H 9800 6050 60 0000 C CNN +F 3 "" H 9800 6050 60 0000 C CNN + 1 9750 6100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 665E601D +P 9750 6200 +F 0 "U30" H 9750 6100 60 0000 C CNN +F 1 "d_inverter" H 9750 6350 60 0000 C CNN +F 2 "" H 9800 6150 60 0000 C CNN +F 3 "" H 9800 6150 60 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Line + 4050 6000 4050 7000 +Wire Wire Line + 3750 6100 3950 6100 +Wire Wire Line + 3950 6100 3950 7100 +Wire Wire Line + 3950 7100 4050 7100 +Wire Wire Line + 3750 6200 3750 7700 +$Comp +L 3_and X1 +U 1 1 665F8A1D +P 6950 4400 +F 0 "X1" H 7050 4350 60 0000 C CNN +F 1 "3_and" H 7100 4550 60 0000 C CNN +F 2 "" H 6950 4400 60 0000 C CNN +F 3 "" H 6950 4400 60 0000 C CNN + 1 6950 4400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 665F8B11 +P 6950 4850 +F 0 "X2" H 7050 4800 60 0000 C CNN +F 1 "3_and" H 7100 5000 60 0000 C CNN +F 2 "" H 6950 4850 60 0000 C CNN +F 3 "" H 6950 4850 60 0000 C CNN + 1 6950 4850 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 665F8C03 +P 6950 5250 +F 0 "X3" H 7050 5200 60 0000 C CNN +F 1 "3_and" H 7100 5400 60 0000 C CNN +F 2 "" H 6950 5250 60 0000 C CNN +F 3 "" H 6950 5250 60 0000 C CNN + 1 6950 5250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 665F8CE8 +P 6950 5700 +F 0 "X4" H 7050 5650 60 0000 C CNN +F 1 "3_and" H 7100 5850 60 0000 C CNN +F 2 "" H 6950 5700 60 0000 C CNN +F 3 "" H 6950 5700 60 0000 C CNN + 1 6950 5700 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 665F8DD2 +P 7000 6200 +F 0 "X5" H 7100 6150 60 0000 C CNN +F 1 "3_and" H 7150 6350 60 0000 C CNN +F 2 "" H 7000 6200 60 0000 C CNN +F 3 "" H 7000 6200 60 0000 C CNN + 1 7000 6200 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 665F8EBF +P 7000 6750 +F 0 "X6" H 7100 6700 60 0000 C CNN +F 1 "3_and" H 7150 6900 60 0000 C CNN +F 2 "" H 7000 6750 60 0000 C CNN +F 3 "" H 7000 6750 60 0000 C CNN + 1 7000 6750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X8 +U 1 1 665F8FB5 +P 7000 7450 +F 0 "X8" H 7100 7400 60 0000 C CNN +F 1 "3_and" H 7150 7600 60 0000 C CNN +F 2 "" H 7000 7450 60 0000 C CNN +F 3 "" H 7000 7450 60 0000 C CNN + 1 7000 7450 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X7 +U 1 1 665F9294 +P 7000 7100 +F 0 "X7" H 7100 7050 60 0000 C CNN +F 1 "3_and" H 7150 7250 60 0000 C CNN +F 2 "" H 7000 7100 60 0000 C CNN +F 3 "" H 7000 7100 60 0000 C CNN + 1 7000 7100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 6950 6650 6950 +Connection ~ 6100 6800 +Wire Wire Line + 6650 7500 6500 7500 +Wire Wire Line + 6500 7500 6500 7550 +Wire Wire Line + 6650 7300 6500 7300 +Wire Wire Line + 6500 7300 6500 7250 +Wire Wire Line + 6650 7150 6500 7150 +Wire Wire Line + 6500 7150 6500 7100 +Wire Wire Line + 6600 6550 6650 6600 +Wire Wire Line + 6650 6050 6500 6000 +Wire Wire Line + 6500 6000 6500 5950 +Wire Wire Line + 6600 5350 6600 5300 +Wire Wire Line + 6600 5100 6500 5100 +Wire Wire Line + 6500 5100 6500 5050 +Wire Wire Line + 6600 5500 6600 5550 +Wire Wire Line + 6600 5750 6500 5750 +Wire Wire Line + 6500 5750 6500 5800 +Wire Wire Line + 6600 4950 6600 4900 +Wire Wire Line + 6600 4650 6600 4700 +Wire Wire Line + 6600 4250 6500 4250 +Wire Wire Line + 6500 4250 6500 4200 +Wire Wire Line + 6600 4500 6600 4450 +$Comp +L d_inverter U18 +U 1 1 665FCEB3 +P 7750 4350 +F 0 "U18" H 7750 4250 60 0000 C CNN +F 1 "d_inverter" H 7750 4500 60 0000 C CNN +F 2 "" H 7800 4300 60 0000 C CNN +F 3 "" H 7800 4300 60 0000 C CNN + 1 7750 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 665FCFCA +P 7750 4800 +F 0 "U19" H 7750 4700 60 0000 C CNN +F 1 "d_inverter" H 7750 4950 60 0000 C CNN +F 2 "" H 7800 4750 60 0000 C CNN +F 3 "" H 7800 4750 60 0000 C CNN + 1 7750 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 665FD0B4 +P 7750 5200 +F 0 "U20" H 7750 5100 60 0000 C CNN +F 1 "d_inverter" H 7750 5350 60 0000 C CNN +F 2 "" H 7800 5150 60 0000 C CNN +F 3 "" H 7800 5150 60 0000 C CNN + 1 7750 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U54 +U 1 1 665FD199 +P 7750 5650 +F 0 "U54" H 7750 5550 60 0000 C CNN +F 1 "d_inverter" H 7750 5800 60 0000 C CNN +F 2 "" H 7800 5600 60 0000 C CNN +F 3 "" H 7800 5600 60 0000 C CNN + 1 7750 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U55 +U 1 1 665FD283 +P 7800 6150 +F 0 "U55" H 7800 6050 60 0000 C CNN +F 1 "d_inverter" H 7800 6300 60 0000 C CNN +F 2 "" H 7850 6100 60 0000 C CNN +F 3 "" H 7850 6100 60 0000 C CNN + 1 7800 6150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U56 +U 1 1 665FD370 +P 7800 6700 +F 0 "U56" H 7800 6600 60 0000 C CNN +F 1 "d_inverter" H 7800 6850 60 0000 C CNN +F 2 "" H 7850 6650 60 0000 C CNN +F 3 "" H 7850 6650 60 0000 C CNN + 1 7800 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U57 +U 1 1 665FD46A +P 7800 7050 +F 0 "U57" H 7800 6950 60 0000 C CNN +F 1 "d_inverter" H 7800 7200 60 0000 C CNN +F 2 "" H 7850 7000 60 0000 C CNN +F 3 "" H 7850 7000 60 0000 C CNN + 1 7800 7050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U58 +U 1 1 665FD55F +P 7800 7400 +F 0 "U58" H 7800 7300 60 0000 C CNN +F 1 "d_inverter" H 7800 7550 60 0000 C CNN +F 2 "" H 7850 7350 60 0000 C CNN +F 3 "" H 7850 7350 60 0000 C CNN + 1 7800 7400 + 1 0 0 -1 +$EndComp +Connection ~ 9100 7500 +Connection ~ 8050 4800 +Wire Wire Line + 8100 6150 9250 6150 +Wire Wire Line + 9250 6150 9250 6100 +Wire Wire Line + 8100 6550 8100 6700 +Wire Wire Line + 8100 7050 8700 7050 +Wire Wire Line + 8700 7050 8700 6950 +$Comp +L PORT U1 +U 1 1 665E7D1A +P 3500 5700 +F 0 "U1" H 3550 5800 30 0000 C CNN +F 1 "PORT" H 3500 5700 30 0000 C CNN +F 2 "" H 3500 5700 60 0000 C CNN +F 3 "" H 3500 5700 60 0000 C CNN + 1 3500 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 665E7DB1 +P 3500 5800 +F 0 "U1" H 3550 5900 30 0000 C CNN +F 1 "PORT" H 3500 5800 30 0000 C CNN +F 2 "" H 3500 5800 60 0000 C CNN +F 3 "" H 3500 5800 60 0000 C CNN + 2 3500 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 665E82C7 +P 3500 5900 +F 0 "U1" H 3550 6000 30 0000 C CNN +F 1 "PORT" H 3500 5900 30 0000 C CNN +F 2 "" H 3500 5900 60 0000 C CNN +F 3 "" H 3500 5900 60 0000 C CNN + 3 3500 5900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 665E835A +P 3500 6000 +F 0 "U1" H 3550 6100 30 0000 C CNN +F 1 "PORT" H 3500 6000 30 0000 C CNN +F 2 "" H 3500 6000 60 0000 C CNN +F 3 "" H 3500 6000 60 0000 C CNN + 4 3500 6000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 665E83ED +P 3500 6100 +F 0 "U1" H 3550 6200 30 0000 C CNN +F 1 "PORT" H 3500 6100 30 0000 C CNN +F 2 "" H 3500 6100 60 0000 C CNN +F 3 "" H 3500 6100 60 0000 C CNN + 5 3500 6100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 665E8482 +P 3500 6200 +F 0 "U1" H 3550 6300 30 0000 C CNN +F 1 "PORT" H 3500 6200 30 0000 C CNN +F 2 "" H 3500 6200 60 0000 C CNN +F 3 "" H 3500 6200 60 0000 C CNN + 6 3500 6200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 665E8A36 +P 11400 5500 +F 0 "U1" H 11450 5600 30 0000 C CNN +F 1 "PORT" H 11400 5500 30 0000 C CNN +F 2 "" H 11400 5500 60 0000 C CNN +F 3 "" H 11400 5500 60 0000 C CNN + 7 11400 5500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 665E8AC5 +P 11400 5600 +F 0 "U1" H 11450 5700 30 0000 C CNN +F 1 "PORT" H 11400 5600 30 0000 C CNN +F 2 "" H 11400 5600 60 0000 C CNN +F 3 "" H 11400 5600 60 0000 C CNN + 8 11400 5600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 665E8B52 +P 11400 5700 +F 0 "U1" H 11450 5800 30 0000 C CNN +F 1 "PORT" H 11400 5700 30 0000 C CNN +F 2 "" H 11400 5700 60 0000 C CNN +F 3 "" H 11400 5700 60 0000 C CNN + 9 11400 5700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 665E8BE1 +P 11400 5800 +F 0 "U1" H 11450 5900 30 0000 C CNN +F 1 "PORT" H 11400 5800 30 0000 C CNN +F 2 "" H 11400 5800 60 0000 C CNN +F 3 "" H 11400 5800 60 0000 C CNN + 10 11400 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 665E8C72 +P 11400 5900 +F 0 "U1" H 11450 6000 30 0000 C CNN +F 1 "PORT" H 11400 5900 30 0000 C CNN +F 2 "" H 11400 5900 60 0000 C CNN +F 3 "" H 11400 5900 60 0000 C CNN + 11 11400 5900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 665E8D05 +P 11400 6000 +F 0 "U1" H 11450 6100 30 0000 C CNN +F 1 "PORT" H 11400 6000 30 0000 C CNN +F 2 "" H 11400 6000 60 0000 C CNN +F 3 "" H 11400 6000 60 0000 C CNN + 12 11400 6000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 665E8D9A +P 11400 6100 +F 0 "U1" H 11450 6200 30 0000 C CNN +F 1 "PORT" H 11400 6100 30 0000 C CNN +F 2 "" H 11400 6100 60 0000 C CNN +F 3 "" H 11400 6100 60 0000 C CNN + 13 11400 6100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 665E8E31 +P 11400 6200 +F 0 "U1" H 11450 6300 30 0000 C CNN +F 1 "PORT" H 11400 6200 30 0000 C CNN +F 2 "" H 11400 6200 60 0000 C CNN +F 3 "" H 11400 6200 60 0000 C CNN + 14 11400 6200 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.sub b/library/SubcircuitLibrary/MC74HC238/MC74HC238.sub new file mode 100644 index 00000000..b5c0662e --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.sub @@ -0,0 +1,183 @@ +* Subcircuit MC74HC238 +.subckt MC74HC238 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\mc74hc238\mc74hc238.cir +.include 3_and.sub +* u37 net-_u21-pad2_ net-_u22-pad2_ net-_u1-pad7_ d_and +* u21 net-_u18-pad2_ net-_u21-pad2_ d_inverter +* u22 net-_u17-pad3_ net-_u22-pad2_ d_inverter +* u38 net-_u23-pad2_ net-_u24-pad2_ net-_u1-pad8_ d_and +* u23 net-_u19-pad2_ net-_u23-pad2_ d_inverter +* u24 net-_u17-pad3_ net-_u24-pad2_ d_inverter +* u39 net-_u25-pad2_ net-_u26-pad2_ net-_u1-pad9_ d_and +* u25 net-_u20-pad2_ net-_u25-pad2_ d_inverter +* u26 net-_u17-pad3_ net-_u26-pad2_ d_inverter +* u40 net-_u27-pad2_ net-_u28-pad2_ net-_u1-pad10_ d_and +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u17-pad3_ net-_u28-pad2_ d_inverter +* u41 net-_u29-pad2_ net-_u30-pad2_ net-_u1-pad11_ d_and +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u30 net-_u17-pad3_ net-_u30-pad2_ d_inverter +* u42 net-_u31-pad2_ net-_u32-pad2_ net-_u1-pad12_ d_and +* u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter +* u32 net-_u17-pad3_ net-_u32-pad2_ d_inverter +* u43 net-_u33-pad2_ net-_u34-pad2_ net-_u1-pad13_ d_and +* u33 net-_u33-pad1_ net-_u33-pad2_ d_inverter +* u34 net-_u17-pad3_ net-_u34-pad2_ d_inverter +* u44 net-_u35-pad2_ net-_u36-pad2_ net-_u1-pad14_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u36 net-_u17-pad3_ net-_u36-pad2_ d_inverter +* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad2_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter +* u14 net-_u10-pad2_ net-_u14-pad2_ d_inverter +* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u16 net-_u12-pad2_ net-_u16-pad2_ d_inverter +* u17 net-_u13-pad3_ net-_u1-pad6_ net-_u17-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u8 net-_u1-pad4_ net-_u13-pad1_ d_inverter +* u9 net-_u1-pad5_ net-_u13-pad2_ d_inverter +x1 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u18-pad1_ 3_and +x2 net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u19-pad1_ 3_and +x3 net-_u10-pad2_ net-_u15-pad2_ net-_u12-pad2_ net-_u20-pad1_ 3_and +x4 net-_u14-pad2_ net-_u15-pad2_ net-_u12-pad2_ net-_u54-pad1_ 3_and +x5 net-_u10-pad2_ net-_u11-pad2_ net-_u16-pad2_ net-_u55-pad1_ 3_and +x6 net-_u11-pad2_ net-_u16-pad2_ net-_u10-pad2_ net-_u56-pad1_ 3_and +x8 net-_u14-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u58-pad1_ 3_and +x7 net-_u10-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u57-pad1_ 3_and +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u54 net-_u54-pad1_ net-_u27-pad1_ d_inverter +* u55 net-_u55-pad1_ net-_u29-pad1_ d_inverter +* u56 net-_u56-pad1_ net-_u31-pad1_ d_inverter +* u57 net-_u57-pad1_ net-_u33-pad1_ d_inverter +* u58 net-_u58-pad1_ net-_u35-pad1_ d_inverter +a1 [net-_u21-pad2_ net-_u22-pad2_ ] net-_u1-pad7_ u37 +a2 net-_u18-pad2_ net-_u21-pad2_ u21 +a3 net-_u17-pad3_ net-_u22-pad2_ u22 +a4 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u1-pad8_ u38 +a5 net-_u19-pad2_ net-_u23-pad2_ u23 +a6 net-_u17-pad3_ net-_u24-pad2_ u24 +a7 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u1-pad9_ u39 +a8 net-_u20-pad2_ net-_u25-pad2_ u25 +a9 net-_u17-pad3_ net-_u26-pad2_ u26 +a10 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u1-pad10_ u40 +a11 net-_u27-pad1_ net-_u27-pad2_ u27 +a12 net-_u17-pad3_ net-_u28-pad2_ u28 +a13 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u1-pad11_ u41 +a14 net-_u29-pad1_ net-_u29-pad2_ u29 +a15 net-_u17-pad3_ net-_u30-pad2_ u30 +a16 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u1-pad12_ u42 +a17 net-_u31-pad1_ net-_u31-pad2_ u31 +a18 net-_u17-pad3_ net-_u32-pad2_ u32 +a19 [net-_u33-pad2_ net-_u34-pad2_ ] net-_u1-pad13_ u43 +a20 net-_u33-pad1_ net-_u33-pad2_ u33 +a21 net-_u17-pad3_ net-_u34-pad2_ u34 +a22 [net-_u35-pad2_ net-_u36-pad2_ ] net-_u1-pad14_ u44 +a23 net-_u35-pad1_ net-_u35-pad2_ u35 +a24 net-_u17-pad3_ net-_u36-pad2_ u36 +a25 net-_u1-pad1_ net-_u10-pad2_ u10 +a26 net-_u1-pad2_ net-_u11-pad2_ u11 +a27 net-_u1-pad3_ net-_u12-pad2_ u12 +a28 net-_u10-pad2_ net-_u14-pad2_ u14 +a29 net-_u11-pad2_ net-_u15-pad2_ u15 +a30 net-_u12-pad2_ net-_u16-pad2_ u16 +a31 [net-_u13-pad3_ net-_u1-pad6_ ] net-_u17-pad3_ u17 +a32 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a33 net-_u1-pad4_ net-_u13-pad1_ u8 +a34 net-_u1-pad5_ net-_u13-pad2_ u9 +a35 net-_u18-pad1_ net-_u18-pad2_ u18 +a36 net-_u19-pad1_ net-_u19-pad2_ u19 +a37 net-_u20-pad1_ net-_u20-pad2_ u20 +a38 net-_u54-pad1_ net-_u27-pad1_ u54 +a39 net-_u55-pad1_ net-_u29-pad1_ u55 +a40 net-_u56-pad1_ net-_u31-pad1_ u56 +a41 net-_u57-pad1_ net-_u33-pad1_ u57 +a42 net-_u58-pad1_ net-_u35-pad1_ u58 +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends MC74HC238
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238_Previous_Values.xml b/library/SubcircuitLibrary/MC74HC238/MC74HC238_Previous_Values.xml new file mode 100644 index 00000000..c73b3abe --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v6 name="Source type">dc<field1 name="Value">5</field1></v6></source><model><u37 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u37><u21 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u22><u38 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u38><u23 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u24><u39 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u39><u25 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u26><u40 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u40><u27 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u28><u41 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u41><u29 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u30><u42 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u42><u31 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u32><u43 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u43><u33 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u33><u34 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u34><u44 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u44><u35 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u35><u36 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u36><u10 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u12><u14 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_nand<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_and<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u13><u8 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u9><u45 name="type">dac_bridge<field103 name="Enter value for out_low (default=0.0)" /><field104 name="Enter value for out_high (default=5.0)" /><field105 name="Enter value for out_undef (default=0.5)" /><field106 name="Enter value for input load (default=1.0e-12)" /><field107 name="Enter the Rise Time (default=1.0e-9)" /><field108 name="Enter the Fall Time (default=1.0e-9)" /></u45><u7 name="type">adc_bridge<field109 name="Enter value for in_low (default=1.0)" /><field110 name="Enter value for in_high (default=2.0)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /><field112 name="Enter Fall Delay (default=1.0e-9)" /></u7><u18 name="type">d_inverter<field113 name="Enter Rise Delay (default=1.0e-9)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /><field115 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_inverter<field116 name="Enter Rise Delay (default=1.0e-9)" /><field117 name="Enter Fall Delay (default=1.0e-9)" /><field118 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_inverter<field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /><field121 name="Enter Input Load (default=1.0e-12)" /></u20><u54 name="type">d_inverter<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u54><u55 name="type">d_inverter<field125 name="Enter Rise Delay (default=1.0e-9)" /><field126 name="Enter Fall Delay (default=1.0e-9)" /><field127 name="Enter Input Load (default=1.0e-12)" /></u55><u56 name="type">d_inverter<field128 name="Enter Rise Delay (default=1.0e-9)" /><field129 name="Enter Fall Delay (default=1.0e-9)" /><field130 name="Enter Input Load (default=1.0e-12)" /></u56><u57 name="type">d_inverter<field131 name="Enter Rise Delay (default=1.0e-9)" /><field132 name="Enter Fall Delay (default=1.0e-9)" /><field133 name="Enter Input Load (default=1.0e-12)" /></u57><u58 name="type">d_inverter<field134 name="Enter Rise Delay (default=1.0e-9)" /><field135 name="Enter Fall Delay (default=1.0e-9)" /><field136 name="Enter Input Load (default=1.0e-12)" /></u58></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC74HC238/analysis b/library/SubcircuitLibrary/MC74HC238/analysis new file mode 100644 index 00000000..cf94dd7f --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and-cache.lib b/library/SubcircuitLibrary/SN74ALS280/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.cir b/library/SubcircuitLibrary/SN74ALS280/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.cir.out b/library/SubcircuitLibrary/SN74ALS280/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.pro b/library/SubcircuitLibrary/SN74ALS280/3_and.pro new file mode 100644 index 00000000..06813ca7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.sch b/library/SubcircuitLibrary/SN74ALS280/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.sub b/library/SubcircuitLibrary/SN74ALS280/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS280/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR-cache.lib b/library/SubcircuitLibrary/SN74ALS280/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.cir b/library/SubcircuitLibrary/SN74ALS280/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.cir.out b/library/SubcircuitLibrary/SN74ALS280/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.pro b/library/SubcircuitLibrary/SN74ALS280/4_OR.pro new file mode 100644 index 00000000..881563eb --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.sch b/library/SubcircuitLibrary/SN74ALS280/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.sub b/library/SubcircuitLibrary/SN74ALS280/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS280/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and-cache.lib b/library/SubcircuitLibrary/SN74ALS280/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and-rescue.lib b/library/SubcircuitLibrary/SN74ALS280/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.cir b/library/SubcircuitLibrary/SN74ALS280/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.cir.out b/library/SubcircuitLibrary/SN74ALS280/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.pro b/library/SubcircuitLibrary/SN74ALS280/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.sch b/library/SubcircuitLibrary/SN74ALS280/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.sub b/library/SubcircuitLibrary/SN74ALS280/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS280/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS-cache.lib b/library/SubcircuitLibrary/SN74ALS280/INVCMOS-cache.lib new file mode 100644 index 00000000..cc25b0c9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir.out b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir.out new file mode 100644 index 00000000..cb2b6641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir.out @@ -0,0 +1,18 @@ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u1 net-_m1-pad2_ net-_c1-pad1_ port +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +.tran 0e-03 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS.pro b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.pro new file mode 100644 index 00000000..81bd9ad4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.pro @@ -0,0 +1,70 @@ +update=Sun Aug 25 15:54:56 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Subckt +LibName23=transistors +LibName24=conn +LibName25=eSim_Plot +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User + diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sch b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sch new file mode 100644 index 00000000..13a7fc09 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:INVCMOS-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 4000 5900 4150 +Connection ~ 5800 2450 +Connection ~ 5800 4150 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5050 3350 +Wire Wire Line + 4000 3350 5050 3350 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 4200 3350 +$Comp +L PORT U1 +U 1 1 5D6263BC +P 3750 3350 +F 0 "U1" H 3800 3450 30 0000 C CNN +F 1 "PORT" H 3750 3350 30 0000 C CNN +F 2 "" H 3750 3350 60 0000 C CNN +F 3 "" H 3750 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3250 5800 3250 +Connection ~ 5800 3250 +Wire Wire Line + 5800 4050 5800 4550 +$Comp +L eSim_MOS_N M1 +U 1 1 5D6265DB +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 5D626659 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2850 6050 2850 +Wire Wire Line + 6050 2850 6050 2450 +Wire Wire Line + 6050 2450 5800 2450 +Connection ~ 6000 3250 +Connection ~ 5800 4300 +$Comp +L GND #PWR1 +U 1 1 5D626C59 +P 5800 4550 +F 0 "#PWR1" H 5800 4300 50 0001 C CNN +F 1 "GND" H 5800 4400 50 0000 C CNN +F 2 "" H 5800 4550 50 0001 C CNN +F 3 "" H 5800 4550 50 0001 C CNN + 1 5800 4550 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5D626C7F +P 6250 2300 +F 0 "v1" H 6050 2400 60 0000 C CNN +F 1 "5" H 6050 2250 60 0000 C CNN +F 2 "R1" H 5950 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 1 6250 2300 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR2 +U 1 1 5D626CF6 +P 6850 2300 +F 0 "#PWR2" H 6850 2050 50 0001 C CNN +F 1 "GND" H 6850 2150 50 0000 C CNN +F 2 "" H 6850 2300 50 0001 C CNN +F 3 "" H 6850 2300 50 0001 C CNN + 1 6850 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 2300 6700 2300 +$Comp +L PORT U1 +U 2 1 5D626DCB +P 6300 3250 +F 0 "U1" H 6350 3350 30 0000 C CNN +F 1 "PORT" H 6300 3250 30 0000 C CNN +F 2 "" H 6300 3250 60 0000 C CNN +F 3 "" H 6300 3250 60 0000 C CNN + 2 6300 3250 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D62796C +P 6050 3850 +F 0 "C1" H 6075 3950 50 0000 L CNN +F 1 "1u" H 6075 3750 50 0000 L CNN +F 2 "" H 6088 3700 30 0000 C CNN +F 3 "" H 6050 3850 60 0000 C CNN + 1 6050 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3700 6050 3400 +Wire Wire Line + 6050 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 3250 +Wire Wire Line + 6050 4000 6050 4300 +Wire Wire Line + 6050 4300 5800 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sub b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sub new file mode 100644 index 00000000..2319995c --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sub @@ -0,0 +1,12 @@ +* Subcircuit INVCMOS +.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +* Control Statements + +.ends INVCMOS
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS280/INVCMOS_Previous_Values.xml new file mode 100644 index 00000000..e5bb98c7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/NMOS-180nm.lib b/library/SubcircuitLibrary/SN74ALS280/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/SN74ALS280/PMOS-180nm.lib b/library/SubcircuitLibrary/SN74ALS280/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280-cache.lib b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280-cache.lib new file mode 100644 index 00000000..9a2d9f78 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280-cache.lib @@ -0,0 +1,150 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir new file mode 100644 index 00000000..003d3f7e --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir @@ -0,0 +1,71 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74ALS280\SN74ALS280.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/15/24 20:41:17 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U14 Net-_U13-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and +U15 Net-_U14-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad3_ d_and +X19 Net-_U1-Pad3_ Net-_U1-Pad2_ ? Net-_U31-Pad1_ 3_and +U22 Net-_U22-Pad1_ Net-_U13-Pad3_ Net-_U22-Pad3_ d_nand +U23 Net-_U23-Pad1_ Net-_U14-Pad3_ Net-_U23-Pad3_ d_nand +U24 Net-_U24-Pad1_ Net-_U15-Pad3_ Net-_U24-Pad3_ d_nand +X22 Net-_U31-Pad2_ Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U34-Pad1_ 4_and +U31 Net-_U31-Pad1_ Net-_U31-Pad2_ d_inverter +U34 Net-_U34-Pad1_ Net-_U34-Pad2_ d_inverter +U35 Net-_U35-Pad1_ Net-_U35-Pad2_ d_inverter +U36 Net-_U36-Pad1_ Net-_U36-Pad2_ d_inverter +X29 Net-_U34-Pad2_ Net-_U35-Pad1_ Net-_U36-Pad1_ Net-_X29-Pad4_ 3_and +X30 Net-_U34-Pad1_ Net-_U35-Pad2_ Net-_U36-Pad1_ Net-_X30-Pad4_ 3_and +X31 Net-_U34-Pad1_ Net-_U36-Pad2_ Net-_U35-Pad1_ Net-_X31-Pad4_ 3_and +X32 Net-_U34-Pad2_ Net-_U36-Pad2_ Net-_U35-Pad2_ Net-_X32-Pad4_ 3_and +X34 Net-_X29-Pad4_ Net-_X30-Pad4_ Net-_X31-Pad4_ Net-_X32-Pad4_ Net-_U38-Pad1_ 4_OR +U38 Net-_U38-Pad1_ Net-_U1-Pad10_ d_inverter +X25 Net-_U34-Pad1_ Net-_U36-Pad2_ Net-_U35-Pad2_ Net-_X25-Pad4_ 3_and +X26 Net-_U34-Pad2_ Net-_U36-Pad2_ Net-_U35-Pad1_ Net-_X26-Pad4_ 3_and +X27 Net-_U34-Pad2_ Net-_U35-Pad2_ Net-_U36-Pad1_ Net-_X27-Pad4_ 3_and +X28 Net-_U34-Pad1_ Net-_U35-Pad1_ Net-_U36-Pad1_ Net-_X28-Pad4_ 3_and +X33 Net-_X25-Pad4_ Net-_X26-Pad4_ Net-_X27-Pad4_ Net-_X28-Pad4_ Net-_U37-Pad1_ 4_OR +U37 Net-_U37-Pad1_ Net-_U1-Pad11_ d_inverter +U17 Net-_U1-Pad2_ Net-_U13-Pad2_ d_inverter +U43 Net-_U14-Pad2_ Net-_U22-Pad1_ d_inverter +U16 Net-_U1-Pad1_ Net-_U14-Pad2_ d_inverter +U44 Net-_U13-Pad2_ Net-_U23-Pad1_ d_inverter +U18 Net-_U1-Pad3_ Net-_U13-Pad1_ d_inverter +U45 Net-_U13-Pad1_ Net-_U24-Pad1_ d_inverter +U28 Net-_U21-Pad2_ Net-_U20-Pad2_ Net-_U28-Pad3_ d_and +U29 Net-_U21-Pad2_ Net-_U19-Pad2_ Net-_U29-Pad3_ d_and +U30 Net-_U19-Pad2_ Net-_U20-Pad2_ Net-_U30-Pad3_ d_and +X1 Net-_U1-Pad6_ Net-_U1-Pad5_ ? Net-_U58-Pad1_ 3_and +U52 Net-_U46-Pad2_ Net-_U28-Pad3_ Net-_U52-Pad3_ d_nand +U53 Net-_U47-Pad2_ Net-_U29-Pad3_ Net-_U53-Pad3_ d_nand +U54 Net-_U48-Pad2_ Net-_U30-Pad3_ Net-_U54-Pad3_ d_nand +X3 Net-_U58-Pad2_ Net-_U52-Pad3_ Net-_U53-Pad3_ Net-_U54-Pad3_ Net-_U35-Pad1_ 4_and +U58 Net-_U58-Pad1_ Net-_U58-Pad2_ d_inverter +U20 Net-_U1-Pad5_ Net-_U20-Pad2_ d_inverter +U46 Net-_U19-Pad2_ Net-_U46-Pad2_ d_inverter +U19 Net-_U1-Pad4_ Net-_U19-Pad2_ d_inverter +U47 Net-_U20-Pad2_ Net-_U47-Pad2_ d_inverter +U21 Net-_U1-Pad6_ Net-_U21-Pad2_ d_inverter +U48 Net-_U21-Pad2_ Net-_U48-Pad2_ d_inverter +U32 Net-_U27-Pad2_ Net-_U26-Pad2_ Net-_U32-Pad3_ d_and +U33 Net-_U27-Pad2_ Net-_U25-Pad2_ Net-_U33-Pad3_ d_and +U42 Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U42-Pad3_ d_and +X2 Net-_U1-Pad9_ Net-_U1-Pad8_ ? Net-_U59-Pad1_ 3_and +U55 Net-_U49-Pad2_ Net-_U32-Pad3_ Net-_U55-Pad3_ d_nand +U56 Net-_U50-Pad2_ Net-_U33-Pad3_ Net-_U56-Pad3_ d_nand +U57 Net-_U51-Pad2_ Net-_U42-Pad3_ Net-_U57-Pad3_ d_nand +X4 Net-_U59-Pad2_ Net-_U55-Pad3_ Net-_U56-Pad3_ Net-_U57-Pad3_ Net-_U36-Pad1_ 4_and +U59 Net-_U59-Pad1_ Net-_U59-Pad2_ d_inverter +U26 Net-_U1-Pad8_ Net-_U26-Pad2_ d_inverter +U49 Net-_U25-Pad2_ Net-_U49-Pad2_ d_inverter +U25 Net-_U1-Pad7_ Net-_U25-Pad2_ d_inverter +U50 Net-_U26-Pad2_ Net-_U50-Pad2_ d_inverter +U27 Net-_U1-Pad9_ Net-_U27-Pad2_ d_inverter +U51 Net-_U27-Pad2_ Net-_U51-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir.out b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir.out new file mode 100644 index 00000000..86483e73 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir.out @@ -0,0 +1,207 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74als280\sn74als280.cir + +.include 4_and.sub +.include 4_OR.sub +.include 3_and.sub +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u14 net-_u13-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and +* u15 net-_u14-pad2_ net-_u13-pad2_ net-_u15-pad3_ d_and +x19 net-_u1-pad3_ net-_u1-pad2_ ? net-_u31-pad1_ 3_and +* u22 net-_u22-pad1_ net-_u13-pad3_ net-_u22-pad3_ d_nand +* u23 net-_u23-pad1_ net-_u14-pad3_ net-_u23-pad3_ d_nand +* u24 net-_u24-pad1_ net-_u15-pad3_ net-_u24-pad3_ d_nand +x22 net-_u31-pad2_ net-_u22-pad3_ net-_u23-pad3_ net-_u24-pad3_ net-_u34-pad1_ 4_and +* u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter +* u34 net-_u34-pad1_ net-_u34-pad2_ d_inverter +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter +x29 net-_u34-pad2_ net-_u35-pad1_ net-_u36-pad1_ net-_x29-pad4_ 3_and +x30 net-_u34-pad1_ net-_u35-pad2_ net-_u36-pad1_ net-_x30-pad4_ 3_and +x31 net-_u34-pad1_ net-_u36-pad2_ net-_u35-pad1_ net-_x31-pad4_ 3_and +x32 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad2_ net-_x32-pad4_ 3_and +x34 net-_x29-pad4_ net-_x30-pad4_ net-_x31-pad4_ net-_x32-pad4_ net-_u38-pad1_ 4_OR +* u38 net-_u38-pad1_ net-_u1-pad10_ d_inverter +x25 net-_u34-pad1_ net-_u36-pad2_ net-_u35-pad2_ net-_x25-pad4_ 3_and +x26 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad1_ net-_x26-pad4_ 3_and +x27 net-_u34-pad2_ net-_u35-pad2_ net-_u36-pad1_ net-_x27-pad4_ 3_and +x28 net-_u34-pad1_ net-_u35-pad1_ net-_u36-pad1_ net-_x28-pad4_ 3_and +x33 net-_x25-pad4_ net-_x26-pad4_ net-_x27-pad4_ net-_x28-pad4_ net-_u37-pad1_ 4_OR +* u37 net-_u37-pad1_ net-_u1-pad11_ d_inverter +* u17 net-_u1-pad2_ net-_u13-pad2_ d_inverter +* u43 net-_u14-pad2_ net-_u22-pad1_ d_inverter +* u16 net-_u1-pad1_ net-_u14-pad2_ d_inverter +* u44 net-_u13-pad2_ net-_u23-pad1_ d_inverter +* u18 net-_u1-pad3_ net-_u13-pad1_ d_inverter +* u45 net-_u13-pad1_ net-_u24-pad1_ d_inverter +* u28 net-_u21-pad2_ net-_u20-pad2_ net-_u28-pad3_ d_and +* u29 net-_u21-pad2_ net-_u19-pad2_ net-_u29-pad3_ d_and +* u30 net-_u19-pad2_ net-_u20-pad2_ net-_u30-pad3_ d_and +x1 net-_u1-pad6_ net-_u1-pad5_ ? net-_u58-pad1_ 3_and +* u52 net-_u46-pad2_ net-_u28-pad3_ net-_u52-pad3_ d_nand +* u53 net-_u47-pad2_ net-_u29-pad3_ net-_u53-pad3_ d_nand +* u54 net-_u48-pad2_ net-_u30-pad3_ net-_u54-pad3_ d_nand +x3 net-_u58-pad2_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u35-pad1_ 4_and +* u58 net-_u58-pad1_ net-_u58-pad2_ d_inverter +* u20 net-_u1-pad5_ net-_u20-pad2_ d_inverter +* u46 net-_u19-pad2_ net-_u46-pad2_ d_inverter +* u19 net-_u1-pad4_ net-_u19-pad2_ d_inverter +* u47 net-_u20-pad2_ net-_u47-pad2_ d_inverter +* u21 net-_u1-pad6_ net-_u21-pad2_ d_inverter +* u48 net-_u21-pad2_ net-_u48-pad2_ d_inverter +* u32 net-_u27-pad2_ net-_u26-pad2_ net-_u32-pad3_ d_and +* u33 net-_u27-pad2_ net-_u25-pad2_ net-_u33-pad3_ d_and +* u42 net-_u25-pad2_ net-_u26-pad2_ net-_u42-pad3_ d_and +x2 net-_u1-pad9_ net-_u1-pad8_ ? net-_u59-pad1_ 3_and +* u55 net-_u49-pad2_ net-_u32-pad3_ net-_u55-pad3_ d_nand +* u56 net-_u50-pad2_ net-_u33-pad3_ net-_u56-pad3_ d_nand +* u57 net-_u51-pad2_ net-_u42-pad3_ net-_u57-pad3_ d_nand +x4 net-_u59-pad2_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u36-pad1_ 4_and +* u59 net-_u59-pad1_ net-_u59-pad2_ d_inverter +* u26 net-_u1-pad8_ net-_u26-pad2_ d_inverter +* u49 net-_u25-pad2_ net-_u49-pad2_ d_inverter +* u25 net-_u1-pad7_ net-_u25-pad2_ d_inverter +* u50 net-_u26-pad2_ net-_u50-pad2_ d_inverter +* u27 net-_u1-pad9_ net-_u27-pad2_ d_inverter +* u51 net-_u27-pad2_ net-_u51-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port +a1 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a2 [net-_u13-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a3 [net-_u14-pad2_ net-_u13-pad2_ ] net-_u15-pad3_ u15 +a4 [net-_u22-pad1_ net-_u13-pad3_ ] net-_u22-pad3_ u22 +a5 [net-_u23-pad1_ net-_u14-pad3_ ] net-_u23-pad3_ u23 +a6 [net-_u24-pad1_ net-_u15-pad3_ ] net-_u24-pad3_ u24 +a7 net-_u31-pad1_ net-_u31-pad2_ u31 +a8 net-_u34-pad1_ net-_u34-pad2_ u34 +a9 net-_u35-pad1_ net-_u35-pad2_ u35 +a10 net-_u36-pad1_ net-_u36-pad2_ u36 +a11 net-_u38-pad1_ net-_u1-pad10_ u38 +a12 net-_u37-pad1_ net-_u1-pad11_ u37 +a13 net-_u1-pad2_ net-_u13-pad2_ u17 +a14 net-_u14-pad2_ net-_u22-pad1_ u43 +a15 net-_u1-pad1_ net-_u14-pad2_ u16 +a16 net-_u13-pad2_ net-_u23-pad1_ u44 +a17 net-_u1-pad3_ net-_u13-pad1_ u18 +a18 net-_u13-pad1_ net-_u24-pad1_ u45 +a19 [net-_u21-pad2_ net-_u20-pad2_ ] net-_u28-pad3_ u28 +a20 [net-_u21-pad2_ net-_u19-pad2_ ] net-_u29-pad3_ u29 +a21 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u30-pad3_ u30 +a22 [net-_u46-pad2_ net-_u28-pad3_ ] net-_u52-pad3_ u52 +a23 [net-_u47-pad2_ net-_u29-pad3_ ] net-_u53-pad3_ u53 +a24 [net-_u48-pad2_ net-_u30-pad3_ ] net-_u54-pad3_ u54 +a25 net-_u58-pad1_ net-_u58-pad2_ u58 +a26 net-_u1-pad5_ net-_u20-pad2_ u20 +a27 net-_u19-pad2_ net-_u46-pad2_ u46 +a28 net-_u1-pad4_ net-_u19-pad2_ u19 +a29 net-_u20-pad2_ net-_u47-pad2_ u47 +a30 net-_u1-pad6_ net-_u21-pad2_ u21 +a31 net-_u21-pad2_ net-_u48-pad2_ u48 +a32 [net-_u27-pad2_ net-_u26-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u27-pad2_ net-_u25-pad2_ ] net-_u33-pad3_ u33 +a34 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u42-pad3_ u42 +a35 [net-_u49-pad2_ net-_u32-pad3_ ] net-_u55-pad3_ u55 +a36 [net-_u50-pad2_ net-_u33-pad3_ ] net-_u56-pad3_ u56 +a37 [net-_u51-pad2_ net-_u42-pad3_ ] net-_u57-pad3_ u57 +a38 net-_u59-pad1_ net-_u59-pad2_ u59 +a39 net-_u1-pad8_ net-_u26-pad2_ u26 +a40 net-_u25-pad2_ net-_u49-pad2_ u49 +a41 net-_u1-pad7_ net-_u25-pad2_ u25 +a42 net-_u26-pad2_ net-_u50-pad2_ u50 +a43 net-_u1-pad9_ net-_u27-pad2_ u27 +a44 net-_u27-pad2_ net-_u51-pad2_ u51 +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-03 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.pro b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.proj b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.proj new file mode 100644 index 00000000..ed5e61fc --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.proj @@ -0,0 +1 @@ +schematicFile SN74ALS280.sch diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch new file mode 100644 index 00000000..67998706 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch @@ -0,0 +1,1294 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74ALS280-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" 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+$EndComp +$Comp +L d_inverter U43 +U 1 1 666ED171 +P 11700 4100 +F 0 "U43" H 11700 4000 60 0000 C CNN +F 1 "d_inverter" H 11700 4250 60 0000 C CNN +F 2 "" H 11750 4050 60 0000 C CNN +F 3 "" H 11750 4050 60 0000 C CNN + 1 11700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12000 4100 12250 4100 +$Comp +L d_inverter U16 +U 1 1 666ED179 +P 9050 4100 +F 0 "U16" H 9050 4000 60 0000 C CNN +F 1 "d_inverter" H 9050 4250 60 0000 C CNN +F 2 "" H 9100 4050 60 0000 C CNN +F 3 "" H 9100 4050 60 0000 C CNN + 1 9050 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U44 +U 1 1 666ED8A2 +P 11700 4800 +F 0 "U44" H 11700 4700 60 0000 C CNN +F 1 "d_inverter" H 11700 4950 60 0000 C CNN +F 2 "" H 11750 4750 60 0000 C CNN +F 3 "" H 11750 4750 60 0000 C CNN + 1 11700 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12000 4800 12250 4800 +$Comp +L d_inverter U18 +U 1 1 666EDB41 +P 9050 5550 +F 0 "U18" H 9050 5450 60 0000 C CNN +F 1 "d_inverter" H 9050 5700 60 0000 C CNN +F 2 "" H 9100 5500 60 0000 C CNN +F 3 "" H 9100 5500 60 0000 C CNN + 1 9050 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U45 +U 1 1 666EDC64 +P 11750 5550 +F 0 "U45" H 11750 5450 60 0000 C CNN +F 1 "d_inverter" H 11750 5700 60 0000 C CNN +F 2 "" H 11800 5500 60 0000 C CNN +F 3 "" H 11800 5500 60 0000 C CNN + 1 11750 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12050 5550 12300 5550 +$Comp +L d_and U28 +U 1 1 666EEBD7 +P 10700 7950 +F 0 "U28" H 10700 7950 60 0000 C CNN +F 1 "d_and" H 10750 8050 60 0000 C CNN +F 2 "" H 10700 7950 60 0000 C CNN +F 3 "" H 10700 7950 60 0000 C CNN + 1 10700 7950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9400 7600 11450 7600 +$Comp +L d_and U29 +U 1 1 666EEBDE +P 10700 8650 +F 0 "U29" H 10700 8650 60 0000 C CNN +F 1 "d_and" H 10750 8750 60 0000 C CNN +F 2 "" H 10700 8650 60 0000 C CNN +F 3 "" H 10700 8650 60 0000 C CNN + 1 10700 8650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9400 8300 11450 8300 +$Comp +L d_and U30 +U 1 1 666EEBE5 +P 10750 9400 +F 0 "U30" H 10750 9400 60 0000 C CNN +F 1 "d_and" H 10800 9500 60 0000 C CNN +F 2 "" H 10750 9400 60 0000 C CNN +F 3 "" H 10750 9400 60 0000 C CNN + 1 10750 9400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9400 9050 11500 9050 +Wire Wire Line + 10250 7850 10100 7850 +Wire Wire Line + 10100 7850 10100 9050 +Wire Wire Line + 10100 8550 10250 8550 +Connection ~ 10100 9050 +Connection ~ 10100 8550 +Wire Wire Line + 10300 9400 9800 9400 +Wire Wire Line + 9800 9400 9800 8300 +Connection ~ 9800 8300 +Wire Wire Line + 10000 8300 10000 7950 +Wire Wire Line + 10000 7950 10250 7950 +Connection ~ 10000 8300 +Wire Wire Line + 10250 9300 10300 9300 +Wire Wire Line + 10250 7600 10250 9300 +Connection ~ 10250 7600 +Connection ~ 10250 8650 +$Comp +L 3_and X1 +U 1 1 666EEBFB +P 12700 6950 +F 0 "X1" H 12800 6900 60 0000 C CNN +F 1 "3_and" H 12850 7100 60 0000 C CNN +F 2 "" H 12700 6950 60 0000 C CNN +F 3 "" H 12700 6950 60 0000 C CNN + 1 12700 6950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12350 7000 8500 7000 +Wire Wire Line + 8500 7000 8500 7600 +Wire Wire Line + 6450 8300 8800 8300 +Wire Wire Line + 8350 8300 8350 6900 +Wire Wire Line + 8350 6900 12350 6900 +Wire Wire Line + 12350 6800 8200 6800 +Wire Wire Line + 8200 6800 8200 9050 +Wire Wire Line + 7550 9050 8800 9050 +Connection ~ 8350 8300 +Connection ~ 8200 9050 +$Comp +L d_nand U52 +U 1 1 666EEC0B +P 12750 7700 +F 0 "U52" H 12750 7700 60 0000 C CNN +F 1 "d_nand" H 12800 7800 60 0000 C CNN +F 2 "" H 12750 7700 60 0000 C CNN +F 3 "" H 12750 7700 60 0000 C CNN + 1 12750 7700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U53 +U 1 1 666EEC11 +P 12750 8400 +F 0 "U53" H 12750 8400 60 0000 C CNN +F 1 "d_nand" H 12800 8500 60 0000 C CNN +F 2 "" H 12750 8400 60 0000 C CNN +F 3 "" H 12750 8400 60 0000 C CNN + 1 12750 8400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U54 +U 1 1 666EEC17 +P 12800 9150 +F 0 "U54" H 12800 9150 60 0000 C CNN +F 1 "d_nand" H 12850 9250 60 0000 C CNN +F 2 "" H 12800 9150 60 0000 C CNN +F 3 "" H 12800 9150 60 0000 C CNN + 1 12800 9150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12350 9150 12350 9350 +Wire Wire Line + 12350 9350 11200 9350 +Wire Wire Line + 11150 8600 12300 8600 +Wire Wire Line + 12300 8600 12300 8400 +Wire Wire Line + 11150 7900 12300 7900 +Wire Wire Line + 12300 7900 12300 7700 +$Comp +L 4_and X3 +U 1 1 666EEC23 +P 14150 8150 +F 0 "X3" H 14200 8100 60 0000 C CNN +F 1 "4_and" H 14250 8250 60 0000 C CNN +F 2 "" H 14150 8150 60 0000 C CNN +F 3 "" H 14150 8150 60 0000 C CNN + 1 14150 8150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U58 +U 1 1 666EEC29 +P 13550 7250 +F 0 "U58" H 13550 7150 60 0000 C CNN +F 1 "d_inverter" H 13550 7400 60 0000 C CNN +F 2 "" H 13600 7200 60 0000 C CNN +F 3 "" H 13600 7200 60 0000 C CNN + 1 13550 7250 + 0 1 1 0 +$EndComp +Wire Wire Line + 13550 6950 13550 6900 +Wire Wire Line + 13550 6900 13200 6900 +Wire Wire Line + 13550 7550 13550 8000 +Wire Wire Line + 13550 8000 13750 8000 +Wire Wire Line + 13750 8100 13500 8100 +Wire Wire Line + 13500 8100 13500 7650 +Wire Wire Line + 13500 7650 13200 7650 +Wire Wire Line + 13250 9100 13550 9100 +Wire Wire Line + 13550 9100 13550 8300 +Wire Wire Line + 13550 8300 13750 8300 +Wire Wire Line + 13750 8200 13500 8200 +Wire Wire Line + 13500 8200 13500 8350 +Wire Wire Line + 13500 8350 13200 8350 +Wire Wire Line + 6450 8400 7550 8400 +Wire Wire Line + 7550 8400 7550 9050 +Wire Wire Line + 7550 7600 8800 7600 +Wire Wire Line + 7550 7600 7550 8200 +Wire Wire Line + 7550 8200 6450 8200 +$Comp +L d_inverter U20 +U 1 1 666EEC41 +P 9100 8300 +F 0 "U20" H 9100 8200 60 0000 C CNN +F 1 "d_inverter" H 9100 8450 60 0000 C CNN +F 2 "" H 9150 8250 60 0000 C CNN +F 3 "" H 9150 8250 60 0000 C CNN + 1 9100 8300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U46 +U 1 1 666EEC49 +P 11750 7600 +F 0 "U46" H 11750 7500 60 0000 C CNN +F 1 "d_inverter" H 11750 7750 60 0000 C CNN +F 2 "" H 11800 7550 60 0000 C CNN +F 3 "" H 11800 7550 60 0000 C CNN + 1 11750 7600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12050 7600 12300 7600 +$Comp +L d_inverter U19 +U 1 1 666EEC51 +P 9100 7600 +F 0 "U19" H 9100 7500 60 0000 C CNN +F 1 "d_inverter" H 9100 7750 60 0000 C CNN +F 2 "" H 9150 7550 60 0000 C CNN +F 3 "" H 9150 7550 60 0000 C CNN + 1 9100 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U47 +U 1 1 666EEC59 +P 11750 8300 +F 0 "U47" H 11750 8200 60 0000 C CNN +F 1 "d_inverter" H 11750 8450 60 0000 C CNN +F 2 "" H 11800 8250 60 0000 C CNN +F 3 "" H 11800 8250 60 0000 C CNN + 1 11750 8300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12050 8300 12300 8300 +$Comp +L d_inverter U21 +U 1 1 666EEC61 +P 9100 9050 +F 0 "U21" H 9100 8950 60 0000 C CNN +F 1 "d_inverter" H 9100 9200 60 0000 C CNN +F 2 "" H 9150 9000 60 0000 C CNN +F 3 "" H 9150 9000 60 0000 C CNN + 1 9100 9050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U48 +U 1 1 666EEC69 +P 11800 9050 +F 0 "U48" H 11800 8950 60 0000 C CNN +F 1 "d_inverter" H 11800 9200 60 0000 C CNN +F 2 "" H 11850 9000 60 0000 C CNN +F 3 "" H 11850 9000 60 0000 C CNN + 1 11800 9050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12100 9050 12350 9050 +Wire Wire Line + 14700 8150 14650 8150 +$Comp +L d_and U32 +U 1 1 666F08E4 +P 10800 11450 +F 0 "U32" H 10800 11450 60 0000 C CNN +F 1 "d_and" H 10850 11550 60 0000 C CNN +F 2 "" H 10800 11450 60 0000 C CNN +F 3 "" H 10800 11450 60 0000 C CNN + 1 10800 11450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9500 11100 11550 11100 +$Comp +L d_and U33 +U 1 1 666F08EB +P 10800 12150 +F 0 "U33" H 10800 12150 60 0000 C CNN +F 1 "d_and" H 10850 12250 60 0000 C CNN +F 2 "" H 10800 12150 60 0000 C CNN +F 3 "" H 10800 12150 60 0000 C CNN + 1 10800 12150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9500 11800 11550 11800 +$Comp +L d_and U42 +U 1 1 666F08F2 +P 10850 12900 +F 0 "U42" H 10850 12900 60 0000 C CNN +F 1 "d_and" H 10900 13000 60 0000 C CNN +F 2 "" H 10850 12900 60 0000 C CNN +F 3 "" H 10850 12900 60 0000 C CNN + 1 10850 12900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9500 12550 11600 12550 +Wire Wire Line + 10350 11350 10200 11350 +Wire Wire Line + 10200 11350 10200 12550 +Wire Wire Line + 10200 12050 10350 12050 +Connection ~ 10200 12550 +Connection ~ 10200 12050 +Wire Wire Line + 10400 12900 9900 12900 +Wire Wire Line + 9900 12900 9900 11800 +Connection ~ 9900 11800 +Wire Wire Line + 10100 11800 10100 11450 +Wire Wire Line + 10100 11450 10350 11450 +Connection ~ 10100 11800 +Wire Wire Line + 10350 12800 10400 12800 +Wire Wire Line + 10350 11100 10350 12800 +Connection ~ 10350 11100 +Connection ~ 10350 12150 +$Comp +L 3_and X2 +U 1 1 666F0908 +P 12800 10450 +F 0 "X2" H 12900 10400 60 0000 C CNN +F 1 "3_and" H 12950 10600 60 0000 C CNN +F 2 "" H 12800 10450 60 0000 C CNN +F 3 "" H 12800 10450 60 0000 C CNN + 1 12800 10450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12450 10500 8600 10500 +Wire Wire Line + 8600 10500 8600 11100 +Wire Wire Line + 6550 11800 8900 11800 +Wire Wire Line + 8450 11800 8450 10400 +Wire Wire Line + 8450 10400 12450 10400 +Wire Wire Line + 12450 10300 8300 10300 +Wire Wire Line + 8300 10300 8300 12550 +Wire Wire Line + 7650 12550 8900 12550 +Connection ~ 8450 11800 +Connection ~ 8300 12550 +$Comp +L d_nand U55 +U 1 1 666F0918 +P 12850 11200 +F 0 "U55" H 12850 11200 60 0000 C CNN +F 1 "d_nand" H 12900 11300 60 0000 C CNN +F 2 "" H 12850 11200 60 0000 C CNN +F 3 "" H 12850 11200 60 0000 C CNN + 1 12850 11200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U56 +U 1 1 666F091E +P 12850 11900 +F 0 "U56" H 12850 11900 60 0000 C CNN +F 1 "d_nand" H 12900 12000 60 0000 C CNN +F 2 "" H 12850 11900 60 0000 C CNN +F 3 "" H 12850 11900 60 0000 C CNN + 1 12850 11900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U57 +U 1 1 666F0924 +P 12900 12650 +F 0 "U57" H 12900 12650 60 0000 C CNN +F 1 "d_nand" H 12950 12750 60 0000 C CNN +F 2 "" H 12900 12650 60 0000 C CNN +F 3 "" H 12900 12650 60 0000 C CNN + 1 12900 12650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12450 12650 12450 12850 +Wire Wire Line + 12450 12850 11300 12850 +Wire Wire Line + 11250 12100 12400 12100 +Wire Wire Line + 12400 12100 12400 11900 +Wire Wire Line + 11250 11400 12400 11400 +Wire Wire Line + 12400 11400 12400 11200 +$Comp +L 4_and X4 +U 1 1 666F0930 +P 14250 11650 +F 0 "X4" H 14300 11600 60 0000 C CNN +F 1 "4_and" H 14350 11750 60 0000 C CNN +F 2 "" H 14250 11650 60 0000 C CNN +F 3 "" H 14250 11650 60 0000 C CNN + 1 14250 11650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U59 +U 1 1 666F0936 +P 13650 10750 +F 0 "U59" H 13650 10650 60 0000 C CNN +F 1 "d_inverter" H 13650 10900 60 0000 C CNN +F 2 "" H 13700 10700 60 0000 C CNN +F 3 "" H 13700 10700 60 0000 C CNN + 1 13650 10750 + 0 1 1 0 +$EndComp +Wire Wire Line + 13650 10450 13650 10400 +Wire Wire Line + 13650 10400 13300 10400 +Wire Wire Line + 13650 11050 13650 11500 +Wire Wire Line + 13650 11500 13850 11500 +Wire Wire Line + 13850 11600 13600 11600 +Wire Wire Line + 13600 11600 13600 11150 +Wire Wire Line + 13600 11150 13300 11150 +Wire Wire Line + 13350 12600 13650 12600 +Wire Wire Line + 13650 12600 13650 11800 +Wire Wire Line + 13650 11800 13850 11800 +Wire Wire Line + 13850 11700 13600 11700 +Wire Wire Line + 13600 11700 13600 11850 +Wire Wire Line + 13600 11850 13300 11850 +Wire Wire Line + 6550 11900 7650 11900 +Wire Wire Line + 7650 11900 7650 12550 +Wire Wire Line + 7650 11100 8900 11100 +Wire Wire Line + 7650 11100 7650 11700 +Wire Wire Line + 7650 11700 6550 11700 +$Comp +L d_inverter U26 +U 1 1 666F094E +P 9200 11800 +F 0 "U26" H 9200 11700 60 0000 C CNN +F 1 "d_inverter" H 9200 11950 60 0000 C CNN +F 2 "" H 9250 11750 60 0000 C CNN +F 3 "" H 9250 11750 60 0000 C CNN + 1 9200 11800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U49 +U 1 1 666F0954 +P 11850 11100 +F 0 "U49" H 11850 11000 60 0000 C CNN +F 1 "d_inverter" H 11850 11250 60 0000 C CNN +F 2 "" H 11900 11050 60 0000 C CNN +F 3 "" H 11900 11050 60 0000 C CNN + 1 11850 11100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12150 11100 12400 11100 +$Comp +L d_inverter U25 +U 1 1 666F095B +P 9200 11100 +F 0 "U25" H 9200 11000 60 0000 C CNN +F 1 "d_inverter" H 9200 11250 60 0000 C CNN +F 2 "" H 9250 11050 60 0000 C CNN +F 3 "" H 9250 11050 60 0000 C CNN + 1 9200 11100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U50 +U 1 1 666F0961 +P 11850 11800 +F 0 "U50" H 11850 11700 60 0000 C CNN +F 1 "d_inverter" H 11850 11950 60 0000 C CNN +F 2 "" H 11900 11750 60 0000 C CNN +F 3 "" H 11900 11750 60 0000 C CNN + 1 11850 11800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12150 11800 12400 11800 +$Comp +L d_inverter U27 +U 1 1 666F0968 +P 9200 12550 +F 0 "U27" H 9200 12450 60 0000 C CNN +F 1 "d_inverter" H 9200 12700 60 0000 C CNN +F 2 "" H 9250 12500 60 0000 C CNN +F 3 "" H 9250 12500 60 0000 C CNN + 1 9200 12550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U51 +U 1 1 666F096E +P 11900 12550 +F 0 "U51" H 11900 12450 60 0000 C CNN +F 1 "d_inverter" H 11900 12700 60 0000 C CNN +F 2 "" H 11950 12500 60 0000 C CNN +F 3 "" H 11950 12500 60 0000 C CNN + 1 11900 12550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12200 12550 12450 12550 +$Comp +L PORT U1 +U 1 1 666DBC06 +P 6150 4700 +F 0 "U1" H 6200 4800 30 0000 C CNN +F 1 "PORT" H 6150 4700 30 0000 C CNN +F 2 "" H 6150 4700 60 0000 C CNN +F 3 "" H 6150 4700 60 0000 C CNN + 1 6150 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 666DBC97 +P 6150 4800 +F 0 "U1" H 6200 4900 30 0000 C CNN +F 1 "PORT" H 6150 4800 30 0000 C CNN +F 2 "" H 6150 4800 60 0000 C CNN +F 3 "" H 6150 4800 60 0000 C CNN + 2 6150 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 666DBD28 +P 6150 4900 +F 0 "U1" H 6200 5000 30 0000 C CNN +F 1 "PORT" H 6150 4900 30 0000 C CNN +F 2 "" H 6150 4900 60 0000 C CNN +F 3 "" H 6150 4900 60 0000 C CNN + 3 6150 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 666DC229 +P 6200 8200 +F 0 "U1" H 6250 8300 30 0000 C CNN +F 1 "PORT" H 6200 8200 30 0000 C CNN +F 2 "" H 6200 8200 60 0000 C CNN +F 3 "" H 6200 8200 60 0000 C CNN + 4 6200 8200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 666DC2C2 +P 6200 8300 +F 0 "U1" H 6250 8400 30 0000 C CNN +F 1 "PORT" H 6200 8300 30 0000 C CNN +F 2 "" H 6200 8300 60 0000 C CNN +F 3 "" H 6200 8300 60 0000 C CNN + 5 6200 8300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 666DC359 +P 6200 8400 +F 0 "U1" H 6250 8500 30 0000 C CNN +F 1 "PORT" H 6200 8400 30 0000 C CNN +F 2 "" H 6200 8400 60 0000 C CNN +F 3 "" H 6200 8400 60 0000 C CNN + 6 6200 8400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 666DC854 +P 6300 11700 +F 0 "U1" H 6350 11800 30 0000 C CNN +F 1 "PORT" H 6300 11700 30 0000 C CNN +F 2 "" H 6300 11700 60 0000 C CNN +F 3 "" H 6300 11700 60 0000 C CNN + 7 6300 11700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 666DC8F1 +P 6300 11800 +F 0 "U1" H 6350 11900 30 0000 C CNN +F 1 "PORT" H 6300 11800 30 0000 C CNN +F 2 "" H 6300 11800 60 0000 C CNN +F 3 "" H 6300 11800 60 0000 C CNN + 8 6300 11800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 666DC98E +P 6300 11900 +F 0 "U1" H 6350 12000 30 0000 C CNN +F 1 "PORT" H 6300 11900 30 0000 C CNN +F 2 "" H 6300 11900 60 0000 C CNN +F 3 "" H 6300 11900 60 0000 C CNN + 9 6300 11900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 666DD060 +P 20950 7950 +F 0 "U1" H 21000 8050 30 0000 C CNN +F 1 "PORT" H 20950 7950 30 0000 C CNN +F 2 "" H 20950 7950 60 0000 C CNN +F 3 "" H 20950 7950 60 0000 C CNN + 10 20950 7950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 666DD105 +P 20950 8050 +F 0 "U1" H 21000 8150 30 0000 C CNN +F 1 "PORT" H 20950 8050 30 0000 C CNN +F 2 "" H 20950 8050 60 0000 C CNN +F 3 "" H 20950 8050 60 0000 C CNN + 11 20950 8050 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sub b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sub new file mode 100644 index 00000000..07595af7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sub @@ -0,0 +1,201 @@ +* Subcircuit SN74ALS280 +.subckt SN74ALS280 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ +* c:\fossee\esim\library\subcircuitlibrary\sn74als280\sn74als280.cir +.include 4_and.sub +.include 4_OR.sub +.include 3_and.sub +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u14 net-_u13-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and +* u15 net-_u14-pad2_ net-_u13-pad2_ net-_u15-pad3_ d_and +x19 net-_u1-pad3_ net-_u1-pad2_ ? net-_u31-pad1_ 3_and +* u22 net-_u22-pad1_ net-_u13-pad3_ net-_u22-pad3_ d_nand +* u23 net-_u23-pad1_ net-_u14-pad3_ net-_u23-pad3_ d_nand +* u24 net-_u24-pad1_ net-_u15-pad3_ net-_u24-pad3_ d_nand +x22 net-_u31-pad2_ net-_u22-pad3_ net-_u23-pad3_ net-_u24-pad3_ net-_u34-pad1_ 4_and +* u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter +* u34 net-_u34-pad1_ net-_u34-pad2_ d_inverter +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter +x29 net-_u34-pad2_ net-_u35-pad1_ net-_u36-pad1_ net-_x29-pad4_ 3_and +x30 net-_u34-pad1_ net-_u35-pad2_ net-_u36-pad1_ net-_x30-pad4_ 3_and +x31 net-_u34-pad1_ net-_u36-pad2_ net-_u35-pad1_ net-_x31-pad4_ 3_and +x32 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad2_ net-_x32-pad4_ 3_and +x34 net-_x29-pad4_ net-_x30-pad4_ net-_x31-pad4_ net-_x32-pad4_ net-_u38-pad1_ 4_OR +* u38 net-_u38-pad1_ net-_u1-pad10_ d_inverter +x25 net-_u34-pad1_ net-_u36-pad2_ net-_u35-pad2_ net-_x25-pad4_ 3_and +x26 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad1_ net-_x26-pad4_ 3_and +x27 net-_u34-pad2_ net-_u35-pad2_ net-_u36-pad1_ net-_x27-pad4_ 3_and +x28 net-_u34-pad1_ net-_u35-pad1_ net-_u36-pad1_ net-_x28-pad4_ 3_and +x33 net-_x25-pad4_ net-_x26-pad4_ net-_x27-pad4_ net-_x28-pad4_ net-_u37-pad1_ 4_OR +* u37 net-_u37-pad1_ net-_u1-pad11_ d_inverter +* u17 net-_u1-pad2_ net-_u13-pad2_ d_inverter +* u43 net-_u14-pad2_ net-_u22-pad1_ d_inverter +* u16 net-_u1-pad1_ net-_u14-pad2_ d_inverter +* u44 net-_u13-pad2_ net-_u23-pad1_ d_inverter +* u18 net-_u1-pad3_ net-_u13-pad1_ d_inverter +* u45 net-_u13-pad1_ net-_u24-pad1_ d_inverter +* u28 net-_u21-pad2_ net-_u20-pad2_ net-_u28-pad3_ d_and +* u29 net-_u21-pad2_ net-_u19-pad2_ net-_u29-pad3_ d_and +* u30 net-_u19-pad2_ net-_u20-pad2_ net-_u30-pad3_ d_and +x1 net-_u1-pad6_ net-_u1-pad5_ ? net-_u58-pad1_ 3_and +* u52 net-_u46-pad2_ net-_u28-pad3_ net-_u52-pad3_ d_nand +* u53 net-_u47-pad2_ net-_u29-pad3_ net-_u53-pad3_ d_nand +* u54 net-_u48-pad2_ net-_u30-pad3_ net-_u54-pad3_ d_nand +x3 net-_u58-pad2_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u35-pad1_ 4_and +* u58 net-_u58-pad1_ net-_u58-pad2_ d_inverter +* u20 net-_u1-pad5_ net-_u20-pad2_ d_inverter +* u46 net-_u19-pad2_ net-_u46-pad2_ d_inverter +* u19 net-_u1-pad4_ net-_u19-pad2_ d_inverter +* u47 net-_u20-pad2_ net-_u47-pad2_ d_inverter +* u21 net-_u1-pad6_ net-_u21-pad2_ d_inverter +* u48 net-_u21-pad2_ net-_u48-pad2_ d_inverter +* u32 net-_u27-pad2_ net-_u26-pad2_ net-_u32-pad3_ d_and +* u33 net-_u27-pad2_ net-_u25-pad2_ net-_u33-pad3_ d_and +* u42 net-_u25-pad2_ net-_u26-pad2_ net-_u42-pad3_ d_and +x2 net-_u1-pad9_ net-_u1-pad8_ ? net-_u59-pad1_ 3_and +* u55 net-_u49-pad2_ net-_u32-pad3_ net-_u55-pad3_ d_nand +* u56 net-_u50-pad2_ net-_u33-pad3_ net-_u56-pad3_ d_nand +* u57 net-_u51-pad2_ net-_u42-pad3_ net-_u57-pad3_ d_nand +x4 net-_u59-pad2_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u36-pad1_ 4_and +* u59 net-_u59-pad1_ net-_u59-pad2_ d_inverter +* u26 net-_u1-pad8_ net-_u26-pad2_ d_inverter +* u49 net-_u25-pad2_ net-_u49-pad2_ d_inverter +* u25 net-_u1-pad7_ net-_u25-pad2_ d_inverter +* u50 net-_u26-pad2_ net-_u50-pad2_ d_inverter +* u27 net-_u1-pad9_ net-_u27-pad2_ d_inverter +* u51 net-_u27-pad2_ net-_u51-pad2_ d_inverter +a1 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a2 [net-_u13-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a3 [net-_u14-pad2_ net-_u13-pad2_ ] net-_u15-pad3_ u15 +a4 [net-_u22-pad1_ net-_u13-pad3_ ] net-_u22-pad3_ u22 +a5 [net-_u23-pad1_ net-_u14-pad3_ ] net-_u23-pad3_ u23 +a6 [net-_u24-pad1_ net-_u15-pad3_ ] net-_u24-pad3_ u24 +a7 net-_u31-pad1_ net-_u31-pad2_ u31 +a8 net-_u34-pad1_ net-_u34-pad2_ u34 +a9 net-_u35-pad1_ net-_u35-pad2_ u35 +a10 net-_u36-pad1_ net-_u36-pad2_ u36 +a11 net-_u38-pad1_ net-_u1-pad10_ u38 +a12 net-_u37-pad1_ net-_u1-pad11_ u37 +a13 net-_u1-pad2_ net-_u13-pad2_ u17 +a14 net-_u14-pad2_ net-_u22-pad1_ u43 +a15 net-_u1-pad1_ net-_u14-pad2_ u16 +a16 net-_u13-pad2_ net-_u23-pad1_ u44 +a17 net-_u1-pad3_ net-_u13-pad1_ u18 +a18 net-_u13-pad1_ net-_u24-pad1_ u45 +a19 [net-_u21-pad2_ net-_u20-pad2_ ] net-_u28-pad3_ u28 +a20 [net-_u21-pad2_ net-_u19-pad2_ ] net-_u29-pad3_ u29 +a21 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u30-pad3_ u30 +a22 [net-_u46-pad2_ net-_u28-pad3_ ] net-_u52-pad3_ u52 +a23 [net-_u47-pad2_ net-_u29-pad3_ ] net-_u53-pad3_ u53 +a24 [net-_u48-pad2_ net-_u30-pad3_ ] net-_u54-pad3_ u54 +a25 net-_u58-pad1_ net-_u58-pad2_ u58 +a26 net-_u1-pad5_ net-_u20-pad2_ u20 +a27 net-_u19-pad2_ net-_u46-pad2_ u46 +a28 net-_u1-pad4_ net-_u19-pad2_ u19 +a29 net-_u20-pad2_ net-_u47-pad2_ u47 +a30 net-_u1-pad6_ net-_u21-pad2_ u21 +a31 net-_u21-pad2_ net-_u48-pad2_ u48 +a32 [net-_u27-pad2_ net-_u26-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u27-pad2_ net-_u25-pad2_ ] net-_u33-pad3_ u33 +a34 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u42-pad3_ u42 +a35 [net-_u49-pad2_ net-_u32-pad3_ ] net-_u55-pad3_ u55 +a36 [net-_u50-pad2_ net-_u33-pad3_ ] net-_u56-pad3_ u56 +a37 [net-_u51-pad2_ net-_u42-pad3_ ] net-_u57-pad3_ u57 +a38 net-_u59-pad1_ net-_u59-pad2_ u59 +a39 net-_u1-pad8_ net-_u26-pad2_ u26 +a40 net-_u25-pad2_ net-_u49-pad2_ u49 +a41 net-_u1-pad7_ net-_u25-pad2_ u25 +a42 net-_u26-pad2_ net-_u50-pad2_ u50 +a43 net-_u1-pad9_ net-_u27-pad2_ u27 +a44 net-_u27-pad2_ net-_u51-pad2_ u51 +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74ALS280
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280_Previous_Values.xml new file mode 100644 index 00000000..7cdfe1a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v7 name="Source type">dc<field1 name="Value">0</field1></v7><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v8 name="Source type">dc<field1 name="Value">0</field1></v8><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v9 name="Source type">dc<field1 name="Value">0</field1></v9><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v3 name="Source type">dc<field1 name="Value">5</field1></v3></source><model><u13 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u15><u22 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u24><u31 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u31><u34 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u34><u16 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u17><u20 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u20><u25 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u26><u29 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u29><u32 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u32><u35 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u35><u18 name="type">d_and<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u19><u21 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u21><u27 name="type">d_nand<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_nand<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u28><u30 name="type">d_nand<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u30><u33 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u33><u36 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u36><u38 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u38><u37 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u37><u39 name="type">dac_bridge<field79 name="Enter value for out_low (default=0.0)" /><field80 name="Enter value for out_high (default=5.0)" /><field81 name="Enter value for out_undef (default=0.5)" /><field82 name="Enter value for input load (default=1.0e-12)" /><field83 name="Enter the Rise Time (default=1.0e-9)" /><field84 name="Enter the Fall Time (default=1.0e-9)" /></u39><u10 name="type">adc_bridge<field85 name="Enter value for in_low (default=1.0)" /><field86 name="Enter value for in_high (default=2.0)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /><field88 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">adc_bridge<field89 name="Enter value for in_low (default=1.0)" /><field90 name="Enter value for in_high (default=2.0)" /><field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">adc_bridge<field93 name="Enter value for in_low (default=1.0)" /><field94 name="Enter value for in_high (default=2.0)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /></u12><u17 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u17><u43 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u43><u16 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u16><u44 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u44><u18 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u18><u45 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u45><u28 name="type">d_and<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_and<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_and<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u30><u52 name="type">d_nand<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u52><u53 name="type">d_nand<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u53><u54 name="type">d_nand<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u54><u58 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u58><u20 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u20><u46 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u46><u19 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u19><u47 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u47><u21 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u21><u48 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u48><u32 name="type">d_and<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u32><u33 name="type">d_and<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u33><u42 name="type">d_and<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u42><u55 name="type">d_nand<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u55><u56 name="type">d_nand<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u56><u57 name="type">d_nand<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u57><u59 name="type">d_inverter<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u59><u26 name="type">d_inverter<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u26><u49 name="type">d_inverter<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u49><u25 name="type">d_inverter<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u25><u50 name="type">d_inverter<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u50><u27 name="type">d_inverter<field145 name="Enter Rise Delay (default=1.0e-9)" /><field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /></u27><u51 name="type">d_inverter<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u51></model><devicemodel /><subcircuit><x19><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x19><x22><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x22><x29><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x29><x30><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x30><x31><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x31><x32><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x32><x34><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x34><x25><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x25><x26><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x26><x27><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x27><x28><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x28><x33><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x33><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74ALS280/analysis b/library/SubcircuitLibrary/SN74ALS280/analysis new file mode 100644 index 00000000..cf94dd7f --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/3_and-cache.lib b/library/SubcircuitLibrary/SN74LS138/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS138/3_and.cir b/library/SubcircuitLibrary/SN74LS138/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS138/3_and.cir.out b/library/SubcircuitLibrary/SN74LS138/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS138/3_and.pro b/library/SubcircuitLibrary/SN74LS138/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74LS138/3_and.sch b/library/SubcircuitLibrary/SN74LS138/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS138/3_and.sub b/library/SubcircuitLibrary/SN74LS138/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS138/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/4_and-cache.lib b/library/SubcircuitLibrary/SN74LS138/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS138/4_and-rescue.lib b/library/SubcircuitLibrary/SN74LS138/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS138/4_and.cir b/library/SubcircuitLibrary/SN74LS138/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS138/4_and.cir.out b/library/SubcircuitLibrary/SN74LS138/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS138/4_and.pro b/library/SubcircuitLibrary/SN74LS138/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN74LS138/4_and.sch b/library/SubcircuitLibrary/SN74LS138/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS138/4_and.sub b/library/SubcircuitLibrary/SN74LS138/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS138/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138-cache.lib b/library/SubcircuitLibrary/SN74LS138/SN74LS138-cache.lib new file mode 100644 index 00000000..7a756fd1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138-cache.lib @@ -0,0 +1,95 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir b/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir new file mode 100644 index 00000000..9024ca93 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir @@ -0,0 +1,38 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS138\SN74LS138.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/18/24 15:20:33 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X2 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_X1-Pad4_ Net-_U19-Pad1_ 4_and +U19 Net-_U19-Pad1_ Net-_U1-Pad7_ d_inverter +X3 Net-_U16-Pad2_ Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_X1-Pad4_ Net-_U20-Pad1_ 4_and +U20 Net-_U20-Pad1_ Net-_U1-Pad8_ d_inverter +X4 Net-_U13-Pad2_ Net-_U17-Pad2_ Net-_U15-Pad2_ Net-_X1-Pad4_ Net-_U21-Pad1_ 4_and +U21 Net-_U21-Pad1_ Net-_U1-Pad9_ d_inverter +X5 Net-_U16-Pad2_ Net-_U17-Pad2_ Net-_U15-Pad2_ Net-_X1-Pad4_ Net-_U22-Pad1_ 4_and +U22 Net-_U22-Pad1_ Net-_U1-Pad10_ d_inverter +X6 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U18-Pad2_ Net-_X1-Pad4_ Net-_U23-Pad1_ 4_and +U23 Net-_U23-Pad1_ Net-_U1-Pad11_ d_inverter +X7 Net-_U14-Pad2_ Net-_U18-Pad2_ Net-_U16-Pad2_ Net-_X1-Pad4_ Net-_U24-Pad1_ 4_and +U24 Net-_U24-Pad1_ Net-_U1-Pad12_ d_inverter +X8 Net-_U13-Pad2_ Net-_U18-Pad2_ Net-_U17-Pad2_ Net-_X1-Pad4_ Net-_U25-Pad1_ 4_and +U25 Net-_U25-Pad1_ Net-_U1-Pad13_ d_inverter +X9 Net-_X1-Pad4_ Net-_U17-Pad2_ Net-_U16-Pad2_ Net-_U18-Pad2_ Net-_U26-Pad1_ 4_and +U26 Net-_U26-Pad1_ Net-_U1-Pad14_ d_inverter +U18 Net-_U15-Pad2_ Net-_U18-Pad2_ d_inverter +U17 Net-_U14-Pad2_ Net-_U17-Pad2_ d_inverter +U16 Net-_U13-Pad2_ Net-_U16-Pad2_ d_inverter +X1 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_X1-Pad4_ 3_and +U8 Net-_U1-Pad1_ Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U1-Pad2_ Net-_U11-Pad2_ d_inverter +U12 Net-_U1-Pad3_ Net-_U12-Pad2_ d_inverter +U13 Net-_U1-Pad4_ Net-_U13-Pad2_ d_inverter +U14 Net-_U1-Pad5_ Net-_U14-Pad2_ d_inverter +U15 Net-_U1-Pad6_ Net-_U15-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir.out b/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir.out new file mode 100644 index 00000000..4ffe8f81 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.cir.out @@ -0,0 +1,95 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls138\sn74ls138.cir + +.include 3_and.sub +.include 4_and.sub +x2 net-_u13-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u19-pad1_ 4_and +* u19 net-_u19-pad1_ net-_u1-pad7_ d_inverter +x3 net-_u16-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u20-pad1_ 4_and +* u20 net-_u20-pad1_ net-_u1-pad8_ d_inverter +x4 net-_u13-pad2_ net-_u17-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u21-pad1_ 4_and +* u21 net-_u21-pad1_ net-_u1-pad9_ d_inverter +x5 net-_u16-pad2_ net-_u17-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u22-pad1_ 4_and +* u22 net-_u22-pad1_ net-_u1-pad10_ d_inverter +x6 net-_u13-pad2_ net-_u14-pad2_ net-_u18-pad2_ net-_x1-pad4_ net-_u23-pad1_ 4_and +* u23 net-_u23-pad1_ net-_u1-pad11_ d_inverter +x7 net-_u14-pad2_ net-_u18-pad2_ net-_u16-pad2_ net-_x1-pad4_ net-_u24-pad1_ 4_and +* u24 net-_u24-pad1_ net-_u1-pad12_ d_inverter +x8 net-_u13-pad2_ net-_u18-pad2_ net-_u17-pad2_ net-_x1-pad4_ net-_u25-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u1-pad13_ d_inverter +x9 net-_x1-pad4_ net-_u17-pad2_ net-_u16-pad2_ net-_u18-pad2_ net-_u26-pad1_ 4_and +* u26 net-_u26-pad1_ net-_u1-pad14_ d_inverter +* u18 net-_u15-pad2_ net-_u18-pad2_ d_inverter +* u17 net-_u14-pad2_ net-_u17-pad2_ d_inverter +* u16 net-_u13-pad2_ net-_u16-pad2_ d_inverter +x1 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_x1-pad4_ 3_and +* u8 net-_u1-pad1_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad2_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad4_ net-_u13-pad2_ d_inverter +* u14 net-_u1-pad5_ net-_u14-pad2_ d_inverter +* u15 net-_u1-pad6_ net-_u15-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 net-_u19-pad1_ net-_u1-pad7_ u19 +a2 net-_u20-pad1_ net-_u1-pad8_ u20 +a3 net-_u21-pad1_ net-_u1-pad9_ u21 +a4 net-_u22-pad1_ net-_u1-pad10_ u22 +a5 net-_u23-pad1_ net-_u1-pad11_ u23 +a6 net-_u24-pad1_ net-_u1-pad12_ u24 +a7 net-_u25-pad1_ net-_u1-pad13_ u25 +a8 net-_u26-pad1_ net-_u1-pad14_ u26 +a9 net-_u15-pad2_ net-_u18-pad2_ u18 +a10 net-_u14-pad2_ net-_u17-pad2_ u17 +a11 net-_u13-pad2_ net-_u16-pad2_ u16 +a12 net-_u1-pad1_ net-_u10-pad1_ u8 +a13 net-_u10-pad1_ net-_u10-pad2_ u10 +a14 net-_u1-pad2_ net-_u11-pad2_ u11 +a15 net-_u1-pad3_ net-_u12-pad2_ u12 +a16 net-_u1-pad4_ net-_u13-pad2_ u13 +a17 net-_u1-pad5_ net-_u14-pad2_ u14 +a18 net-_u1-pad6_ net-_u15-pad2_ u15 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-03 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.pro b/library/SubcircuitLibrary/SN74LS138/SN74LS138.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.proj b/library/SubcircuitLibrary/SN74LS138/SN74LS138.proj new file mode 100644 index 00000000..7b1a94a1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.proj @@ -0,0 +1 @@ +schematicFile New.sch diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.sch b/library/SubcircuitLibrary/SN74LS138/SN74LS138.sch new file mode 100644 index 00000000..37a20de9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.sch @@ -0,0 +1,665 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74LS138-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4_and X2 +U 1 1 665D7644 +P 12650 5550 +F 0 "X2" H 12700 5500 60 0000 C CNN +F 1 "4_and" H 12750 5650 60 0000 C CNN +F 2 "" H 12650 5550 60 0000 C CNN +F 3 "" H 12650 5550 60 0000 C CNN + 1 12650 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 665D77DD +P 13450 5550 +F 0 "U19" H 13450 5450 60 0000 C CNN +F 1 "d_inverter" H 13450 5700 60 0000 C CNN +F 2 "" H 13500 5500 60 0000 C CNN +F 3 "" H 13500 5500 60 0000 C CNN + 1 13450 5550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X3 +U 1 1 665D79AA +P 12650 6050 +F 0 "X3" H 12700 6000 60 0000 C CNN +F 1 "4_and" H 12750 6150 60 0000 C CNN +F 2 "" H 12650 6050 60 0000 C CNN +F 3 "" H 12650 6050 60 0000 C CNN + 1 12650 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 665D79B0 +P 13450 6050 +F 0 "U20" H 13450 5950 60 0000 C CNN +F 1 "d_inverter" H 13450 6200 60 0000 C CNN +F 2 "" H 13500 6000 60 0000 C CNN +F 3 "" H 13500 6000 60 0000 C CNN + 1 13450 6050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X4 +U 1 1 665D7B32 +P 12650 6550 +F 0 "X4" H 12700 6500 60 0000 C CNN +F 1 "4_and" H 12750 6650 60 0000 C CNN +F 2 "" H 12650 6550 60 0000 C CNN +F 3 "" H 12650 6550 60 0000 C CNN + 1 12650 6550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 665D7B38 +P 13450 6550 +F 0 "U21" H 13450 6450 60 0000 C CNN +F 1 "d_inverter" H 13450 6700 60 0000 C CNN +F 2 "" H 13500 6500 60 0000 C CNN +F 3 "" H 13500 6500 60 0000 C CNN + 1 13450 6550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 665D7B3E +P 12650 7050 +F 0 "X5" H 12700 7000 60 0000 C CNN +F 1 "4_and" H 12750 7150 60 0000 C CNN +F 2 "" H 12650 7050 60 0000 C CNN +F 3 "" H 12650 7050 60 0000 C CNN + 1 12650 7050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 665D7B44 +P 13450 7050 +F 0 "U22" H 13450 6950 60 0000 C CNN +F 1 "d_inverter" H 13450 7200 60 0000 C CNN +F 2 "" H 13500 7000 60 0000 C CNN +F 3 "" H 13500 7000 60 0000 C CNN + 1 13450 7050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 665D7ED8 +P 12650 7550 +F 0 "X6" H 12700 7500 60 0000 C CNN +F 1 "4_and" H 12750 7650 60 0000 C CNN +F 2 "" H 12650 7550 60 0000 C CNN +F 3 "" H 12650 7550 60 0000 C CNN + 1 12650 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 665D7EDE +P 13450 7550 +F 0 "U23" H 13450 7450 60 0000 C CNN +F 1 "d_inverter" H 13450 7700 60 0000 C CNN +F 2 "" H 13500 7500 60 0000 C CNN +F 3 "" H 13500 7500 60 0000 C CNN + 1 13450 7550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 665D7EE4 +P 12650 8050 +F 0 "X7" H 12700 8000 60 0000 C CNN +F 1 "4_and" H 12750 8150 60 0000 C CNN +F 2 "" H 12650 8050 60 0000 C CNN +F 3 "" H 12650 8050 60 0000 C CNN + 1 12650 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 665D7EEA +P 13450 8050 +F 0 "U24" H 13450 7950 60 0000 C CNN +F 1 "d_inverter" H 13450 8200 60 0000 C CNN +F 2 "" H 13500 8000 60 0000 C CNN +F 3 "" H 13500 8000 60 0000 C CNN + 1 13450 8050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X8 +U 1 1 665D7EF0 +P 12650 8550 +F 0 "X8" H 12700 8500 60 0000 C CNN +F 1 "4_and" H 12750 8650 60 0000 C CNN +F 2 "" H 12650 8550 60 0000 C CNN +F 3 "" H 12650 8550 60 0000 C CNN + 1 12650 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 665D7EF6 +P 13450 8550 +F 0 "U25" H 13450 8450 60 0000 C CNN +F 1 "d_inverter" H 13450 8700 60 0000 C CNN +F 2 "" H 13500 8500 60 0000 C CNN +F 3 "" H 13500 8500 60 0000 C CNN + 1 13450 8550 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X9 +U 1 1 665D7EFC +P 12650 9050 +F 0 "X9" H 12700 9000 60 0000 C CNN +F 1 "4_and" H 12750 9150 60 0000 C CNN +F 2 "" H 12650 9050 60 0000 C CNN +F 3 "" H 12650 9050 60 0000 C CNN + 1 12650 9050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U26 +U 1 1 665D7F02 +P 13450 9050 +F 0 "U26" H 13450 8950 60 0000 C CNN +F 1 "d_inverter" H 13450 9200 60 0000 C CNN +F 2 "" H 13500 9000 60 0000 C CNN +F 3 "" H 13500 9000 60 0000 C CNN + 1 13450 9050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 665D879A +P 10400 9200 +F 0 "U18" H 10400 9100 60 0000 C CNN +F 1 "d_inverter" H 10400 9350 60 0000 C CNN +F 2 "" H 10450 9150 60 0000 C CNN +F 3 "" H 10450 9150 60 0000 C CNN + 1 10400 9200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 665D8853 +P 10400 8600 +F 0 "U17" H 10400 8500 60 0000 C CNN +F 1 "d_inverter" H 10400 8750 60 0000 C CNN +F 2 "" H 10450 8550 60 0000 C CNN +F 3 "" H 10450 8550 60 0000 C CNN + 1 10400 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 665D88B9 +P 10400 8100 +F 0 "U16" H 10400 8000 60 0000 C CNN +F 1 "d_inverter" H 10400 8250 60 0000 C CNN +F 2 "" H 10450 8050 60 0000 C CNN +F 3 "" H 10450 8050 60 0000 C CNN + 1 10400 8100 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 665D95DE +P 8550 6750 +F 0 "X1" H 8650 6700 60 0000 C CNN +F 1 "3_and" H 8700 6900 60 0000 C CNN +F 2 "" H 8550 6750 60 0000 C CNN +F 3 "" H 8550 6750 60 0000 C CNN + 1 8550 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 665D96C5 +P 7050 6600 +F 0 "U8" H 7050 6500 60 0000 C CNN +F 1 "d_inverter" H 7050 6750 60 0000 C CNN +F 2 "" H 7100 6550 60 0000 C CNN +F 3 "" H 7100 6550 60 0000 C CNN + 1 7050 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 665D979E +P 7900 6600 +F 0 "U10" H 7650 6900 60 0000 C CNN +F 1 "d_inverter" H 7950 6900 60 0000 C CNN +F 2 "" H 7950 6550 60 0000 C CNN +F 3 "" H 7950 6550 60 0000 C CNN + 1 7900 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 665D981E +P 7900 6700 +F 0 "U11" H 7650 7000 60 0000 C CNN +F 1 "d_inverter" H 7950 7000 60 0000 C CNN +F 2 "" H 7950 6650 60 0000 C CNN +F 3 "" H 7950 6650 60 0000 C CNN + 1 7900 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 665D9873 +P 7900 6800 +F 0 "U12" H 7650 7100 60 0000 C CNN +F 1 "d_inverter" H 7950 7100 60 0000 C CNN +F 2 "" H 7950 6750 60 0000 C CNN +F 3 "" H 7950 6750 60 0000 C CNN + 1 7900 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 665D9DBA +P 9200 8100 +F 0 "U13" H 9200 8000 60 0000 C CNN +F 1 "d_inverter" H 9200 8250 60 0000 C CNN +F 2 "" H 9250 8050 60 0000 C CNN +F 3 "" H 9250 8050 60 0000 C CNN + 1 9200 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 665D9E3F +P 9200 8600 +F 0 "U14" H 9200 8500 60 0000 C CNN +F 1 "d_inverter" H 9200 8750 60 0000 C CNN +F 2 "" H 9250 8550 60 0000 C CNN +F 3 "" H 9250 8550 60 0000 C CNN + 1 9200 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 665D9EAF +P 9200 9200 +F 0 "U15" H 9200 9100 60 0000 C CNN +F 1 "d_inverter" H 9200 9350 60 0000 C CNN +F 2 "" H 9250 9150 60 0000 C CNN +F 3 "" H 9250 9150 60 0000 C CNN + 1 9200 9200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12250 5400 9500 5400 +Wire Wire Line + 9500 5400 9500 8400 +Wire Wire Line + 9500 8400 12250 8400 +Wire Wire Line + 12250 5700 12050 5700 +Wire Wire Line + 12050 5700 12050 8900 +Wire Wire Line + 12250 8200 12050 8200 +Connection ~ 12050 8200 +Wire Wire Line + 12250 7700 12050 7700 +Connection ~ 12050 7700 +Wire Wire Line + 12250 8700 12050 8700 +Connection ~ 12050 8700 +Wire Wire Line + 12250 7200 12050 7200 +Connection ~ 12050 7200 +Wire Wire Line + 9050 6700 12250 6700 +Connection ~ 12050 6700 +Wire Wire Line + 12250 6200 12050 6200 +Connection ~ 12050 6200 +Wire Wire Line + 10750 9100 12250 9100 +Wire Wire Line + 10750 5900 10750 9100 +Wire Wire Line + 10750 5900 12250 5900 +Wire Wire Line + 9500 9200 10100 9200 +Wire Wire Line + 9900 5600 9900 9200 +Wire Wire Line + 9900 5600 12250 5600 +Wire Wire Line + 12250 5500 9650 5500 +Wire Wire Line + 9650 5500 9650 8600 +Wire Wire Line + 9500 8600 10100 8600 +Wire Wire Line + 10100 8100 9500 8100 +Connection ~ 9500 8100 +Wire Wire Line + 10700 8600 12250 8600 +Wire Wire Line + 10700 8100 12250 8100 +Wire Wire Line + 12250 6000 9650 6000 +Connection ~ 9650 6000 +Wire Wire Line + 12250 6100 9900 6100 +Connection ~ 9900 6100 +Wire Wire Line + 12250 6400 9500 6400 +Connection ~ 9500 6400 +Wire Wire Line + 12250 6500 11050 6500 +Wire Wire Line + 11050 6500 11050 9000 +Wire Wire Line + 11050 7000 12250 7000 +Wire Wire Line + 12250 6900 10750 6900 +Connection ~ 10750 6900 +Wire Wire Line + 12250 6600 9900 6600 +Connection ~ 9900 6600 +Wire Wire Line + 12250 7100 9900 7100 +Connection ~ 9900 7100 +Wire Wire Line + 12250 7400 9500 7400 +Connection ~ 9500 7400 +Wire Wire Line + 12250 7500 9650 7500 +Connection ~ 9650 7500 +Wire Wire Line + 12250 7600 11600 7600 +Wire Wire Line + 11600 7600 11600 9200 +Wire Wire Line + 11600 8000 12250 8000 +Wire Wire Line + 12250 7900 9650 7900 +Connection ~ 9650 7900 +Wire Wire Line + 11600 8500 12250 8500 +Connection ~ 11600 8000 +Wire Wire Line + 12050 8900 12250 8900 +Connection ~ 12050 8900 +Wire Wire Line + 10700 9200 12250 9200 +Connection ~ 11600 9200 +Connection ~ 11600 8500 +Connection ~ 11050 8600 +Connection ~ 11050 7000 +Wire Wire Line + 11050 9000 12250 9000 +Connection ~ 10750 8100 +Wire Wire Line + 7350 6600 7600 6600 +Connection ~ 9650 8600 +Wire Wire Line + 6750 6700 7600 6700 +Wire Wire Line + 7600 6800 6750 6800 +Wire Wire Line + 14400 6950 14400 5550 +Wire Wire Line + 14400 5550 13750 5550 +Wire Wire Line + 13750 6050 14250 6050 +Wire Wire Line + 14250 6050 14250 7050 +Wire Wire Line + 14250 7050 14400 7050 +Wire Wire Line + 13750 6550 14100 6550 +Wire Wire Line + 14100 6550 14100 7150 +Wire Wire Line + 14100 7150 14400 7150 +Wire Wire Line + 14400 7250 13750 7250 +Wire Wire Line + 13750 7250 13750 7050 +Wire Wire Line + 13750 7350 13750 7550 +Wire Wire Line + 13750 7350 14400 7350 +Wire Wire Line + 14400 7450 13850 7450 +Wire Wire Line + 13850 7450 13850 8050 +Wire Wire Line + 13850 8050 13750 8050 +Wire Wire Line + 13750 8550 14000 8550 +Wire Wire Line + 14000 8550 14000 7550 +Wire Wire Line + 14000 7550 14400 7550 +Wire Wire Line + 14400 7650 14200 7650 +Wire Wire Line + 14200 7650 14200 9050 +Wire Wire Line + 14200 9050 13750 9050 +Connection ~ 9900 9200 +$Comp +L PORT U1 +U 7 1 665D9B14 +P 14650 6950 +F 0 "U1" H 14700 7050 30 0000 C CNN +F 1 "PORT" H 14650 6950 30 0000 C CNN +F 2 "" H 14650 6950 60 0000 C CNN +F 3 "" H 14650 6950 60 0000 C CNN + 7 14650 6950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 665D9CEE +P 14650 7050 +F 0 "U1" H 14700 7150 30 0000 C CNN +F 1 "PORT" H 14650 7050 30 0000 C CNN +F 2 "" H 14650 7050 60 0000 C CNN +F 3 "" H 14650 7050 60 0000 C CNN + 8 14650 7050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 665D9D71 +P 14650 7150 +F 0 "U1" H 14700 7250 30 0000 C CNN +F 1 "PORT" H 14650 7150 30 0000 C CNN +F 2 "" H 14650 7150 60 0000 C CNN +F 3 "" H 14650 7150 60 0000 C CNN + 9 14650 7150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 665D9DE6 +P 14650 7250 +F 0 "U1" H 14700 7350 30 0000 C CNN +F 1 "PORT" H 14650 7250 30 0000 C CNN +F 2 "" H 14650 7250 60 0000 C CNN +F 3 "" H 14650 7250 60 0000 C CNN + 10 14650 7250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 665D9E5B +P 14650 7350 +F 0 "U1" H 14700 7450 30 0000 C CNN +F 1 "PORT" H 14650 7350 30 0000 C CNN +F 2 "" H 14650 7350 60 0000 C CNN +F 3 "" H 14650 7350 60 0000 C CNN + 11 14650 7350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 665D9ED2 +P 14650 7450 +F 0 "U1" H 14700 7550 30 0000 C CNN +F 1 "PORT" H 14650 7450 30 0000 C CNN +F 2 "" H 14650 7450 60 0000 C CNN +F 3 "" H 14650 7450 60 0000 C CNN + 12 14650 7450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 665D9F4B +P 14650 7550 +F 0 "U1" H 14700 7650 30 0000 C CNN +F 1 "PORT" H 14650 7550 30 0000 C CNN +F 2 "" H 14650 7550 60 0000 C CNN +F 3 "" H 14650 7550 60 0000 C CNN + 13 14650 7550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 665D9FC6 +P 14650 7650 +F 0 "U1" H 14700 7750 30 0000 C CNN +F 1 "PORT" H 14650 7650 30 0000 C CNN +F 2 "" H 14650 7650 60 0000 C CNN +F 3 "" H 14650 7650 60 0000 C CNN + 14 14650 7650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 665DB37C +P 6500 6600 +F 0 "U1" H 6550 6700 30 0000 C CNN +F 1 "PORT" H 6500 6600 30 0000 C CNN +F 2 "" H 6500 6600 60 0000 C CNN +F 3 "" H 6500 6600 60 0000 C CNN + 1 6500 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 665DB3FD +P 6500 6700 +F 0 "U1" H 6550 6800 30 0000 C CNN +F 1 "PORT" H 6500 6700 30 0000 C CNN +F 2 "" H 6500 6700 60 0000 C CNN +F 3 "" H 6500 6700 60 0000 C CNN + 2 6500 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 665DB46C +P 6500 6800 +F 0 "U1" H 6550 6900 30 0000 C CNN +F 1 "PORT" H 6500 6800 30 0000 C CNN +F 2 "" H 6500 6800 60 0000 C CNN +F 3 "" H 6500 6800 60 0000 C CNN + 3 6500 6800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 665DB971 +P 8650 8100 +F 0 "U1" H 8700 8200 30 0000 C CNN +F 1 "PORT" H 8650 8100 30 0000 C CNN +F 2 "" H 8650 8100 60 0000 C CNN +F 3 "" H 8650 8100 60 0000 C CNN + 4 8650 8100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 665DB9EA +P 8650 8600 +F 0 "U1" H 8700 8700 30 0000 C CNN +F 1 "PORT" H 8650 8600 30 0000 C CNN +F 2 "" H 8650 8600 60 0000 C CNN +F 3 "" H 8650 8600 60 0000 C CNN + 5 8650 8600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 665DBA59 +P 8650 9200 +F 0 "U1" H 8700 9300 30 0000 C CNN +F 1 "PORT" H 8650 9200 30 0000 C CNN +F 2 "" H 8650 9200 60 0000 C CNN +F 3 "" H 8650 9200 60 0000 C CNN + 6 8650 9200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138.sub b/library/SubcircuitLibrary/SN74LS138/SN74LS138.sub new file mode 100644 index 00000000..58836a60 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138.sub @@ -0,0 +1,89 @@ +* Subcircuit SN74LS138 +.subckt SN74LS138 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls138\sn74ls138.cir +.include 3_and.sub +.include 4_and.sub +x2 net-_u13-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u19-pad1_ 4_and +* u19 net-_u19-pad1_ net-_u1-pad7_ d_inverter +x3 net-_u16-pad2_ net-_u14-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u20-pad1_ 4_and +* u20 net-_u20-pad1_ net-_u1-pad8_ d_inverter +x4 net-_u13-pad2_ net-_u17-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u21-pad1_ 4_and +* u21 net-_u21-pad1_ net-_u1-pad9_ d_inverter +x5 net-_u16-pad2_ net-_u17-pad2_ net-_u15-pad2_ net-_x1-pad4_ net-_u22-pad1_ 4_and +* u22 net-_u22-pad1_ net-_u1-pad10_ d_inverter +x6 net-_u13-pad2_ net-_u14-pad2_ net-_u18-pad2_ net-_x1-pad4_ net-_u23-pad1_ 4_and +* u23 net-_u23-pad1_ net-_u1-pad11_ d_inverter +x7 net-_u14-pad2_ net-_u18-pad2_ net-_u16-pad2_ net-_x1-pad4_ net-_u24-pad1_ 4_and +* u24 net-_u24-pad1_ net-_u1-pad12_ d_inverter +x8 net-_u13-pad2_ net-_u18-pad2_ net-_u17-pad2_ net-_x1-pad4_ net-_u25-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u1-pad13_ d_inverter +x9 net-_x1-pad4_ net-_u17-pad2_ net-_u16-pad2_ net-_u18-pad2_ net-_u26-pad1_ 4_and +* u26 net-_u26-pad1_ net-_u1-pad14_ d_inverter +* u18 net-_u15-pad2_ net-_u18-pad2_ d_inverter +* u17 net-_u14-pad2_ net-_u17-pad2_ d_inverter +* u16 net-_u13-pad2_ net-_u16-pad2_ d_inverter +x1 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_x1-pad4_ 3_and +* u8 net-_u1-pad1_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad2_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter +* u13 net-_u1-pad4_ net-_u13-pad2_ d_inverter +* u14 net-_u1-pad5_ net-_u14-pad2_ d_inverter +* u15 net-_u1-pad6_ net-_u15-pad2_ d_inverter +a1 net-_u19-pad1_ net-_u1-pad7_ u19 +a2 net-_u20-pad1_ net-_u1-pad8_ u20 +a3 net-_u21-pad1_ net-_u1-pad9_ u21 +a4 net-_u22-pad1_ net-_u1-pad10_ u22 +a5 net-_u23-pad1_ net-_u1-pad11_ u23 +a6 net-_u24-pad1_ net-_u1-pad12_ u24 +a7 net-_u25-pad1_ net-_u1-pad13_ u25 +a8 net-_u26-pad1_ net-_u1-pad14_ u26 +a9 net-_u15-pad2_ net-_u18-pad2_ u18 +a10 net-_u14-pad2_ net-_u17-pad2_ u17 +a11 net-_u13-pad2_ net-_u16-pad2_ u16 +a12 net-_u1-pad1_ net-_u10-pad1_ u8 +a13 net-_u10-pad1_ net-_u10-pad2_ u10 +a14 net-_u1-pad2_ net-_u11-pad2_ u11 +a15 net-_u1-pad3_ net-_u12-pad2_ u12 +a16 net-_u1-pad4_ net-_u13-pad2_ u13 +a17 net-_u1-pad5_ net-_u14-pad2_ u14 +a18 net-_u1-pad6_ net-_u15-pad2_ u15 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS138
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/SN74LS138_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS138/SN74LS138_Previous_Values.xml new file mode 100644 index 00000000..6947b376 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/SN74LS138_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v6 name="Source type">dc<field1 name="Value">0</field1></v6></source><model><u19 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u26><u18 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u18><u17 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u17><u16 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u16><u8 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u8><u10 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u15><u7 name="type">adc_bridge<field55 name="Enter value for in_low (default=1.0)" /><field56 name="Enter value for in_high (default=2.0)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /><field58 name="Enter Fall Delay (default=1.0e-9)" /></u7><u9 name="type">adc_bridge<field59 name="Enter value for in_low (default=1.0)" /><field60 name="Enter value for in_high (default=2.0)" /><field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /></u9><u27 name="type">dac_bridge<field63 name="Enter value for out_low (default=0.0)" /><field64 name="Enter value for out_high (default=5.0)" /><field65 name="Enter value for out_undef (default=0.5)" /><field66 name="Enter value for input load (default=1.0e-12)" /><field67 name="Enter the Rise Time (default=1.0e-9)" /><field68 name="Enter the Fall Time (default=1.0e-9)" /></u27></model><devicemodel /><subcircuit><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x8><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x9><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS138/analysis b/library/SubcircuitLibrary/SN74LS138/analysis new file mode 100644 index 00000000..cf94dd7f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS138/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-00 0e-00
\ No newline at end of file |