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authorSumanto Kar2024-11-21 22:09:07 +0530
committerGitHub2024-11-21 22:09:07 +0530
commitc7f8a75e51d3c79aaa994b25849bcb358543f12c (patch)
treee0164ce8ed66b4b6d26fb522b37daed7d3d14dde /library/SubcircuitLibrary/SN74ALS280/4_and.cir
parent5aa4943922ff5af9bbb840782aaf26e72de40576 (diff)
parent8e6fb624fda240239f9bfff67b40c28fba44e744 (diff)
downloadeSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.tar.gz
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Merge pull request #289 from Eyantra698Sumanto/master
Subcircuit Files of ICs(Contributor: Varad Patil)
Diffstat (limited to 'library/SubcircuitLibrary/SN74ALS280/4_and.cir')
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+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end