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| author | Sumanto Kar | 2024-11-21 22:09:07 +0530 |
|---|---|---|
| committer | GitHub | 2024-11-21 22:09:07 +0530 |
| commit | c7f8a75e51d3c79aaa994b25849bcb358543f12c (patch) | |
| tree | e0164ce8ed66b4b6d26fb522b37daed7d3d14dde /library/SubcircuitLibrary/SN74ALS280/4_OR.sub | |
| parent | 5aa4943922ff5af9bbb840782aaf26e72de40576 (diff) | |
| parent | 8e6fb624fda240239f9bfff67b40c28fba44e744 (diff) | |
| download | eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.tar.gz eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.tar.bz2 eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.zip | |
Merge pull request #289 from Eyantra698Sumanto/master
Subcircuit Files of ICs(Contributor: Varad Patil)
Diffstat (limited to 'library/SubcircuitLibrary/SN74ALS280/4_OR.sub')
| -rw-r--r-- | library/SubcircuitLibrary/SN74ALS280/4_OR.sub | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.sub b/library/SubcircuitLibrary/SN74ALS280/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
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