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authorSumanto Kar2024-11-21 21:32:11 +0530
committerSumanto Kar2024-11-21 21:32:11 +0530
commit5338d6a340e0fb746bcfa9b6184ee884c45ff44b (patch)
treec4b0621e144cb400c8f32b92c0a1b9273281954a /library/SubcircuitLibrary/SN74ALS280/3_and.sub
parent2e48868406e15598a8986e12fc95396c6baa7d1f (diff)
downloadeSim-5338d6a340e0fb746bcfa9b6184ee884c45ff44b.tar.gz
eSim-5338d6a340e0fb746bcfa9b6184ee884c45ff44b.tar.bz2
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SN74ALS280 is a parity generator/checker
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+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and \ No newline at end of file