SN74ALS280 is a parity generator/checker

40 files changed, 3423 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and-cache.lib b/library/SubcircuitLibrary/SN74ALS280/3_and-cache.lib
new file mode 100644
index 00000000..af058641
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.cir b/library/SubcircuitLibrary/SN74ALS280/3_and.cir
new file mode 100644
index 00000000..ba296cf0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.cir.out b/library/SubcircuitLibrary/SN74ALS280/3_and.cir.out
new file mode 100644
index 00000000..d7cf79a0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.pro b/library/SubcircuitLibrary/SN74ALS280/3_and.pro
new file mode 100644
index 00000000..06813ca7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 19:54:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.sch b/library/SubcircuitLibrary/SN74ALS280/3_and.sch
new file mode 100644
index 00000000..d6ac89f9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and.sub b/library/SubcircuitLibrary/SN74ALS280/3_and.sub
new file mode 100644
index 00000000..3d9120bb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS280/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS280/3_and_Previous_Values.xml
new file mode 100644
index 00000000..abc5faaa
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR-cache.lib b/library/SubcircuitLibrary/SN74ALS280/4_OR-cache.lib
new file mode 100644
index 00000000..155f5e60
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.cir b/library/SubcircuitLibrary/SN74ALS280/4_OR.cir
new file mode 100644
index 00000000..b338b7b5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or		
+U3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
+U4  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.cir.out b/library/SubcircuitLibrary/SN74ALS280/4_OR.cir.out
new file mode 100644
index 00000000..adb6b01b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.pro b/library/SubcircuitLibrary/SN74ALS280/4_OR.pro
new file mode 100644
index 00000000..881563eb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.pro
@@ -0,0 +1,44 @@
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.sch b/library/SubcircuitLibrary/SN74ALS280/4_OR.sch
new file mode 100644
index 00000000..11896865
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60  0000 C CNN
+F 1 "d_or" H 4300 3050 60  0000 C CNN
+F 2 "" H 4300 2950 60  0000 C CNN
+F 3 "" H 4300 2950 60  0000 C CNN
+	1    4300 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60  0000 C CNN
+F 1 "d_or" H 4300 3450 60  0000 C CNN
+F 2 "" H 4300 3350 60  0000 C CNN
+F 3 "" H 4300 3350 60  0000 C CNN
+	1    4300 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60  0000 C CNN
+F 1 "d_or" H 5250 3250 60  0000 C CNN
+F 2 "" H 5250 3150 60  0000 C CNN
+F 3 "" H 5250 3150 60  0000 C CNN
+	1    5250 3150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4800 3050 4800 2900
+Wire Wire Line
+	4800 2900 4750 2900
+Wire Wire Line
+	4800 3150 4800 3300
+Wire Wire Line
+	4800 3300 4750 3300
+Wire Wire Line
+	3350 2850 3850 2850
+Wire Wire Line
+	3850 2950 3600 2950
+Wire Wire Line
+	3850 3250 3350 3250
+Wire Wire Line
+	3600 2950 3600 3000
+Wire Wire Line
+	3600 3000 3350 3000
+Wire Wire Line
+	3850 3350 3850 3400
+Wire Wire Line
+	3850 3400 3350 3400
+Wire Wire Line
+	5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30  0000 C CNN
+F 1 "PORT" H 3100 2850 30  0000 C CNN
+F 2 "" H 3100 2850 60  0000 C CNN
+F 3 "" H 3100 2850 60  0000 C CNN
+	1    3100 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30  0000 C CNN
+F 1 "PORT" H 3100 3000 30  0000 C CNN
+F 2 "" H 3100 3000 60  0000 C CNN
+F 3 "" H 3100 3000 60  0000 C CNN
+	2    3100 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30  0000 C CNN
+F 1 "PORT" H 3100 3250 30  0000 C CNN
+F 2 "" H 3100 3250 60  0000 C CNN
+F 3 "" H 3100 3250 60  0000 C CNN
+	3    3100 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30  0000 C CNN
+F 1 "PORT" H 3100 3400 30  0000 C CNN
+F 2 "" H 3100 3400 60  0000 C CNN
+F 3 "" H 3100 3400 60  0000 C CNN
+	4    3100 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30  0000 C CNN
+F 1 "PORT" H 6450 3100 30  0000 C CNN
+F 2 "" H 6450 3100 60  0000 C CNN
+F 3 "" H 6450 3100 60  0000 C CNN
+	5    6450 3100
+	-1   0    0    1   
+$EndComp
+Text Notes 3450 2850 0    60   ~ 12
+in1
+Text Notes 3450 3000 0    60   ~ 12
+in2
+Text Notes 3450 3250 0    60   ~ 12
+in3
+Text Notes 3450 3400 0    60   ~ 12
+in4
+Text Notes 5800 3100 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR.sub b/library/SubcircuitLibrary/SN74ALS280/4_OR.sub
new file mode 100644
index 00000000..d1fd3a24
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3  net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS280/4_OR_Previous_Values.xml
new file mode 100644
index 00000000..0683d9eb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and-cache.lib b/library/SubcircuitLibrary/SN74ALS280/4_and-cache.lib
new file mode 100644
index 00000000..60f1a83d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and-rescue.lib b/library/SubcircuitLibrary/SN74ALS280/4_and-rescue.lib
new file mode 100644
index 00000000..e3833051
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0  650 550  1000 550 N
+P 3 0 1 0  650 550  650 250  1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.cir b/library/SubcircuitLibrary/SN74ALS280/4_and.cir
new file mode 100644
index 00000000..fdf2e107
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and		
+U2  Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.cir.out b/library/SubcircuitLibrary/SN74ALS280/4_and.cir.out
new file mode 100644
index 00000000..f40e5bc6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.pro b/library/SubcircuitLibrary/SN74ALS280/4_and.pro
new file mode 100644
index 00000000..b13a0a82
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.sch b/library/SubcircuitLibrary/SN74ALS280/4_and.sch
new file mode 100644
index 00000000..f5e8febd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60  0000 C CNN
+F 1 "3_and" H 4650 4000 60  0000 C CNN
+F 2 "" H 3700 3500 60  0000 C CNN
+F 3 "" H 3700 3500 60  0000 C CNN
+	1    3700 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60  0000 C CNN
+F 1 "d_and" H 5500 3500 60  0000 C CNN
+F 2 "" H 5450 3400 60  0000 C CNN
+F 3 "" H 5450 3400 60  0000 C CNN
+	1    5450 3400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5000 3100 5000 3300
+Wire Wire Line
+	4150 3000 4150 2700
+Wire Wire Line
+	4150 2700 3200 2700
+Wire Wire Line
+	4150 3100 4000 3100
+Wire Wire Line
+	4000 3100 4000 3000
+Wire Wire Line
+	4000 3000 3200 3000
+Wire Wire Line
+	4150 3200 4150 3300
+Wire Wire Line
+	4150 3300 3250 3300
+Wire Wire Line
+	5000 3400 5000 3550
+Wire Wire Line
+	5000 3550 3250 3550
+Wire Wire Line
+	5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30  0000 C CNN
+F 1 "PORT" H 2950 2700 30  0000 C CNN
+F 2 "" H 2950 2700 60  0000 C CNN
+F 3 "" H 2950 2700 60  0000 C CNN
+	1    2950 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30  0000 C CNN
+F 1 "PORT" H 2950 3000 30  0000 C CNN
+F 2 "" H 2950 3000 60  0000 C CNN
+F 3 "" H 2950 3000 60  0000 C CNN
+	2    2950 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30  0000 C CNN
+F 1 "PORT" H 3000 3300 30  0000 C CNN
+F 2 "" H 3000 3300 60  0000 C CNN
+F 3 "" H 3000 3300 60  0000 C CNN
+	3    3000 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30  0000 C CNN
+F 1 "PORT" H 3000 3550 30  0000 C CNN
+F 2 "" H 3000 3550 60  0000 C CNN
+F 3 "" H 3000 3550 60  0000 C CNN
+	4    3000 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30  0000 C CNN
+F 1 "PORT" H 6750 3350 30  0000 C CNN
+F 2 "" H 6750 3350 60  0000 C CNN
+F 3 "" H 6750 3350 60  0000 C CNN
+	5    6750 3350
+	-1   0    0    1   
+$EndComp
+Text Notes 3450 2650 0    60   ~ 12
+in1
+Text Notes 3450 2950 0    60   ~ 12
+in2
+Text Notes 3500 3300 0    60   ~ 12
+in3
+Text Notes 3500 3550 0    60   ~ 12
+in4
+Text Notes 6150 3350 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and.sub b/library/SubcircuitLibrary/SN74ALS280/4_and.sub
new file mode 100644
index 00000000..8663f37e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ 
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2  net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS280/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS280/4_and_Previous_Values.xml
new file mode 100644
index 00000000..f2ba0130
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS-cache.lib b/library/SubcircuitLibrary/SN74ALS280/INVCMOS-cache.lib
new file mode 100644
index 00000000..cc25b0c9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS-cache.lib
@@ -0,0 +1,146 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir
new file mode 100644
index 00000000..44f1df81
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir
@@ -0,0 +1,15 @@
+* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1  Net-_M1-Pad2_ Net-_C1-Pad1_ PORT		
+M1  Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N		
+M2  Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P		
+v1  Net-_M2-Pad1_ GND 5		
+C1  Net-_C1-Pad1_ GND 1u		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir.out b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir.out
new file mode 100644
index 00000000..cb2b6641
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.cir.out
@@ -0,0 +1,18 @@
+* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+* u1  net-_m1-pad2_ net-_c1-pad1_ port
+m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+v1  net-_m2-pad1_ gnd 5
+c1  net-_c1-pad1_ gnd 1u
+.tran 0e-03 0e-03 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS.pro b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.pro
new file mode 100644
index 00000000..81bd9ad4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.pro
@@ -0,0 +1,70 @@
+update=Sun Aug 25 15:54:56 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Subckt
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_Plot
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_User
+
diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sch b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sch
new file mode 100644
index 00000000..13a7fc09
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sch
@@ -0,0 +1,189 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+LIBS:eSim_Subckt
+LIBS:INVCMOS-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "29 apr 2015"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	5900 4000 5900 4150
+Connection ~ 5800 2450
+Connection ~ 5800 4150
+Wire Wire Line
+	5900 4150 5800 4150
+Connection ~ 5050 3350
+Wire Wire Line
+	4000 3350 5050 3350
+Wire Wire Line
+	5050 3850 5500 3850
+Wire Wire Line
+	5050 2700 5050 3850
+Wire Wire Line
+	5050 2700 5500 2700
+Wire Wire Line
+	5800 3650 5800 2900
+Wire Wire Line
+	5800 2500 5800 2300
+Connection ~ 4200 3350
+$Comp
+L PORT U1
+U 1 1 5D6263BC
+P 3750 3350
+F 0 "U1" H 3800 3450 30  0000 C CNN
+F 1 "PORT" H 3750 3350 30  0000 C CNN
+F 2 "" H 3750 3350 60  0000 C CNN
+F 3 "" H 3750 3350 60  0000 C CNN
+	1    3750 3350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6050 3250 5800 3250
+Connection ~ 5800 3250
+Wire Wire Line
+	5800 4050 5800 4550
+$Comp
+L eSim_MOS_N M1
+U 1 1 5D6265DB
+P 5600 3650
+F 0 "M1" H 5600 3500 50  0000 R CNN
+F 1 "eSim_MOS_N" H 5700 3600 50  0000 R CNN
+F 2 "" H 5900 3350 29  0000 C CNN
+F 3 "" H 5700 3450 60  0000 C CNN
+	1    5600 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_MOS_P M2
+U 1 1 5D626659
+P 5650 2700
+F 0 "M2" H 5600 2750 50  0000 R CNN
+F 1 "eSim_MOS_P" H 5700 2850 50  0000 R CNN
+F 2 "" H 5900 2800 29  0000 C CNN
+F 3 "" H 5700 2700 60  0000 C CNN
+	1    5650 2700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5900 2850 6050 2850
+Wire Wire Line
+	6050 2850 6050 2450
+Wire Wire Line
+	6050 2450 5800 2450
+Connection ~ 6000 3250
+Connection ~ 5800 4300
+$Comp
+L GND #PWR1
+U 1 1 5D626C59
+P 5800 4550
+F 0 "#PWR1" H 5800 4300 50  0001 C CNN
+F 1 "GND" H 5800 4400 50  0000 C CNN
+F 2 "" H 5800 4550 50  0001 C CNN
+F 3 "" H 5800 4550 50  0001 C CNN
+	1    5800 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v1
+U 1 1 5D626C7F
+P 6250 2300
+F 0 "v1" H 6050 2400 60  0000 C CNN
+F 1 "5" H 6050 2250 60  0000 C CNN
+F 2 "R1" H 5950 2300 60  0000 C CNN
+F 3 "" H 6250 2300 60  0000 C CNN
+	1    6250 2300
+	0    -1   -1   0   
+$EndComp
+$Comp
+L GND #PWR2
+U 1 1 5D626CF6
+P 6850 2300
+F 0 "#PWR2" H 6850 2050 50  0001 C CNN
+F 1 "GND" H 6850 2150 50  0000 C CNN
+F 2 "" H 6850 2300 50  0001 C CNN
+F 3 "" H 6850 2300 50  0001 C CNN
+	1    6850 2300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6850 2300 6700 2300
+$Comp
+L PORT U1
+U 2 1 5D626DCB
+P 6300 3250
+F 0 "U1" H 6350 3350 30  0000 C CNN
+F 1 "PORT" H 6300 3250 30  0000 C CNN
+F 2 "" H 6300 3250 60  0000 C CNN
+F 3 "" H 6300 3250 60  0000 C CNN
+	2    6300 3250
+	-1   0    0    1   
+$EndComp
+$Comp
+L eSim_C C1
+U 1 1 5D62796C
+P 6050 3850
+F 0 "C1" H 6075 3950 50  0000 L CNN
+F 1 "1u" H 6075 3750 50  0000 L CNN
+F 2 "" H 6088 3700 30  0000 C CNN
+F 3 "" H 6050 3850 60  0000 C CNN
+	1    6050 3850
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6050 3700 6050 3400
+Wire Wire Line
+	6050 3400 6000 3400
+Wire Wire Line
+	6000 3400 6000 3250
+Wire Wire Line
+	6050 4000 6050 4300
+Wire Wire Line
+	6050 4300 5800 4300
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sub b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sub
new file mode 100644
index 00000000..2319995c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS.sub
@@ -0,0 +1,12 @@
+* Subcircuit INVCMOS
+.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ 
+* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+v1  net-_m2-pad1_ gnd 5
+c1  net-_c1-pad1_ gnd 1u
+* Control Statements
+
+.ends INVCMOS
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS280/INVCMOS_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS280/INVCMOS_Previous_Values.xml
new file mode 100644
index 00000000..e5bb98c7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/INVCMOS_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS280/NMOS-180nm.lib b/library/SubcircuitLibrary/SN74ALS280/NMOS-180nm.lib
new file mode 100644
index 00000000..51e9b119
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/SN74ALS280/PMOS-180nm.lib b/library/SubcircuitLibrary/SN74ALS280/PMOS-180nm.lib
new file mode 100644
index 00000000..032b5b95
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280-cache.lib b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280-cache.lib
new file mode 100644
index 00000000..9a2d9f78
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280-cache.lib
@@ -0,0 +1,150 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir
new file mode 100644
index 00000000..003d3f7e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir
@@ -0,0 +1,71 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74ALS280\SN74ALS280.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/15/24 20:41:17
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U13  Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and		
+U14  Net-_U13-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_and		
+U15  Net-_U14-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad3_ d_and		
+X19  Net-_U1-Pad3_ Net-_U1-Pad2_ ? Net-_U31-Pad1_ 3_and		
+U22  Net-_U22-Pad1_ Net-_U13-Pad3_ Net-_U22-Pad3_ d_nand		
+U23  Net-_U23-Pad1_ Net-_U14-Pad3_ Net-_U23-Pad3_ d_nand		
+U24  Net-_U24-Pad1_ Net-_U15-Pad3_ Net-_U24-Pad3_ d_nand		
+X22  Net-_U31-Pad2_ Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U34-Pad1_ 4_and		
+U31  Net-_U31-Pad1_ Net-_U31-Pad2_ d_inverter		
+U34  Net-_U34-Pad1_ Net-_U34-Pad2_ d_inverter		
+U35  Net-_U35-Pad1_ Net-_U35-Pad2_ d_inverter		
+U36  Net-_U36-Pad1_ Net-_U36-Pad2_ d_inverter		
+X29  Net-_U34-Pad2_ Net-_U35-Pad1_ Net-_U36-Pad1_ Net-_X29-Pad4_ 3_and		
+X30  Net-_U34-Pad1_ Net-_U35-Pad2_ Net-_U36-Pad1_ Net-_X30-Pad4_ 3_and		
+X31  Net-_U34-Pad1_ Net-_U36-Pad2_ Net-_U35-Pad1_ Net-_X31-Pad4_ 3_and		
+X32  Net-_U34-Pad2_ Net-_U36-Pad2_ Net-_U35-Pad2_ Net-_X32-Pad4_ 3_and		
+X34  Net-_X29-Pad4_ Net-_X30-Pad4_ Net-_X31-Pad4_ Net-_X32-Pad4_ Net-_U38-Pad1_ 4_OR		
+U38  Net-_U38-Pad1_ Net-_U1-Pad10_ d_inverter		
+X25  Net-_U34-Pad1_ Net-_U36-Pad2_ Net-_U35-Pad2_ Net-_X25-Pad4_ 3_and		
+X26  Net-_U34-Pad2_ Net-_U36-Pad2_ Net-_U35-Pad1_ Net-_X26-Pad4_ 3_and		
+X27  Net-_U34-Pad2_ Net-_U35-Pad2_ Net-_U36-Pad1_ Net-_X27-Pad4_ 3_and		
+X28  Net-_U34-Pad1_ Net-_U35-Pad1_ Net-_U36-Pad1_ Net-_X28-Pad4_ 3_and		
+X33  Net-_X25-Pad4_ Net-_X26-Pad4_ Net-_X27-Pad4_ Net-_X28-Pad4_ Net-_U37-Pad1_ 4_OR		
+U37  Net-_U37-Pad1_ Net-_U1-Pad11_ d_inverter		
+U17  Net-_U1-Pad2_ Net-_U13-Pad2_ d_inverter		
+U43  Net-_U14-Pad2_ Net-_U22-Pad1_ d_inverter		
+U16  Net-_U1-Pad1_ Net-_U14-Pad2_ d_inverter		
+U44  Net-_U13-Pad2_ Net-_U23-Pad1_ d_inverter		
+U18  Net-_U1-Pad3_ Net-_U13-Pad1_ d_inverter		
+U45  Net-_U13-Pad1_ Net-_U24-Pad1_ d_inverter		
+U28  Net-_U21-Pad2_ Net-_U20-Pad2_ Net-_U28-Pad3_ d_and		
+U29  Net-_U21-Pad2_ Net-_U19-Pad2_ Net-_U29-Pad3_ d_and		
+U30  Net-_U19-Pad2_ Net-_U20-Pad2_ Net-_U30-Pad3_ d_and		
+X1  Net-_U1-Pad6_ Net-_U1-Pad5_ ? Net-_U58-Pad1_ 3_and		
+U52  Net-_U46-Pad2_ Net-_U28-Pad3_ Net-_U52-Pad3_ d_nand		
+U53  Net-_U47-Pad2_ Net-_U29-Pad3_ Net-_U53-Pad3_ d_nand		
+U54  Net-_U48-Pad2_ Net-_U30-Pad3_ Net-_U54-Pad3_ d_nand		
+X3  Net-_U58-Pad2_ Net-_U52-Pad3_ Net-_U53-Pad3_ Net-_U54-Pad3_ Net-_U35-Pad1_ 4_and		
+U58  Net-_U58-Pad1_ Net-_U58-Pad2_ d_inverter		
+U20  Net-_U1-Pad5_ Net-_U20-Pad2_ d_inverter		
+U46  Net-_U19-Pad2_ Net-_U46-Pad2_ d_inverter		
+U19  Net-_U1-Pad4_ Net-_U19-Pad2_ d_inverter		
+U47  Net-_U20-Pad2_ Net-_U47-Pad2_ d_inverter		
+U21  Net-_U1-Pad6_ Net-_U21-Pad2_ d_inverter		
+U48  Net-_U21-Pad2_ Net-_U48-Pad2_ d_inverter		
+U32  Net-_U27-Pad2_ Net-_U26-Pad2_ Net-_U32-Pad3_ d_and		
+U33  Net-_U27-Pad2_ Net-_U25-Pad2_ Net-_U33-Pad3_ d_and		
+U42  Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U42-Pad3_ d_and		
+X2  Net-_U1-Pad9_ Net-_U1-Pad8_ ? Net-_U59-Pad1_ 3_and		
+U55  Net-_U49-Pad2_ Net-_U32-Pad3_ Net-_U55-Pad3_ d_nand		
+U56  Net-_U50-Pad2_ Net-_U33-Pad3_ Net-_U56-Pad3_ d_nand		
+U57  Net-_U51-Pad2_ Net-_U42-Pad3_ Net-_U57-Pad3_ d_nand		
+X4  Net-_U59-Pad2_ Net-_U55-Pad3_ Net-_U56-Pad3_ Net-_U57-Pad3_ Net-_U36-Pad1_ 4_and		
+U59  Net-_U59-Pad1_ Net-_U59-Pad2_ d_inverter		
+U26  Net-_U1-Pad8_ Net-_U26-Pad2_ d_inverter		
+U49  Net-_U25-Pad2_ Net-_U49-Pad2_ d_inverter		
+U25  Net-_U1-Pad7_ Net-_U25-Pad2_ d_inverter		
+U50  Net-_U26-Pad2_ Net-_U50-Pad2_ d_inverter		
+U27  Net-_U1-Pad9_ Net-_U27-Pad2_ d_inverter		
+U51  Net-_U27-Pad2_ Net-_U51-Pad2_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir.out b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir.out
new file mode 100644
index 00000000..86483e73
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.cir.out
@@ -0,0 +1,207 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74als280\sn74als280.cir
+
+.include 4_and.sub
+.include 4_OR.sub
+.include 3_and.sub
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and
+* u14  net-_u13-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and
+* u15  net-_u14-pad2_ net-_u13-pad2_ net-_u15-pad3_ d_and
+x19 net-_u1-pad3_ net-_u1-pad2_ ? net-_u31-pad1_ 3_and
+* u22  net-_u22-pad1_ net-_u13-pad3_ net-_u22-pad3_ d_nand
+* u23  net-_u23-pad1_ net-_u14-pad3_ net-_u23-pad3_ d_nand
+* u24  net-_u24-pad1_ net-_u15-pad3_ net-_u24-pad3_ d_nand
+x22 net-_u31-pad2_ net-_u22-pad3_ net-_u23-pad3_ net-_u24-pad3_ net-_u34-pad1_ 4_and
+* u31  net-_u31-pad1_ net-_u31-pad2_ d_inverter
+* u34  net-_u34-pad1_ net-_u34-pad2_ d_inverter
+* u35  net-_u35-pad1_ net-_u35-pad2_ d_inverter
+* u36  net-_u36-pad1_ net-_u36-pad2_ d_inverter
+x29 net-_u34-pad2_ net-_u35-pad1_ net-_u36-pad1_ net-_x29-pad4_ 3_and
+x30 net-_u34-pad1_ net-_u35-pad2_ net-_u36-pad1_ net-_x30-pad4_ 3_and
+x31 net-_u34-pad1_ net-_u36-pad2_ net-_u35-pad1_ net-_x31-pad4_ 3_and
+x32 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad2_ net-_x32-pad4_ 3_and
+x34 net-_x29-pad4_ net-_x30-pad4_ net-_x31-pad4_ net-_x32-pad4_ net-_u38-pad1_ 4_OR
+* u38  net-_u38-pad1_ net-_u1-pad10_ d_inverter
+x25 net-_u34-pad1_ net-_u36-pad2_ net-_u35-pad2_ net-_x25-pad4_ 3_and
+x26 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad1_ net-_x26-pad4_ 3_and
+x27 net-_u34-pad2_ net-_u35-pad2_ net-_u36-pad1_ net-_x27-pad4_ 3_and
+x28 net-_u34-pad1_ net-_u35-pad1_ net-_u36-pad1_ net-_x28-pad4_ 3_and
+x33 net-_x25-pad4_ net-_x26-pad4_ net-_x27-pad4_ net-_x28-pad4_ net-_u37-pad1_ 4_OR
+* u37  net-_u37-pad1_ net-_u1-pad11_ d_inverter
+* u17  net-_u1-pad2_ net-_u13-pad2_ d_inverter
+* u43  net-_u14-pad2_ net-_u22-pad1_ d_inverter
+* u16  net-_u1-pad1_ net-_u14-pad2_ d_inverter
+* u44  net-_u13-pad2_ net-_u23-pad1_ d_inverter
+* u18  net-_u1-pad3_ net-_u13-pad1_ d_inverter
+* u45  net-_u13-pad1_ net-_u24-pad1_ d_inverter
+* u28  net-_u21-pad2_ net-_u20-pad2_ net-_u28-pad3_ d_and
+* u29  net-_u21-pad2_ net-_u19-pad2_ net-_u29-pad3_ d_and
+* u30  net-_u19-pad2_ net-_u20-pad2_ net-_u30-pad3_ d_and
+x1 net-_u1-pad6_ net-_u1-pad5_ ? net-_u58-pad1_ 3_and
+* u52  net-_u46-pad2_ net-_u28-pad3_ net-_u52-pad3_ d_nand
+* u53  net-_u47-pad2_ net-_u29-pad3_ net-_u53-pad3_ d_nand
+* u54  net-_u48-pad2_ net-_u30-pad3_ net-_u54-pad3_ d_nand
+x3 net-_u58-pad2_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u35-pad1_ 4_and
+* u58  net-_u58-pad1_ net-_u58-pad2_ d_inverter
+* u20  net-_u1-pad5_ net-_u20-pad2_ d_inverter
+* u46  net-_u19-pad2_ net-_u46-pad2_ d_inverter
+* u19  net-_u1-pad4_ net-_u19-pad2_ d_inverter
+* u47  net-_u20-pad2_ net-_u47-pad2_ d_inverter
+* u21  net-_u1-pad6_ net-_u21-pad2_ d_inverter
+* u48  net-_u21-pad2_ net-_u48-pad2_ d_inverter
+* u32  net-_u27-pad2_ net-_u26-pad2_ net-_u32-pad3_ d_and
+* u33  net-_u27-pad2_ net-_u25-pad2_ net-_u33-pad3_ d_and
+* u42  net-_u25-pad2_ net-_u26-pad2_ net-_u42-pad3_ d_and
+x2 net-_u1-pad9_ net-_u1-pad8_ ? net-_u59-pad1_ 3_and
+* u55  net-_u49-pad2_ net-_u32-pad3_ net-_u55-pad3_ d_nand
+* u56  net-_u50-pad2_ net-_u33-pad3_ net-_u56-pad3_ d_nand
+* u57  net-_u51-pad2_ net-_u42-pad3_ net-_u57-pad3_ d_nand
+x4 net-_u59-pad2_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u36-pad1_ 4_and
+* u59  net-_u59-pad1_ net-_u59-pad2_ d_inverter
+* u26  net-_u1-pad8_ net-_u26-pad2_ d_inverter
+* u49  net-_u25-pad2_ net-_u49-pad2_ d_inverter
+* u25  net-_u1-pad7_ net-_u25-pad2_ d_inverter
+* u50  net-_u26-pad2_ net-_u50-pad2_ d_inverter
+* u27  net-_u1-pad9_ net-_u27-pad2_ d_inverter
+* u51  net-_u27-pad2_ net-_u51-pad2_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port
+a1 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a2 [net-_u13-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a3 [net-_u14-pad2_ net-_u13-pad2_ ] net-_u15-pad3_ u15
+a4 [net-_u22-pad1_ net-_u13-pad3_ ] net-_u22-pad3_ u22
+a5 [net-_u23-pad1_ net-_u14-pad3_ ] net-_u23-pad3_ u23
+a6 [net-_u24-pad1_ net-_u15-pad3_ ] net-_u24-pad3_ u24
+a7 net-_u31-pad1_ net-_u31-pad2_ u31
+a8 net-_u34-pad1_ net-_u34-pad2_ u34
+a9 net-_u35-pad1_ net-_u35-pad2_ u35
+a10 net-_u36-pad1_ net-_u36-pad2_ u36
+a11 net-_u38-pad1_ net-_u1-pad10_ u38
+a12 net-_u37-pad1_ net-_u1-pad11_ u37
+a13 net-_u1-pad2_ net-_u13-pad2_ u17
+a14 net-_u14-pad2_ net-_u22-pad1_ u43
+a15 net-_u1-pad1_ net-_u14-pad2_ u16
+a16 net-_u13-pad2_ net-_u23-pad1_ u44
+a17 net-_u1-pad3_ net-_u13-pad1_ u18
+a18 net-_u13-pad1_ net-_u24-pad1_ u45
+a19 [net-_u21-pad2_ net-_u20-pad2_ ] net-_u28-pad3_ u28
+a20 [net-_u21-pad2_ net-_u19-pad2_ ] net-_u29-pad3_ u29
+a21 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u30-pad3_ u30
+a22 [net-_u46-pad2_ net-_u28-pad3_ ] net-_u52-pad3_ u52
+a23 [net-_u47-pad2_ net-_u29-pad3_ ] net-_u53-pad3_ u53
+a24 [net-_u48-pad2_ net-_u30-pad3_ ] net-_u54-pad3_ u54
+a25 net-_u58-pad1_ net-_u58-pad2_ u58
+a26 net-_u1-pad5_ net-_u20-pad2_ u20
+a27 net-_u19-pad2_ net-_u46-pad2_ u46
+a28 net-_u1-pad4_ net-_u19-pad2_ u19
+a29 net-_u20-pad2_ net-_u47-pad2_ u47
+a30 net-_u1-pad6_ net-_u21-pad2_ u21
+a31 net-_u21-pad2_ net-_u48-pad2_ u48
+a32 [net-_u27-pad2_ net-_u26-pad2_ ] net-_u32-pad3_ u32
+a33 [net-_u27-pad2_ net-_u25-pad2_ ] net-_u33-pad3_ u33
+a34 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u42-pad3_ u42
+a35 [net-_u49-pad2_ net-_u32-pad3_ ] net-_u55-pad3_ u55
+a36 [net-_u50-pad2_ net-_u33-pad3_ ] net-_u56-pad3_ u56
+a37 [net-_u51-pad2_ net-_u42-pad3_ ] net-_u57-pad3_ u57
+a38 net-_u59-pad1_ net-_u59-pad2_ u59
+a39 net-_u1-pad8_ net-_u26-pad2_ u26
+a40 net-_u25-pad2_ net-_u49-pad2_ u49
+a41 net-_u1-pad7_ net-_u25-pad2_ u25
+a42 net-_u26-pad2_ net-_u50-pad2_ u50
+a43 net-_u1-pad9_ net-_u27-pad2_ u27
+a44 net-_u27-pad2_ net-_u51-pad2_ u51
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-03 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.pro b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.proj b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.proj
new file mode 100644
index 00000000..ed5e61fc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.proj
@@ -0,0 +1 @@
+schematicFile SN74ALS280.sch
diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch
new file mode 100644
index 00000000..67998706
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sch
@@ -0,0 +1,1294 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74ALS280-cache
+EELAYER 25 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
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+	18900 5850 18900 6050
+Wire Wire Line
+	18900 6050 19000 6050
+Wire Wire Line
+	19000 6150 18900 6150
+Wire Wire Line
+	18900 6150 18900 6350
+Wire Wire Line
+	18900 6350 18700 6350
+Wire Wire Line
+	18700 6850 19000 6850
+Wire Wire Line
+	19000 6850 19000 6250
+$Comp
+L 3_and X25
+U 1 1 666DB38E
+P 18150 9050
+F 0 "X25" H 18250 9000 60  0000 C CNN
+F 1 "3_and" H 18300 9200 60  0000 C CNN
+F 2 "" H 18150 9050 60  0000 C CNN
+F 3 "" H 18150 9050 60  0000 C CNN
+	1    18150 9050
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X26
+U 1 1 666DB394
+P 18150 9550
+F 0 "X26" H 18250 9500 60  0000 C CNN
+F 1 "3_and" H 18300 9700 60  0000 C CNN
+F 2 "" H 18150 9550 60  0000 C CNN
+F 3 "" H 18150 9550 60  0000 C CNN
+	1    18150 9550
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X27
+U 1 1 666DB39A
+P 18150 10050
+F 0 "X27" H 18250 10000 60  0000 C CNN
+F 1 "3_and" H 18300 10200 60  0000 C CNN
+F 2 "" H 18150 10050 60  0000 C CNN
+F 3 "" H 18150 10050 60  0000 C CNN
+	1    18150 10050
+	1    0    0    -1  
+$EndComp
+$Comp
+L 3_and X28
+U 1 1 666DB3A0
+P 18150 10550
+F 0 "X28" H 18250 10500 60  0000 C CNN
+F 1 "3_and" H 18300 10700 60  0000 C CNN
+F 2 "" H 18150 10550 60  0000 C CNN
+F 3 "" H 18150 10550 60  0000 C CNN
+	1    18150 10550
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4_OR X33
+U 1 1 666DB3A6
+P 19300 9750
+F 0 "X33" H 19450 9650 60  0000 C CNN
+F 1 "4_OR" H 19450 9850 60  0000 C CNN
+F 2 "" H 19300 9750 60  0000 C CNN
+F 3 "" H 19300 9750 60  0000 C CNN
+	1    19300 9750
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U37
+U 1 1 666DB3AC
+P 20150 9750
+F 0 "U37" H 20150 9650 60  0000 C CNN
+F 1 "d_inverter" H 20150 9900 60  0000 C CNN
+F 2 "" H 20200 9700 60  0000 C CNN
+F 3 "" H 20200 9700 60  0000 C CNN
+	1    20150 9750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	18950 9600 18950 9000
+Wire Wire Line
+	18950 9000 18650 9000
+Wire Wire Line
+	18650 9500 18850 9500
+Wire Wire Line
+	18850 9500 18850 9700
+Wire Wire Line
+	18850 9700 18950 9700
+Wire Wire Line
+	18950 9800 18850 9800
+Wire Wire Line
+	18850 9800 18850 10000
+Wire Wire Line
+	18850 10000 18650 10000
+Wire Wire Line
+	18650 10500 18950 10500
+Wire Wire Line
+	18950 10500 18950 9900
+Wire Wire Line
+	15950 10600 17800 10600
+Wire Wire Line
+	15950 5450 15950 12050
+Wire Wire Line
+	15950 12050 14750 12050
+Wire Wire Line
+	14750 12050 14750 11650
+Wire Wire Line
+	15950 10100 17800 10100
+Connection ~ 15950 10600
+Wire Wire Line
+	15950 5950 17850 5950
+Connection ~ 15950 10100
+Wire Wire Line
+	15950 5450 17850 5450
+Connection ~ 15950 5950
+Wire Wire Line
+	15200 4650 17200 4650
+Wire Wire Line
+	17200 4650 17200 9900
+Wire Wire Line
+	17200 5250 17850 5250
+Wire Wire Line
+	14600 4650 14600 5150
+Wire Wire Line
+	14600 5150 16800 5150
+Wire Wire Line
+	16800 5150 16800 10400
+Wire Wire Line
+	16800 5750 17850 5750
+Wire Wire Line
+	17200 6750 17850 6750
+Connection ~ 17200 5250
+Wire Wire Line
+	16800 6250 17850 6250
+Connection ~ 16800 5750
+Wire Wire Line
+	17850 5350 17000 5350
+Wire Wire Line
+	17000 5350 17000 10500
+Wire Wire Line
+	17000 6450 17850 6450
+Wire Wire Line
+	17850 5850 17400 5850
+Wire Wire Line
+	17400 5850 17400 10000
+Wire Wire Line
+	17400 6950 17850 6950
+Wire Wire Line
+	17550 6350 17850 6350
+Wire Wire Line
+	17550 6350 17550 11650
+Wire Wire Line
+	17550 6850 17850 6850
+Wire Wire Line
+	17400 8150 15300 8150
+Connection ~ 17400 6950
+Wire Wire Line
+	17000 8700 14700 8700
+Wire Wire Line
+	14700 8700 14700 8150
+Connection ~ 17000 6450
+Wire Wire Line
+	17000 10500 17800 10500
+Connection ~ 17000 8700
+Wire Wire Line
+	17800 9600 17000 9600
+Connection ~ 17000 9600
+Wire Wire Line
+	17550 9000 17800 9000
+Connection ~ 17550 6850
+Wire Wire Line
+	17550 9500 17800 9500
+Connection ~ 17550 9000
+Wire Wire Line
+	17200 9400 17800 9400
+Wire Wire Line
+	17400 10000 17800 10000
+Connection ~ 17200 6750
+Connection ~ 17200 9400
+Connection ~ 16800 6250
+Connection ~ 16800 8900
+Wire Wire Line
+	16800 8900 17800 8900
+Wire Wire Line
+	16800 10400 17800 10400
+Wire Wire Line
+	17200 9900 17800 9900
+Connection ~ 17400 8150
+Connection ~ 17400 9100
+Wire Wire Line
+	17800 9100 17400 9100
+Wire Wire Line
+	17550 11650 15350 11650
+Connection ~ 17550 9500
+Wire Wire Line
+	20450 9750 20450 8050
+Wire Wire Line
+	20450 8050 20700 8050
+Wire Wire Line
+	20700 7950 20450 7950
+Wire Wire Line
+	20450 7950 20450 6200
+Wire Wire Line
+	20450 6200 20500 6200
+Wire Wire Line
+	20500 6200 20500 6100
+Wire Wire Line
+	6400 4900 7500 4900
+Wire Wire Line
+	7500 4900 7500 5550
+Wire Wire Line
+	7500 4100 8750 4100
+Wire Wire Line
+	7500 4100 7500 4700
+Wire Wire Line
+	7500 4700 6400 4700
+$Comp
+L d_inverter U17
+U 1 1 666ECAE4
+P 9050 4800
+F 0 "U17" H 9050 4700 60  0000 C CNN
+F 1 "d_inverter" H 9050 4950 60  0000 C CNN
+F 2 "" H 9100 4750 60  0000 C CNN
+F 3 "" H 9100 4750 60  0000 C CNN
+	1    9050 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U43
+U 1 1 666ED171
+P 11700 4100
+F 0 "U43" H 11700 4000 60  0000 C CNN
+F 1 "d_inverter" H 11700 4250 60  0000 C CNN
+F 2 "" H 11750 4050 60  0000 C CNN
+F 3 "" H 11750 4050 60  0000 C CNN
+	1    11700 4100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12000 4100 12250 4100
+$Comp
+L d_inverter U16
+U 1 1 666ED179
+P 9050 4100
+F 0 "U16" H 9050 4000 60  0000 C CNN
+F 1 "d_inverter" H 9050 4250 60  0000 C CNN
+F 2 "" H 9100 4050 60  0000 C CNN
+F 3 "" H 9100 4050 60  0000 C CNN
+	1    9050 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U44
+U 1 1 666ED8A2
+P 11700 4800
+F 0 "U44" H 11700 4700 60  0000 C CNN
+F 1 "d_inverter" H 11700 4950 60  0000 C CNN
+F 2 "" H 11750 4750 60  0000 C CNN
+F 3 "" H 11750 4750 60  0000 C CNN
+	1    11700 4800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12000 4800 12250 4800
+$Comp
+L d_inverter U18
+U 1 1 666EDB41
+P 9050 5550
+F 0 "U18" H 9050 5450 60  0000 C CNN
+F 1 "d_inverter" H 9050 5700 60  0000 C CNN
+F 2 "" H 9100 5500 60  0000 C CNN
+F 3 "" H 9100 5500 60  0000 C CNN
+	1    9050 5550
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U45
+U 1 1 666EDC64
+P 11750 5550
+F 0 "U45" H 11750 5450 60  0000 C CNN
+F 1 "d_inverter" H 11750 5700 60  0000 C CNN
+F 2 "" H 11800 5500 60  0000 C CNN
+F 3 "" H 11800 5500 60  0000 C CNN
+	1    11750 5550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12050 5550 12300 5550
+$Comp
+L d_and U28
+U 1 1 666EEBD7
+P 10700 7950
+F 0 "U28" H 10700 7950 60  0000 C CNN
+F 1 "d_and" H 10750 8050 60  0000 C CNN
+F 2 "" H 10700 7950 60  0000 C CNN
+F 3 "" H 10700 7950 60  0000 C CNN
+	1    10700 7950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9400 7600 11450 7600
+$Comp
+L d_and U29
+U 1 1 666EEBDE
+P 10700 8650
+F 0 "U29" H 10700 8650 60  0000 C CNN
+F 1 "d_and" H 10750 8750 60  0000 C CNN
+F 2 "" H 10700 8650 60  0000 C CNN
+F 3 "" H 10700 8650 60  0000 C CNN
+	1    10700 8650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9400 8300 11450 8300
+$Comp
+L d_and U30
+U 1 1 666EEBE5
+P 10750 9400
+F 0 "U30" H 10750 9400 60  0000 C CNN
+F 1 "d_and" H 10800 9500 60  0000 C CNN
+F 2 "" H 10750 9400 60  0000 C CNN
+F 3 "" H 10750 9400 60  0000 C CNN
+	1    10750 9400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9400 9050 11500 9050
+Wire Wire Line
+	10250 7850 10100 7850
+Wire Wire Line
+	10100 7850 10100 9050
+Wire Wire Line
+	10100 8550 10250 8550
+Connection ~ 10100 9050
+Connection ~ 10100 8550
+Wire Wire Line
+	10300 9400 9800 9400
+Wire Wire Line
+	9800 9400 9800 8300
+Connection ~ 9800 8300
+Wire Wire Line
+	10000 8300 10000 7950
+Wire Wire Line
+	10000 7950 10250 7950
+Connection ~ 10000 8300
+Wire Wire Line
+	10250 9300 10300 9300
+Wire Wire Line
+	10250 7600 10250 9300
+Connection ~ 10250 7600
+Connection ~ 10250 8650
+$Comp
+L 3_and X1
+U 1 1 666EEBFB
+P 12700 6950
+F 0 "X1" H 12800 6900 60  0000 C CNN
+F 1 "3_and" H 12850 7100 60  0000 C CNN
+F 2 "" H 12700 6950 60  0000 C CNN
+F 3 "" H 12700 6950 60  0000 C CNN
+	1    12700 6950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12350 7000 8500 7000
+Wire Wire Line
+	8500 7000 8500 7600
+Wire Wire Line
+	6450 8300 8800 8300
+Wire Wire Line
+	8350 8300 8350 6900
+Wire Wire Line
+	8350 6900 12350 6900
+Wire Wire Line
+	12350 6800 8200 6800
+Wire Wire Line
+	8200 6800 8200 9050
+Wire Wire Line
+	7550 9050 8800 9050
+Connection ~ 8350 8300
+Connection ~ 8200 9050
+$Comp
+L d_nand U52
+U 1 1 666EEC0B
+P 12750 7700
+F 0 "U52" H 12750 7700 60  0000 C CNN
+F 1 "d_nand" H 12800 7800 60  0000 C CNN
+F 2 "" H 12750 7700 60  0000 C CNN
+F 3 "" H 12750 7700 60  0000 C CNN
+	1    12750 7700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U53
+U 1 1 666EEC11
+P 12750 8400
+F 0 "U53" H 12750 8400 60  0000 C CNN
+F 1 "d_nand" H 12800 8500 60  0000 C CNN
+F 2 "" H 12750 8400 60  0000 C CNN
+F 3 "" H 12750 8400 60  0000 C CNN
+	1    12750 8400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U54
+U 1 1 666EEC17
+P 12800 9150
+F 0 "U54" H 12800 9150 60  0000 C CNN
+F 1 "d_nand" H 12850 9250 60  0000 C CNN
+F 2 "" H 12800 9150 60  0000 C CNN
+F 3 "" H 12800 9150 60  0000 C CNN
+	1    12800 9150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12350 9150 12350 9350
+Wire Wire Line
+	12350 9350 11200 9350
+Wire Wire Line
+	11150 8600 12300 8600
+Wire Wire Line
+	12300 8600 12300 8400
+Wire Wire Line
+	11150 7900 12300 7900
+Wire Wire Line
+	12300 7900 12300 7700
+$Comp
+L 4_and X3
+U 1 1 666EEC23
+P 14150 8150
+F 0 "X3" H 14200 8100 60  0000 C CNN
+F 1 "4_and" H 14250 8250 60  0000 C CNN
+F 2 "" H 14150 8150 60  0000 C CNN
+F 3 "" H 14150 8150 60  0000 C CNN
+	1    14150 8150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U58
+U 1 1 666EEC29
+P 13550 7250
+F 0 "U58" H 13550 7150 60  0000 C CNN
+F 1 "d_inverter" H 13550 7400 60  0000 C CNN
+F 2 "" H 13600 7200 60  0000 C CNN
+F 3 "" H 13600 7200 60  0000 C CNN
+	1    13550 7250
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	13550 6950 13550 6900
+Wire Wire Line
+	13550 6900 13200 6900
+Wire Wire Line
+	13550 7550 13550 8000
+Wire Wire Line
+	13550 8000 13750 8000
+Wire Wire Line
+	13750 8100 13500 8100
+Wire Wire Line
+	13500 8100 13500 7650
+Wire Wire Line
+	13500 7650 13200 7650
+Wire Wire Line
+	13250 9100 13550 9100
+Wire Wire Line
+	13550 9100 13550 8300
+Wire Wire Line
+	13550 8300 13750 8300
+Wire Wire Line
+	13750 8200 13500 8200
+Wire Wire Line
+	13500 8200 13500 8350
+Wire Wire Line
+	13500 8350 13200 8350
+Wire Wire Line
+	6450 8400 7550 8400
+Wire Wire Line
+	7550 8400 7550 9050
+Wire Wire Line
+	7550 7600 8800 7600
+Wire Wire Line
+	7550 7600 7550 8200
+Wire Wire Line
+	7550 8200 6450 8200
+$Comp
+L d_inverter U20
+U 1 1 666EEC41
+P 9100 8300
+F 0 "U20" H 9100 8200 60  0000 C CNN
+F 1 "d_inverter" H 9100 8450 60  0000 C CNN
+F 2 "" H 9150 8250 60  0000 C CNN
+F 3 "" H 9150 8250 60  0000 C CNN
+	1    9100 8300
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U46
+U 1 1 666EEC49
+P 11750 7600
+F 0 "U46" H 11750 7500 60  0000 C CNN
+F 1 "d_inverter" H 11750 7750 60  0000 C CNN
+F 2 "" H 11800 7550 60  0000 C CNN
+F 3 "" H 11800 7550 60  0000 C CNN
+	1    11750 7600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12050 7600 12300 7600
+$Comp
+L d_inverter U19
+U 1 1 666EEC51
+P 9100 7600
+F 0 "U19" H 9100 7500 60  0000 C CNN
+F 1 "d_inverter" H 9100 7750 60  0000 C CNN
+F 2 "" H 9150 7550 60  0000 C CNN
+F 3 "" H 9150 7550 60  0000 C CNN
+	1    9100 7600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U47
+U 1 1 666EEC59
+P 11750 8300
+F 0 "U47" H 11750 8200 60  0000 C CNN
+F 1 "d_inverter" H 11750 8450 60  0000 C CNN
+F 2 "" H 11800 8250 60  0000 C CNN
+F 3 "" H 11800 8250 60  0000 C CNN
+	1    11750 8300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12050 8300 12300 8300
+$Comp
+L d_inverter U21
+U 1 1 666EEC61
+P 9100 9050
+F 0 "U21" H 9100 8950 60  0000 C CNN
+F 1 "d_inverter" H 9100 9200 60  0000 C CNN
+F 2 "" H 9150 9000 60  0000 C CNN
+F 3 "" H 9150 9000 60  0000 C CNN
+	1    9100 9050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U48
+U 1 1 666EEC69
+P 11800 9050
+F 0 "U48" H 11800 8950 60  0000 C CNN
+F 1 "d_inverter" H 11800 9200 60  0000 C CNN
+F 2 "" H 11850 9000 60  0000 C CNN
+F 3 "" H 11850 9000 60  0000 C CNN
+	1    11800 9050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12100 9050 12350 9050
+Wire Wire Line
+	14700 8150 14650 8150
+$Comp
+L d_and U32
+U 1 1 666F08E4
+P 10800 11450
+F 0 "U32" H 10800 11450 60  0000 C CNN
+F 1 "d_and" H 10850 11550 60  0000 C CNN
+F 2 "" H 10800 11450 60  0000 C CNN
+F 3 "" H 10800 11450 60  0000 C CNN
+	1    10800 11450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9500 11100 11550 11100
+$Comp
+L d_and U33
+U 1 1 666F08EB
+P 10800 12150
+F 0 "U33" H 10800 12150 60  0000 C CNN
+F 1 "d_and" H 10850 12250 60  0000 C CNN
+F 2 "" H 10800 12150 60  0000 C CNN
+F 3 "" H 10800 12150 60  0000 C CNN
+	1    10800 12150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9500 11800 11550 11800
+$Comp
+L d_and U42
+U 1 1 666F08F2
+P 10850 12900
+F 0 "U42" H 10850 12900 60  0000 C CNN
+F 1 "d_and" H 10900 13000 60  0000 C CNN
+F 2 "" H 10850 12900 60  0000 C CNN
+F 3 "" H 10850 12900 60  0000 C CNN
+	1    10850 12900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9500 12550 11600 12550
+Wire Wire Line
+	10350 11350 10200 11350
+Wire Wire Line
+	10200 11350 10200 12550
+Wire Wire Line
+	10200 12050 10350 12050
+Connection ~ 10200 12550
+Connection ~ 10200 12050
+Wire Wire Line
+	10400 12900 9900 12900
+Wire Wire Line
+	9900 12900 9900 11800
+Connection ~ 9900 11800
+Wire Wire Line
+	10100 11800 10100 11450
+Wire Wire Line
+	10100 11450 10350 11450
+Connection ~ 10100 11800
+Wire Wire Line
+	10350 12800 10400 12800
+Wire Wire Line
+	10350 11100 10350 12800
+Connection ~ 10350 11100
+Connection ~ 10350 12150
+$Comp
+L 3_and X2
+U 1 1 666F0908
+P 12800 10450
+F 0 "X2" H 12900 10400 60  0000 C CNN
+F 1 "3_and" H 12950 10600 60  0000 C CNN
+F 2 "" H 12800 10450 60  0000 C CNN
+F 3 "" H 12800 10450 60  0000 C CNN
+	1    12800 10450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12450 10500 8600 10500
+Wire Wire Line
+	8600 10500 8600 11100
+Wire Wire Line
+	6550 11800 8900 11800
+Wire Wire Line
+	8450 11800 8450 10400
+Wire Wire Line
+	8450 10400 12450 10400
+Wire Wire Line
+	12450 10300 8300 10300
+Wire Wire Line
+	8300 10300 8300 12550
+Wire Wire Line
+	7650 12550 8900 12550
+Connection ~ 8450 11800
+Connection ~ 8300 12550
+$Comp
+L d_nand U55
+U 1 1 666F0918
+P 12850 11200
+F 0 "U55" H 12850 11200 60  0000 C CNN
+F 1 "d_nand" H 12900 11300 60  0000 C CNN
+F 2 "" H 12850 11200 60  0000 C CNN
+F 3 "" H 12850 11200 60  0000 C CNN
+	1    12850 11200
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U56
+U 1 1 666F091E
+P 12850 11900
+F 0 "U56" H 12850 11900 60  0000 C CNN
+F 1 "d_nand" H 12900 12000 60  0000 C CNN
+F 2 "" H 12850 11900 60  0000 C CNN
+F 3 "" H 12850 11900 60  0000 C CNN
+	1    12850 11900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nand U57
+U 1 1 666F0924
+P 12900 12650
+F 0 "U57" H 12900 12650 60  0000 C CNN
+F 1 "d_nand" H 12950 12750 60  0000 C CNN
+F 2 "" H 12900 12650 60  0000 C CNN
+F 3 "" H 12900 12650 60  0000 C CNN
+	1    12900 12650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	12450 12650 12450 12850
+Wire Wire Line
+	12450 12850 11300 12850
+Wire Wire Line
+	11250 12100 12400 12100
+Wire Wire Line
+	12400 12100 12400 11900
+Wire Wire Line
+	11250 11400 12400 11400
+Wire Wire Line
+	12400 11400 12400 11200
+$Comp
+L 4_and X4
+U 1 1 666F0930
+P 14250 11650
+F 0 "X4" H 14300 11600 60  0000 C CNN
+F 1 "4_and" H 14350 11750 60  0000 C CNN
+F 2 "" H 14250 11650 60  0000 C CNN
+F 3 "" H 14250 11650 60  0000 C CNN
+	1    14250 11650
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U59
+U 1 1 666F0936
+P 13650 10750
+F 0 "U59" H 13650 10650 60  0000 C CNN
+F 1 "d_inverter" H 13650 10900 60  0000 C CNN
+F 2 "" H 13700 10700 60  0000 C CNN
+F 3 "" H 13700 10700 60  0000 C CNN
+	1    13650 10750
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	13650 10450 13650 10400
+Wire Wire Line
+	13650 10400 13300 10400
+Wire Wire Line
+	13650 11050 13650 11500
+Wire Wire Line
+	13650 11500 13850 11500
+Wire Wire Line
+	13850 11600 13600 11600
+Wire Wire Line
+	13600 11600 13600 11150
+Wire Wire Line
+	13600 11150 13300 11150
+Wire Wire Line
+	13350 12600 13650 12600
+Wire Wire Line
+	13650 12600 13650 11800
+Wire Wire Line
+	13650 11800 13850 11800
+Wire Wire Line
+	13850 11700 13600 11700
+Wire Wire Line
+	13600 11700 13600 11850
+Wire Wire Line
+	13600 11850 13300 11850
+Wire Wire Line
+	6550 11900 7650 11900
+Wire Wire Line
+	7650 11900 7650 12550
+Wire Wire Line
+	7650 11100 8900 11100
+Wire Wire Line
+	7650 11100 7650 11700
+Wire Wire Line
+	7650 11700 6550 11700
+$Comp
+L d_inverter U26
+U 1 1 666F094E
+P 9200 11800
+F 0 "U26" H 9200 11700 60  0000 C CNN
+F 1 "d_inverter" H 9200 11950 60  0000 C CNN
+F 2 "" H 9250 11750 60  0000 C CNN
+F 3 "" H 9250 11750 60  0000 C CNN
+	1    9200 11800
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U49
+U 1 1 666F0954
+P 11850 11100
+F 0 "U49" H 11850 11000 60  0000 C CNN
+F 1 "d_inverter" H 11850 11250 60  0000 C CNN
+F 2 "" H 11900 11050 60  0000 C CNN
+F 3 "" H 11900 11050 60  0000 C CNN
+	1    11850 11100
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+$EndComp
+Wire Wire Line
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+$Comp
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+U 1 1 666F095B
+P 9200 11100
+F 0 "U25" H 9200 11000 60  0000 C CNN
+F 1 "d_inverter" H 9200 11250 60  0000 C CNN
+F 2 "" H 9250 11050 60  0000 C CNN
+F 3 "" H 9250 11050 60  0000 C CNN
+	1    9200 11100
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 666F0961
+P 11850 11800
+F 0 "U50" H 11850 11700 60  0000 C CNN
+F 1 "d_inverter" H 11850 11950 60  0000 C CNN
+F 2 "" H 11900 11750 60  0000 C CNN
+F 3 "" H 11900 11750 60  0000 C CNN
+	1    11850 11800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+$Comp
+L d_inverter U27
+U 1 1 666F0968
+P 9200 12550
+F 0 "U27" H 9200 12450 60  0000 C CNN
+F 1 "d_inverter" H 9200 12700 60  0000 C CNN
+F 2 "" H 9250 12500 60  0000 C CNN
+F 3 "" H 9250 12500 60  0000 C CNN
+	1    9200 12550
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 666F096E
+P 11900 12550
+F 0 "U51" H 11900 12450 60  0000 C CNN
+F 1 "d_inverter" H 11900 12700 60  0000 C CNN
+F 2 "" H 11950 12500 60  0000 C CNN
+F 3 "" H 11950 12500 60  0000 C CNN
+	1    11900 12550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+$Comp
+L PORT U1
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+F 1 "PORT" H 6150 4700 30  0000 C CNN
+F 2 "" H 6150 4700 60  0000 C CNN
+F 3 "" H 6150 4700 60  0000 C CNN
+	1    6150 4700
+	1    0    0    -1  
+$EndComp
+$Comp
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+F 3 "" H 6150 4800 60  0000 C CNN
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+	1    0    0    -1  
+$EndComp
+$Comp
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+F 3 "" H 6150 4900 60  0000 C CNN
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+	1    0    0    -1  
+$EndComp
+$Comp
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+F 3 "" H 6200 8200 60  0000 C CNN
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+	1    0    0    -1  
+$EndComp
+$Comp
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+$EndComp
+$Comp
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+F 3 "" H 6200 8400 60  0000 C CNN
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+F 3 "" H 6300 11900 60  0000 C CNN
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+$EndComp
+$Comp
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+F 1 "PORT" H 20950 7950 30  0000 C CNN
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+F 3 "" H 20950 7950 60  0000 C CNN
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+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 666DD105
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+F 1 "PORT" H 20950 8050 30  0000 C CNN
+F 2 "" H 20950 8050 60  0000 C CNN
+F 3 "" H 20950 8050 60  0000 C CNN
+	11   20950 8050
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+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sub b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sub
new file mode 100644
index 00000000..07595af7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280.sub
@@ -0,0 +1,201 @@
+* Subcircuit SN74ALS280
+.subckt SN74ALS280 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ 
+* c:\fossee\esim\library\subcircuitlibrary\sn74als280\sn74als280.cir
+.include 4_and.sub
+.include 4_OR.sub
+.include 3_and.sub
+* u13  net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and
+* u14  net-_u13-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and
+* u15  net-_u14-pad2_ net-_u13-pad2_ net-_u15-pad3_ d_and
+x19 net-_u1-pad3_ net-_u1-pad2_ ? net-_u31-pad1_ 3_and
+* u22  net-_u22-pad1_ net-_u13-pad3_ net-_u22-pad3_ d_nand
+* u23  net-_u23-pad1_ net-_u14-pad3_ net-_u23-pad3_ d_nand
+* u24  net-_u24-pad1_ net-_u15-pad3_ net-_u24-pad3_ d_nand
+x22 net-_u31-pad2_ net-_u22-pad3_ net-_u23-pad3_ net-_u24-pad3_ net-_u34-pad1_ 4_and
+* u31  net-_u31-pad1_ net-_u31-pad2_ d_inverter
+* u34  net-_u34-pad1_ net-_u34-pad2_ d_inverter
+* u35  net-_u35-pad1_ net-_u35-pad2_ d_inverter
+* u36  net-_u36-pad1_ net-_u36-pad2_ d_inverter
+x29 net-_u34-pad2_ net-_u35-pad1_ net-_u36-pad1_ net-_x29-pad4_ 3_and
+x30 net-_u34-pad1_ net-_u35-pad2_ net-_u36-pad1_ net-_x30-pad4_ 3_and
+x31 net-_u34-pad1_ net-_u36-pad2_ net-_u35-pad1_ net-_x31-pad4_ 3_and
+x32 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad2_ net-_x32-pad4_ 3_and
+x34 net-_x29-pad4_ net-_x30-pad4_ net-_x31-pad4_ net-_x32-pad4_ net-_u38-pad1_ 4_OR
+* u38  net-_u38-pad1_ net-_u1-pad10_ d_inverter
+x25 net-_u34-pad1_ net-_u36-pad2_ net-_u35-pad2_ net-_x25-pad4_ 3_and
+x26 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad1_ net-_x26-pad4_ 3_and
+x27 net-_u34-pad2_ net-_u35-pad2_ net-_u36-pad1_ net-_x27-pad4_ 3_and
+x28 net-_u34-pad1_ net-_u35-pad1_ net-_u36-pad1_ net-_x28-pad4_ 3_and
+x33 net-_x25-pad4_ net-_x26-pad4_ net-_x27-pad4_ net-_x28-pad4_ net-_u37-pad1_ 4_OR
+* u37  net-_u37-pad1_ net-_u1-pad11_ d_inverter
+* u17  net-_u1-pad2_ net-_u13-pad2_ d_inverter
+* u43  net-_u14-pad2_ net-_u22-pad1_ d_inverter
+* u16  net-_u1-pad1_ net-_u14-pad2_ d_inverter
+* u44  net-_u13-pad2_ net-_u23-pad1_ d_inverter
+* u18  net-_u1-pad3_ net-_u13-pad1_ d_inverter
+* u45  net-_u13-pad1_ net-_u24-pad1_ d_inverter
+* u28  net-_u21-pad2_ net-_u20-pad2_ net-_u28-pad3_ d_and
+* u29  net-_u21-pad2_ net-_u19-pad2_ net-_u29-pad3_ d_and
+* u30  net-_u19-pad2_ net-_u20-pad2_ net-_u30-pad3_ d_and
+x1 net-_u1-pad6_ net-_u1-pad5_ ? net-_u58-pad1_ 3_and
+* u52  net-_u46-pad2_ net-_u28-pad3_ net-_u52-pad3_ d_nand
+* u53  net-_u47-pad2_ net-_u29-pad3_ net-_u53-pad3_ d_nand
+* u54  net-_u48-pad2_ net-_u30-pad3_ net-_u54-pad3_ d_nand
+x3 net-_u58-pad2_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u35-pad1_ 4_and
+* u58  net-_u58-pad1_ net-_u58-pad2_ d_inverter
+* u20  net-_u1-pad5_ net-_u20-pad2_ d_inverter
+* u46  net-_u19-pad2_ net-_u46-pad2_ d_inverter
+* u19  net-_u1-pad4_ net-_u19-pad2_ d_inverter
+* u47  net-_u20-pad2_ net-_u47-pad2_ d_inverter
+* u21  net-_u1-pad6_ net-_u21-pad2_ d_inverter
+* u48  net-_u21-pad2_ net-_u48-pad2_ d_inverter
+* u32  net-_u27-pad2_ net-_u26-pad2_ net-_u32-pad3_ d_and
+* u33  net-_u27-pad2_ net-_u25-pad2_ net-_u33-pad3_ d_and
+* u42  net-_u25-pad2_ net-_u26-pad2_ net-_u42-pad3_ d_and
+x2 net-_u1-pad9_ net-_u1-pad8_ ? net-_u59-pad1_ 3_and
+* u55  net-_u49-pad2_ net-_u32-pad3_ net-_u55-pad3_ d_nand
+* u56  net-_u50-pad2_ net-_u33-pad3_ net-_u56-pad3_ d_nand
+* u57  net-_u51-pad2_ net-_u42-pad3_ net-_u57-pad3_ d_nand
+x4 net-_u59-pad2_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u36-pad1_ 4_and
+* u59  net-_u59-pad1_ net-_u59-pad2_ d_inverter
+* u26  net-_u1-pad8_ net-_u26-pad2_ d_inverter
+* u49  net-_u25-pad2_ net-_u49-pad2_ d_inverter
+* u25  net-_u1-pad7_ net-_u25-pad2_ d_inverter
+* u50  net-_u26-pad2_ net-_u50-pad2_ d_inverter
+* u27  net-_u1-pad9_ net-_u27-pad2_ d_inverter
+* u51  net-_u27-pad2_ net-_u51-pad2_ d_inverter
+a1 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a2 [net-_u13-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a3 [net-_u14-pad2_ net-_u13-pad2_ ] net-_u15-pad3_ u15
+a4 [net-_u22-pad1_ net-_u13-pad3_ ] net-_u22-pad3_ u22
+a5 [net-_u23-pad1_ net-_u14-pad3_ ] net-_u23-pad3_ u23
+a6 [net-_u24-pad1_ net-_u15-pad3_ ] net-_u24-pad3_ u24
+a7 net-_u31-pad1_ net-_u31-pad2_ u31
+a8 net-_u34-pad1_ net-_u34-pad2_ u34
+a9 net-_u35-pad1_ net-_u35-pad2_ u35
+a10 net-_u36-pad1_ net-_u36-pad2_ u36
+a11 net-_u38-pad1_ net-_u1-pad10_ u38
+a12 net-_u37-pad1_ net-_u1-pad11_ u37
+a13 net-_u1-pad2_ net-_u13-pad2_ u17
+a14 net-_u14-pad2_ net-_u22-pad1_ u43
+a15 net-_u1-pad1_ net-_u14-pad2_ u16
+a16 net-_u13-pad2_ net-_u23-pad1_ u44
+a17 net-_u1-pad3_ net-_u13-pad1_ u18
+a18 net-_u13-pad1_ net-_u24-pad1_ u45
+a19 [net-_u21-pad2_ net-_u20-pad2_ ] net-_u28-pad3_ u28
+a20 [net-_u21-pad2_ net-_u19-pad2_ ] net-_u29-pad3_ u29
+a21 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u30-pad3_ u30
+a22 [net-_u46-pad2_ net-_u28-pad3_ ] net-_u52-pad3_ u52
+a23 [net-_u47-pad2_ net-_u29-pad3_ ] net-_u53-pad3_ u53
+a24 [net-_u48-pad2_ net-_u30-pad3_ ] net-_u54-pad3_ u54
+a25 net-_u58-pad1_ net-_u58-pad2_ u58
+a26 net-_u1-pad5_ net-_u20-pad2_ u20
+a27 net-_u19-pad2_ net-_u46-pad2_ u46
+a28 net-_u1-pad4_ net-_u19-pad2_ u19
+a29 net-_u20-pad2_ net-_u47-pad2_ u47
+a30 net-_u1-pad6_ net-_u21-pad2_ u21
+a31 net-_u21-pad2_ net-_u48-pad2_ u48
+a32 [net-_u27-pad2_ net-_u26-pad2_ ] net-_u32-pad3_ u32
+a33 [net-_u27-pad2_ net-_u25-pad2_ ] net-_u33-pad3_ u33
+a34 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u42-pad3_ u42
+a35 [net-_u49-pad2_ net-_u32-pad3_ ] net-_u55-pad3_ u55
+a36 [net-_u50-pad2_ net-_u33-pad3_ ] net-_u56-pad3_ u56
+a37 [net-_u51-pad2_ net-_u42-pad3_ ] net-_u57-pad3_ u57
+a38 net-_u59-pad1_ net-_u59-pad2_ u59
+a39 net-_u1-pad8_ net-_u26-pad2_ u26
+a40 net-_u25-pad2_ net-_u49-pad2_ u49
+a41 net-_u1-pad7_ net-_u25-pad2_ u25
+a42 net-_u26-pad2_ net-_u50-pad2_ u50
+a43 net-_u1-pad9_ net-_u27-pad2_ u27
+a44 net-_u27-pad2_ net-_u51-pad2_ u51
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u59 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74ALS280
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS280/SN74ALS280_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280_Previous_Values.xml
new file mode 100644
index 00000000..7cdfe1a7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/SN74ALS280_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v7 name="Source type">dc<field1 name="Value">0</field1></v7><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v8 name="Source type">dc<field1 name="Value">0</field1></v8><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v9 name="Source type">dc<field1 name="Value">0</field1></v9><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v3 name="Source type">dc<field1 name="Value">5</field1></v3></source><model><u13 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u15><u22 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u24><u31 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u31><u34 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u34><u16 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u17><u20 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u20><u25 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u26><u29 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u29><u32 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u32><u35 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u35><u18 name="type">d_and<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u19><u21 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u21><u27 name="type">d_nand<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_nand<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u28><u30 name="type">d_nand<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u30><u33 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u33><u36 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u36><u38 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u38><u37 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u37><u39 name="type">dac_bridge<field79 name="Enter value for out_low (default=0.0)" /><field80 name="Enter value for out_high (default=5.0)" /><field81 name="Enter value for out_undef (default=0.5)" /><field82 name="Enter value for input load (default=1.0e-12)" /><field83 name="Enter the Rise Time (default=1.0e-9)" /><field84 name="Enter the Fall Time (default=1.0e-9)" /></u39><u10 name="type">adc_bridge<field85 name="Enter value for in_low (default=1.0)" /><field86 name="Enter value for in_high (default=2.0)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /><field88 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">adc_bridge<field89 name="Enter value for in_low (default=1.0)" /><field90 name="Enter value for in_high (default=2.0)" /><field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">adc_bridge<field93 name="Enter value for in_low (default=1.0)" /><field94 name="Enter value for in_high (default=2.0)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /></u12><u17 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u17><u43 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u43><u16 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u16><u44 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u44><u18 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u18><u45 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u45><u28 name="type">d_and<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_and<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_and<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u30><u52 name="type">d_nand<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u52><u53 name="type">d_nand<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u53><u54 name="type">d_nand<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u54><u58 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u58><u20 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u20><u46 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u46><u19 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u19><u47 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u47><u21 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u21><u48 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u48><u32 name="type">d_and<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u32><u33 name="type">d_and<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u33><u42 name="type">d_and<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u42><u55 name="type">d_nand<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u55><u56 name="type">d_nand<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u56><u57 name="type">d_nand<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u57><u59 name="type">d_inverter<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u59><u26 name="type">d_inverter<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u26><u49 name="type">d_inverter<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u49><u25 name="type">d_inverter<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u25><u50 name="type">d_inverter<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u50><u27 name="type">d_inverter<field145 name="Enter Rise Delay (default=1.0e-9)" /><field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /></u27><u51 name="type">d_inverter<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u51></model><devicemodel /><subcircuit><x19><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x19><x22><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x22><x29><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x29><x30><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x30><x31><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x31><x32><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x32><x34><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x34><x25><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x25><x26><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x26><x27><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x27><x28><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x28><x33><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x33><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS280/analysis b/library/SubcircuitLibrary/SN74ALS280/analysis
new file mode 100644
index 00000000..cf94dd7f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS280/analysis
@@ -0,0 +1 @@
+.tran 0e-03 0e-00 0e-00
\ No newline at end of file