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| author | Sumanto Kar | 2024-11-21 21:32:09 +0530 |
|---|---|---|
| committer | Sumanto Kar | 2024-11-21 21:32:09 +0530 |
| commit | 2e48868406e15598a8986e12fc95396c6baa7d1f (patch) | |
| tree | dec3754d2eaa3fb77ab7385531d2bca2d92512d1 | |
| parent | b679f7c2f604e6ab0092b62165595843c1d122f0 (diff) | |
| download | eSim-2e48868406e15598a8986e12fc95396c6baa7d1f.tar.gz eSim-2e48868406e15598a8986e12fc95396c6baa7d1f.tar.bz2 eSim-2e48868406e15598a8986e12fc95396c6baa7d1f.zip | |
MC74HC238 is a 3-to-8 line decoder
16 files changed, 1949 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/MC74HC238/3_and-cache.lib b/library/SubcircuitLibrary/MC74HC238/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC74HC238/3_and.cir b/library/SubcircuitLibrary/MC74HC238/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC74HC238/3_and.cir.out b/library/SubcircuitLibrary/MC74HC238/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC74HC238/3_and.pro b/library/SubcircuitLibrary/MC74HC238/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/MC74HC238/3_and.sch b/library/SubcircuitLibrary/MC74HC238/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC74HC238/3_and.sub b/library/SubcircuitLibrary/MC74HC238/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC74HC238/3_and_Previous_Values.xml b/library/SubcircuitLibrary/MC74HC238/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238-cache.lib b/library/SubcircuitLibrary/MC74HC238/MC74HC238-cache.lib new file mode 100644 index 00000000..c42bbd93 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238-cache.lib @@ -0,0 +1,110 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir b/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir new file mode 100644 index 00000000..0c204b7c --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir @@ -0,0 +1,61 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC74HC238\MC74HC238.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/24 07:37:01 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U37 Net-_U21-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad7_ d_and +U21 Net-_U18-Pad2_ Net-_U21-Pad2_ d_inverter +U22 Net-_U17-Pad3_ Net-_U22-Pad2_ d_inverter +U38 Net-_U23-Pad2_ Net-_U24-Pad2_ Net-_U1-Pad8_ d_and +U23 Net-_U19-Pad2_ Net-_U23-Pad2_ d_inverter +U24 Net-_U17-Pad3_ Net-_U24-Pad2_ d_inverter +U39 Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U1-Pad9_ d_and +U25 Net-_U20-Pad2_ Net-_U25-Pad2_ d_inverter +U26 Net-_U17-Pad3_ Net-_U26-Pad2_ d_inverter +U40 Net-_U27-Pad2_ Net-_U28-Pad2_ Net-_U1-Pad10_ d_and +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter +U28 Net-_U17-Pad3_ Net-_U28-Pad2_ d_inverter +U41 Net-_U29-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad11_ d_and +U29 Net-_U29-Pad1_ Net-_U29-Pad2_ d_inverter +U30 Net-_U17-Pad3_ Net-_U30-Pad2_ d_inverter +U42 Net-_U31-Pad2_ Net-_U32-Pad2_ Net-_U1-Pad12_ d_and +U31 Net-_U31-Pad1_ Net-_U31-Pad2_ d_inverter +U32 Net-_U17-Pad3_ Net-_U32-Pad2_ d_inverter +U43 Net-_U33-Pad2_ Net-_U34-Pad2_ Net-_U1-Pad13_ d_and +U33 Net-_U33-Pad1_ Net-_U33-Pad2_ d_inverter +U34 Net-_U17-Pad3_ Net-_U34-Pad2_ d_inverter +U44 Net-_U35-Pad2_ Net-_U36-Pad2_ Net-_U1-Pad14_ d_and +U35 Net-_U35-Pad1_ Net-_U35-Pad2_ d_inverter +U36 Net-_U17-Pad3_ Net-_U36-Pad2_ d_inverter +U10 Net-_U1-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U1-Pad2_ Net-_U11-Pad2_ d_inverter +U12 Net-_U1-Pad3_ Net-_U12-Pad2_ d_inverter +U14 Net-_U10-Pad2_ Net-_U14-Pad2_ d_inverter +U15 Net-_U11-Pad2_ Net-_U15-Pad2_ d_inverter +U16 Net-_U12-Pad2_ Net-_U16-Pad2_ d_inverter +U17 Net-_U13-Pad3_ Net-_U1-Pad6_ Net-_U17-Pad3_ d_nand +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U8 Net-_U1-Pad4_ Net-_U13-Pad1_ d_inverter +U9 Net-_U1-Pad5_ Net-_U13-Pad2_ d_inverter +X1 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U18-Pad1_ 3_and +X2 Net-_U14-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U19-Pad1_ 3_and +X3 Net-_U10-Pad2_ Net-_U15-Pad2_ Net-_U12-Pad2_ Net-_U20-Pad1_ 3_and +X4 Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U12-Pad2_ Net-_U54-Pad1_ 3_and +X5 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U16-Pad2_ Net-_U55-Pad1_ 3_and +X6 Net-_U11-Pad2_ Net-_U16-Pad2_ Net-_U10-Pad2_ Net-_U56-Pad1_ 3_and +X8 Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U58-Pad1_ 3_and +X7 Net-_U10-Pad2_ Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U57-Pad1_ 3_and +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter +U54 Net-_U54-Pad1_ Net-_U27-Pad1_ d_inverter +U55 Net-_U55-Pad1_ Net-_U29-Pad1_ d_inverter +U56 Net-_U56-Pad1_ Net-_U31-Pad1_ d_inverter +U57 Net-_U57-Pad1_ Net-_U33-Pad1_ d_inverter +U58 Net-_U58-Pad1_ Net-_U35-Pad1_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir.out b/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir.out new file mode 100644 index 00000000..ed1f4eaf --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.cir.out @@ -0,0 +1,189 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc74hc238\mc74hc238.cir + +.include 3_and.sub +* u37 net-_u21-pad2_ net-_u22-pad2_ net-_u1-pad7_ d_and +* u21 net-_u18-pad2_ net-_u21-pad2_ d_inverter +* u22 net-_u17-pad3_ net-_u22-pad2_ d_inverter +* u38 net-_u23-pad2_ net-_u24-pad2_ net-_u1-pad8_ d_and +* u23 net-_u19-pad2_ net-_u23-pad2_ d_inverter +* u24 net-_u17-pad3_ net-_u24-pad2_ d_inverter +* u39 net-_u25-pad2_ net-_u26-pad2_ net-_u1-pad9_ d_and +* u25 net-_u20-pad2_ net-_u25-pad2_ d_inverter +* u26 net-_u17-pad3_ net-_u26-pad2_ d_inverter +* u40 net-_u27-pad2_ net-_u28-pad2_ net-_u1-pad10_ d_and +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u17-pad3_ net-_u28-pad2_ d_inverter +* u41 net-_u29-pad2_ net-_u30-pad2_ net-_u1-pad11_ d_and +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u30 net-_u17-pad3_ net-_u30-pad2_ d_inverter +* u42 net-_u31-pad2_ net-_u32-pad2_ net-_u1-pad12_ d_and +* u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter +* u32 net-_u17-pad3_ net-_u32-pad2_ d_inverter +* u43 net-_u33-pad2_ net-_u34-pad2_ net-_u1-pad13_ d_and +* u33 net-_u33-pad1_ net-_u33-pad2_ d_inverter +* u34 net-_u17-pad3_ net-_u34-pad2_ d_inverter +* u44 net-_u35-pad2_ net-_u36-pad2_ net-_u1-pad14_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u36 net-_u17-pad3_ net-_u36-pad2_ d_inverter +* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad2_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter +* u14 net-_u10-pad2_ net-_u14-pad2_ d_inverter +* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u16 net-_u12-pad2_ net-_u16-pad2_ d_inverter +* u17 net-_u13-pad3_ net-_u1-pad6_ net-_u17-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u8 net-_u1-pad4_ net-_u13-pad1_ d_inverter +* u9 net-_u1-pad5_ net-_u13-pad2_ d_inverter +x1 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u18-pad1_ 3_and +x2 net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u19-pad1_ 3_and +x3 net-_u10-pad2_ net-_u15-pad2_ net-_u12-pad2_ net-_u20-pad1_ 3_and +x4 net-_u14-pad2_ net-_u15-pad2_ net-_u12-pad2_ net-_u54-pad1_ 3_and +x5 net-_u10-pad2_ net-_u11-pad2_ net-_u16-pad2_ net-_u55-pad1_ 3_and +x6 net-_u11-pad2_ net-_u16-pad2_ net-_u10-pad2_ net-_u56-pad1_ 3_and +x8 net-_u14-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u58-pad1_ 3_and +x7 net-_u10-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u57-pad1_ 3_and +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u54 net-_u54-pad1_ net-_u27-pad1_ d_inverter +* u55 net-_u55-pad1_ net-_u29-pad1_ d_inverter +* u56 net-_u56-pad1_ net-_u31-pad1_ d_inverter +* u57 net-_u57-pad1_ net-_u33-pad1_ d_inverter +* u58 net-_u58-pad1_ net-_u35-pad1_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u21-pad2_ net-_u22-pad2_ ] net-_u1-pad7_ u37 +a2 net-_u18-pad2_ net-_u21-pad2_ u21 +a3 net-_u17-pad3_ net-_u22-pad2_ u22 +a4 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u1-pad8_ u38 +a5 net-_u19-pad2_ net-_u23-pad2_ u23 +a6 net-_u17-pad3_ net-_u24-pad2_ u24 +a7 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u1-pad9_ u39 +a8 net-_u20-pad2_ net-_u25-pad2_ u25 +a9 net-_u17-pad3_ net-_u26-pad2_ u26 +a10 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u1-pad10_ u40 +a11 net-_u27-pad1_ net-_u27-pad2_ u27 +a12 net-_u17-pad3_ net-_u28-pad2_ u28 +a13 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u1-pad11_ u41 +a14 net-_u29-pad1_ net-_u29-pad2_ u29 +a15 net-_u17-pad3_ net-_u30-pad2_ u30 +a16 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u1-pad12_ u42 +a17 net-_u31-pad1_ net-_u31-pad2_ u31 +a18 net-_u17-pad3_ net-_u32-pad2_ u32 +a19 [net-_u33-pad2_ net-_u34-pad2_ ] net-_u1-pad13_ u43 +a20 net-_u33-pad1_ net-_u33-pad2_ u33 +a21 net-_u17-pad3_ net-_u34-pad2_ u34 +a22 [net-_u35-pad2_ net-_u36-pad2_ ] net-_u1-pad14_ u44 +a23 net-_u35-pad1_ net-_u35-pad2_ u35 +a24 net-_u17-pad3_ net-_u36-pad2_ u36 +a25 net-_u1-pad1_ net-_u10-pad2_ u10 +a26 net-_u1-pad2_ net-_u11-pad2_ u11 +a27 net-_u1-pad3_ net-_u12-pad2_ u12 +a28 net-_u10-pad2_ net-_u14-pad2_ u14 +a29 net-_u11-pad2_ net-_u15-pad2_ u15 +a30 net-_u12-pad2_ net-_u16-pad2_ u16 +a31 [net-_u13-pad3_ net-_u1-pad6_ ] net-_u17-pad3_ u17 +a32 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a33 net-_u1-pad4_ net-_u13-pad1_ u8 +a34 net-_u1-pad5_ net-_u13-pad2_ u9 +a35 net-_u18-pad1_ net-_u18-pad2_ u18 +a36 net-_u19-pad1_ net-_u19-pad2_ u19 +a37 net-_u20-pad1_ net-_u20-pad2_ u20 +a38 net-_u54-pad1_ net-_u27-pad1_ u54 +a39 net-_u55-pad1_ net-_u29-pad1_ u55 +a40 net-_u56-pad1_ net-_u31-pad1_ u56 +a41 net-_u57-pad1_ net-_u33-pad1_ u57 +a42 net-_u58-pad1_ net-_u35-pad1_ u58 +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-03 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.pro b/library/SubcircuitLibrary/MC74HC238/MC74HC238.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.proj b/library/SubcircuitLibrary/MC74HC238/MC74HC238.proj new file mode 100644 index 00000000..41b4387c --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.proj @@ -0,0 +1 @@ +schematicFile 74238.sch diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.sch b/library/SubcircuitLibrary/MC74HC238/MC74HC238.sch new file mode 100644 index 00000000..57020d36 --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.sch @@ -0,0 +1,1048 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MC74HC238-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U37 +U 1 1 665E55B4 +P 10500 4450 +F 0 "U37" H 10500 4450 60 0000 C CNN +F 1 "d_and" H 10550 4550 60 0000 C CNN +F 2 "" H 10500 4450 60 0000 C CNN +F 3 "" H 10500 4450 60 0000 C CNN + 1 10500 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 665E560E +P 9750 4350 +F 0 "U21" H 9750 4250 60 0000 C CNN +F 1 "d_inverter" H 9750 4500 60 0000 C CNN +F 2 "" H 9800 4300 60 0000 C CNN +F 3 "" H 9800 4300 60 0000 C CNN + 1 9750 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 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+$Comp +L d_inverter U56 +U 1 1 665FD370 +P 7800 6700 +F 0 "U56" H 7800 6600 60 0000 C CNN +F 1 "d_inverter" H 7800 6850 60 0000 C CNN +F 2 "" H 7850 6650 60 0000 C CNN +F 3 "" H 7850 6650 60 0000 C CNN + 1 7800 6700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U57 +U 1 1 665FD46A +P 7800 7050 +F 0 "U57" H 7800 6950 60 0000 C CNN +F 1 "d_inverter" H 7800 7200 60 0000 C CNN +F 2 "" H 7850 7000 60 0000 C CNN +F 3 "" H 7850 7000 60 0000 C CNN + 1 7800 7050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U58 +U 1 1 665FD55F +P 7800 7400 +F 0 "U58" H 7800 7300 60 0000 C CNN +F 1 "d_inverter" H 7800 7550 60 0000 C CNN +F 2 "" H 7850 7350 60 0000 C CNN +F 3 "" H 7850 7350 60 0000 C CNN + 1 7800 7400 + 1 0 0 -1 +$EndComp +Connection ~ 9100 7500 +Connection ~ 8050 4800 +Wire Wire Line + 8100 6150 9250 6150 +Wire Wire Line + 9250 6150 9250 6100 +Wire Wire Line + 8100 6550 8100 6700 +Wire Wire Line + 8100 7050 8700 7050 +Wire Wire Line + 8700 7050 8700 6950 +$Comp +L PORT U1 +U 1 1 665E7D1A +P 3500 5700 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CNN +F 3 "" H 3500 6100 60 0000 C CNN + 5 3500 6100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 665E8482 +P 3500 6200 +F 0 "U1" H 3550 6300 30 0000 C CNN +F 1 "PORT" H 3500 6200 30 0000 C CNN +F 2 "" H 3500 6200 60 0000 C CNN +F 3 "" H 3500 6200 60 0000 C CNN + 6 3500 6200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 665E8A36 +P 11400 5500 +F 0 "U1" H 11450 5600 30 0000 C CNN +F 1 "PORT" H 11400 5500 30 0000 C CNN +F 2 "" H 11400 5500 60 0000 C CNN +F 3 "" H 11400 5500 60 0000 C CNN + 7 11400 5500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 665E8AC5 +P 11400 5600 +F 0 "U1" H 11450 5700 30 0000 C CNN +F 1 "PORT" H 11400 5600 30 0000 C CNN +F 2 "" H 11400 5600 60 0000 C CNN +F 3 "" H 11400 5600 60 0000 C CNN + 8 11400 5600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 665E8B52 +P 11400 5700 +F 0 "U1" H 11450 5800 30 0000 C CNN +F 1 "PORT" H 11400 5700 30 0000 C CNN +F 2 "" H 11400 5700 60 0000 C CNN +F 3 "" H 11400 5700 60 0000 C CNN + 9 11400 5700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 665E8BE1 +P 11400 5800 +F 0 "U1" H 11450 5900 30 0000 C CNN +F 1 "PORT" H 11400 5800 30 0000 C CNN +F 2 "" H 11400 5800 60 0000 C CNN +F 3 "" H 11400 5800 60 0000 C CNN + 10 11400 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 665E8C72 +P 11400 5900 +F 0 "U1" H 11450 6000 30 0000 C CNN +F 1 "PORT" H 11400 5900 30 0000 C CNN +F 2 "" H 11400 5900 60 0000 C CNN +F 3 "" H 11400 5900 60 0000 C CNN + 11 11400 5900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 665E8D05 +P 11400 6000 +F 0 "U1" H 11450 6100 30 0000 C CNN +F 1 "PORT" H 11400 6000 30 0000 C CNN +F 2 "" H 11400 6000 60 0000 C CNN +F 3 "" H 11400 6000 60 0000 C CNN + 12 11400 6000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 665E8D9A +P 11400 6100 +F 0 "U1" H 11450 6200 30 0000 C CNN +F 1 "PORT" H 11400 6100 30 0000 C CNN +F 2 "" H 11400 6100 60 0000 C CNN +F 3 "" H 11400 6100 60 0000 C CNN + 13 11400 6100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 665E8E31 +P 11400 6200 +F 0 "U1" H 11450 6300 30 0000 C CNN +F 1 "PORT" H 11400 6200 30 0000 C CNN +F 2 "" H 11400 6200 60 0000 C CNN +F 3 "" H 11400 6200 60 0000 C CNN + 14 11400 6200 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238.sub b/library/SubcircuitLibrary/MC74HC238/MC74HC238.sub new file mode 100644 index 00000000..b5c0662e --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238.sub @@ -0,0 +1,183 @@ +* Subcircuit MC74HC238 +.subckt MC74HC238 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\mc74hc238\mc74hc238.cir +.include 3_and.sub +* u37 net-_u21-pad2_ net-_u22-pad2_ net-_u1-pad7_ d_and +* u21 net-_u18-pad2_ net-_u21-pad2_ d_inverter +* u22 net-_u17-pad3_ net-_u22-pad2_ d_inverter +* u38 net-_u23-pad2_ net-_u24-pad2_ net-_u1-pad8_ d_and +* u23 net-_u19-pad2_ net-_u23-pad2_ d_inverter +* u24 net-_u17-pad3_ net-_u24-pad2_ d_inverter +* u39 net-_u25-pad2_ net-_u26-pad2_ net-_u1-pad9_ d_and +* u25 net-_u20-pad2_ net-_u25-pad2_ d_inverter +* u26 net-_u17-pad3_ net-_u26-pad2_ d_inverter +* u40 net-_u27-pad2_ net-_u28-pad2_ net-_u1-pad10_ d_and +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u17-pad3_ net-_u28-pad2_ d_inverter +* u41 net-_u29-pad2_ net-_u30-pad2_ net-_u1-pad11_ d_and +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u30 net-_u17-pad3_ net-_u30-pad2_ d_inverter +* u42 net-_u31-pad2_ net-_u32-pad2_ net-_u1-pad12_ d_and +* u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter +* u32 net-_u17-pad3_ net-_u32-pad2_ d_inverter +* u43 net-_u33-pad2_ net-_u34-pad2_ net-_u1-pad13_ d_and +* u33 net-_u33-pad1_ net-_u33-pad2_ d_inverter +* u34 net-_u17-pad3_ net-_u34-pad2_ d_inverter +* u44 net-_u35-pad2_ net-_u36-pad2_ net-_u1-pad14_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u36 net-_u17-pad3_ net-_u36-pad2_ d_inverter +* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad2_ net-_u11-pad2_ d_inverter +* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter +* u14 net-_u10-pad2_ net-_u14-pad2_ d_inverter +* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u16 net-_u12-pad2_ net-_u16-pad2_ d_inverter +* u17 net-_u13-pad3_ net-_u1-pad6_ net-_u17-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u8 net-_u1-pad4_ net-_u13-pad1_ d_inverter +* u9 net-_u1-pad5_ net-_u13-pad2_ d_inverter +x1 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u18-pad1_ 3_and +x2 net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u19-pad1_ 3_and +x3 net-_u10-pad2_ net-_u15-pad2_ net-_u12-pad2_ net-_u20-pad1_ 3_and +x4 net-_u14-pad2_ net-_u15-pad2_ net-_u12-pad2_ net-_u54-pad1_ 3_and +x5 net-_u10-pad2_ net-_u11-pad2_ net-_u16-pad2_ net-_u55-pad1_ 3_and +x6 net-_u11-pad2_ net-_u16-pad2_ net-_u10-pad2_ net-_u56-pad1_ 3_and +x8 net-_u14-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u58-pad1_ 3_and +x7 net-_u10-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u57-pad1_ 3_and +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u54 net-_u54-pad1_ net-_u27-pad1_ d_inverter +* u55 net-_u55-pad1_ net-_u29-pad1_ d_inverter +* u56 net-_u56-pad1_ net-_u31-pad1_ d_inverter +* u57 net-_u57-pad1_ net-_u33-pad1_ d_inverter +* u58 net-_u58-pad1_ net-_u35-pad1_ d_inverter +a1 [net-_u21-pad2_ net-_u22-pad2_ ] net-_u1-pad7_ u37 +a2 net-_u18-pad2_ net-_u21-pad2_ u21 +a3 net-_u17-pad3_ net-_u22-pad2_ u22 +a4 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u1-pad8_ u38 +a5 net-_u19-pad2_ net-_u23-pad2_ u23 +a6 net-_u17-pad3_ net-_u24-pad2_ u24 +a7 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u1-pad9_ u39 +a8 net-_u20-pad2_ net-_u25-pad2_ u25 +a9 net-_u17-pad3_ net-_u26-pad2_ u26 +a10 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u1-pad10_ u40 +a11 net-_u27-pad1_ net-_u27-pad2_ u27 +a12 net-_u17-pad3_ net-_u28-pad2_ u28 +a13 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u1-pad11_ u41 +a14 net-_u29-pad1_ net-_u29-pad2_ u29 +a15 net-_u17-pad3_ net-_u30-pad2_ u30 +a16 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u1-pad12_ u42 +a17 net-_u31-pad1_ net-_u31-pad2_ u31 +a18 net-_u17-pad3_ net-_u32-pad2_ u32 +a19 [net-_u33-pad2_ net-_u34-pad2_ ] net-_u1-pad13_ u43 +a20 net-_u33-pad1_ net-_u33-pad2_ u33 +a21 net-_u17-pad3_ net-_u34-pad2_ u34 +a22 [net-_u35-pad2_ net-_u36-pad2_ ] net-_u1-pad14_ u44 +a23 net-_u35-pad1_ net-_u35-pad2_ u35 +a24 net-_u17-pad3_ net-_u36-pad2_ u36 +a25 net-_u1-pad1_ net-_u10-pad2_ u10 +a26 net-_u1-pad2_ net-_u11-pad2_ u11 +a27 net-_u1-pad3_ net-_u12-pad2_ u12 +a28 net-_u10-pad2_ net-_u14-pad2_ u14 +a29 net-_u11-pad2_ net-_u15-pad2_ u15 +a30 net-_u12-pad2_ net-_u16-pad2_ u16 +a31 [net-_u13-pad3_ net-_u1-pad6_ ] net-_u17-pad3_ u17 +a32 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a33 net-_u1-pad4_ net-_u13-pad1_ u8 +a34 net-_u1-pad5_ net-_u13-pad2_ u9 +a35 net-_u18-pad1_ net-_u18-pad2_ u18 +a36 net-_u19-pad1_ net-_u19-pad2_ u19 +a37 net-_u20-pad1_ net-_u20-pad2_ u20 +a38 net-_u54-pad1_ net-_u27-pad1_ u54 +a39 net-_u55-pad1_ net-_u29-pad1_ u55 +a40 net-_u56-pad1_ net-_u31-pad1_ u56 +a41 net-_u57-pad1_ net-_u33-pad1_ u57 +a42 net-_u58-pad1_ net-_u35-pad1_ u58 +* Schematic Name: d_and, NgSpice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends MC74HC238
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC74HC238/MC74HC238_Previous_Values.xml b/library/SubcircuitLibrary/MC74HC238/MC74HC238_Previous_Values.xml new file mode 100644 index 00000000..c73b3abe --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/MC74HC238_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v6 name="Source type">dc<field1 name="Value">5</field1></v6></source><model><u37 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u37><u21 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u22><u38 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u38><u23 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u24><u39 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u39><u25 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u26><u40 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u40><u27 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u28><u41 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u41><u29 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u30><u42 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u42><u31 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u32><u43 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u43><u33 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u33><u34 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u34><u44 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u44><u35 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u35><u36 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u36><u10 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u12><u14 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_nand<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u17><u13 name="type">d_and<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u13><u8 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u9><u45 name="type">dac_bridge<field103 name="Enter value for out_low (default=0.0)" /><field104 name="Enter value for out_high (default=5.0)" /><field105 name="Enter value for out_undef (default=0.5)" /><field106 name="Enter value for input load (default=1.0e-12)" /><field107 name="Enter the Rise Time (default=1.0e-9)" /><field108 name="Enter the Fall Time (default=1.0e-9)" /></u45><u7 name="type">adc_bridge<field109 name="Enter value for in_low (default=1.0)" /><field110 name="Enter value for in_high (default=2.0)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /><field112 name="Enter Fall Delay (default=1.0e-9)" /></u7><u18 name="type">d_inverter<field113 name="Enter Rise Delay (default=1.0e-9)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /><field115 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_inverter<field116 name="Enter Rise Delay (default=1.0e-9)" /><field117 name="Enter Fall Delay (default=1.0e-9)" /><field118 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_inverter<field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /><field121 name="Enter Input Load (default=1.0e-12)" /></u20><u54 name="type">d_inverter<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u54><u55 name="type">d_inverter<field125 name="Enter Rise Delay (default=1.0e-9)" /><field126 name="Enter Fall Delay (default=1.0e-9)" /><field127 name="Enter Input Load (default=1.0e-12)" /></u55><u56 name="type">d_inverter<field128 name="Enter Rise Delay (default=1.0e-9)" /><field129 name="Enter Fall Delay (default=1.0e-9)" /><field130 name="Enter Input Load (default=1.0e-12)" /></u56><u57 name="type">d_inverter<field131 name="Enter Rise Delay (default=1.0e-9)" /><field132 name="Enter Fall Delay (default=1.0e-9)" /><field133 name="Enter Input Load (default=1.0e-12)" /></u57><u58 name="type">d_inverter<field134 name="Enter Rise Delay (default=1.0e-9)" /><field135 name="Enter Fall Delay (default=1.0e-9)" /><field136 name="Enter Input Load (default=1.0e-12)" /></u58></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC74HC238/analysis b/library/SubcircuitLibrary/MC74HC238/analysis new file mode 100644 index 00000000..cf94dd7f --- /dev/null +++ b/library/SubcircuitLibrary/MC74HC238/analysis @@ -0,0 +1 @@ +.tran 0e-03 0e-00 0e-00
\ No newline at end of file |