diff options
author | Sumanto Kar | 2024-11-21 20:48:19 +0530 |
---|---|---|
committer | Sumanto Kar | 2024-11-21 20:48:19 +0530 |
commit | ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3 (patch) | |
tree | 6affc84ae61bd25a629881ba5b61c947b6cacf3d /library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch | |
parent | eacf5ca52184c22dfb8f9e01789acda4ab96dcf3 (diff) | |
download | eSim-ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3.tar.gz eSim-ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3.tar.bz2 eSim-ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3.zip |
SN7483A is a 4-bit binary full adder
Diffstat (limited to 'library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch')
-rw-r--r-- | library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch | 1136 |
1 files changed, 1136 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch new file mode 100644 index 00000000..4987c996 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch @@ -0,0 +1,1136 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN7483A-cache +EELAYER 25 0 +EELAYER END +$Descr User 27559 19685 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_buffer U23 +U 1 1 666AB8B2 +P 14450 3100 +F 0 "U23" H 14450 3050 60 0000 C CNN +F 1 "d_buffer" H 14450 3150 60 0000 C CNN +F 2 "" H 14450 3100 60 0000 C CNN +F 3 "" H 14450 3100 60 0000 C CNN + 1 14450 3100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 666AB8B3 +P 14450 3750 +F 0 "U24" H 14450 3750 60 0000 C CNN +F 1 "d_and" H 14500 3850 60 0000 C CNN +F 2 "" H 14450 3750 60 0000 C CNN +F 3 "" H 14450 3750 60 0000 C CNN + 1 14450 3750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 666AB8B4 +P 14350 4350 +F 0 "X1" H 14450 4300 60 0000 C CNN +F 1 "3_and" H 14500 4500 60 0000 C CNN +F 2 "" H 14350 4350 60 0000 C CNN +F 3 "" H 14350 4350 60 0000 C CNN + 1 14350 4350 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 666AB8B5 +P 14400 4950 +F 0 "X2" H 14450 4900 60 0000 C CNN +F 1 "4_and" H 14500 5050 60 0000 C CNN +F 2 "" H 14400 4950 60 0000 C CNN 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