diff options
| author | Sumanto Kar | 2024-11-21 20:48:19 +0530 |
|---|---|---|
| committer | Sumanto Kar | 2024-11-21 20:48:19 +0530 |
| commit | ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3 (patch) | |
| tree | 6affc84ae61bd25a629881ba5b61c947b6cacf3d | |
| parent | eacf5ca52184c22dfb8f9e01789acda4ab96dcf3 (diff) | |
| download | eSim-ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3.tar.gz eSim-ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3.tar.bz2 eSim-ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3.zip | |
SN7483A is a 4-bit binary full adder
38 files changed, 3270 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and-cache.lib b/library/SubcircuitLibrary/SN7483A_sub/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.cir b/library/SubcircuitLibrary/SN7483A_sub/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out b/library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.pro b/library/SubcircuitLibrary/SN7483A_sub/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.sch b/library/SubcircuitLibrary/SN7483A_sub/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and.sub b/library/SubcircuitLibrary/SN7483A_sub/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7483A_sub/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN7483A_sub/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR-cache.lib b/library/SubcircuitLibrary/SN7483A_sub/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.pro b/library/SubcircuitLibrary/SN7483A_sub/4_OR.pro new file mode 100644 index 00000000..881563eb --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.sch b/library/SubcircuitLibrary/SN7483A_sub/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.sub b/library/SubcircuitLibrary/SN7483A_sub/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN7483A_sub/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and-cache.lib b/library/SubcircuitLibrary/SN7483A_sub/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and-rescue.lib b/library/SubcircuitLibrary/SN7483A_sub/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and.cir b/library/SubcircuitLibrary/SN7483A_sub/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and.cir.out b/library/SubcircuitLibrary/SN7483A_sub/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and.pro b/library/SubcircuitLibrary/SN7483A_sub/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and.sch b/library/SubcircuitLibrary/SN7483A_sub/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and.sub b/library/SubcircuitLibrary/SN7483A_sub/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN7483A_sub/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and-cache.lib b/library/SubcircuitLibrary/SN7483A_sub/5_and-cache.lib new file mode 100644 index 00000000..fc177c1f --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and-rescue.lib b/library/SubcircuitLibrary/SN7483A_sub/5_and-rescue.lib new file mode 100644 index 00000000..483b8efb --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and.cir b/library/SubcircuitLibrary/SN7483A_sub/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and.cir.out b/library/SubcircuitLibrary/SN7483A_sub/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and.pro b/library/SubcircuitLibrary/SN7483A_sub/5_and.pro new file mode 100644 index 00000000..c16a3f85 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and.sch b/library/SubcircuitLibrary/SN7483A_sub/5_and.sch new file mode 100644 index 00000000..aef3c043 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and.sub b/library/SubcircuitLibrary/SN7483A_sub/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7483A_sub/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN7483A_sub/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub-cache.lib b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub-cache.lib new file mode 100644 index 00000000..45a4afe5 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub-cache.lib @@ -0,0 +1,306 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_5 +# +DEF dac_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir new file mode 100644 index 00000000..42089f0f --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir @@ -0,0 +1,60 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN7483A_sub\SN7483A_sub.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 13/06/2024 2:46:07 PM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U23 Net-_U12-Pad3_ Net-_U23-Pad2_ d_buffer +U24 Net-_U15-Pad1_ Net-_U11-Pad3_ Net-_U24-Pad3_ d_and +X1 Net-_U13-Pad1_ Net-_U11-Pad3_ Net-_U21-Pad1_ Net-_X1-Pad4_ 3_and +X2 Net-_U14-Pad1_ Net-_U11-Pad3_ Net-_U21-Pad1_ Net-_U17-Pad1_ Net-_X2-Pad5_ 4_and +X4 Net-_U11-Pad3_ Net-_U21-Pad1_ Net-_U17-Pad1_ Net-_U19-Pad1_ Net-_U10-Pad2_ Net-_U36-Pad2_ 5_and +X8 Net-_U23-Pad2_ Net-_U24-Pad3_ Net-_X1-Pad4_ Net-_X2-Pad5_ Net-_U36-Pad1_ 4_OR +U36 Net-_U36-Pad1_ Net-_U36-Pad2_ Net-_U36-Pad3_ d_or +U40 Net-_U36-Pad3_ Net-_U40-Pad2_ d_inverter +U26 Net-_U11-Pad3_ Net-_U16-Pad2_ Net-_U26-Pad3_ d_and +U16 Net-_U12-Pad3_ Net-_U16-Pad2_ d_inverter +U27 Net-_U15-Pad1_ Net-_U27-Pad2_ d_buffer +U29 Net-_U13-Pad1_ Net-_U21-Pad1_ Net-_U29-Pad3_ d_and +X5 Net-_U14-Pad1_ Net-_U21-Pad1_ Net-_U17-Pad1_ Net-_X5-Pad4_ 3_and +X6 Net-_U21-Pad1_ Net-_U17-Pad1_ Net-_U19-Pad1_ Net-_U10-Pad2_ Net-_X6-Pad5_ 4_and +X7 Net-_U27-Pad2_ Net-_U29-Pad3_ Net-_X5-Pad4_ Net-_X6-Pad5_ Net-_U35-Pad1_ 4_OR +U35 Net-_U35-Pad1_ Net-_U35-Pad2_ d_inverter +U39 Net-_U26-Pad3_ Net-_U35-Pad2_ Net-_U39-Pad3_ d_xor +U21 Net-_U21-Pad1_ Net-_U15-Pad2_ Net-_U21-Pad3_ d_and +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U22 Net-_U13-Pad1_ Net-_U22-Pad2_ d_buffer +U28 Net-_U14-Pad1_ Net-_U17-Pad1_ Net-_U28-Pad3_ d_and +X3 Net-_U17-Pad1_ Net-_U19-Pad1_ Net-_U10-Pad2_ Net-_U33-Pad2_ 3_and +U30 Net-_U22-Pad2_ Net-_U28-Pad3_ Net-_U30-Pad3_ d_or +U33 Net-_U30-Pad3_ Net-_U33-Pad2_ Net-_U33-Pad3_ d_or +U41 Net-_U21-Pad3_ Net-_U37-Pad2_ Net-_U41-Pad3_ d_xor +U17 Net-_U17-Pad1_ Net-_U13-Pad2_ Net-_U17-Pad3_ d_and +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U18 Net-_U14-Pad1_ Net-_U18-Pad2_ d_buffer +U25 Net-_U19-Pad1_ Net-_U10-Pad2_ Net-_U25-Pad3_ d_and +U19 Net-_U19-Pad1_ Net-_U14-Pad2_ Net-_U19-Pad3_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U34 Net-_U31-Pad3_ Net-_U34-Pad2_ d_inverter +U38 Net-_U17-Pad3_ Net-_U34-Pad2_ Net-_U38-Pad3_ d_xor +U32 Net-_U19-Pad3_ Net-_U20-Pad2_ Net-_U32-Pad3_ d_xor +U31 Net-_U18-Pad2_ Net-_U25-Pad3_ Net-_U31-Pad3_ d_or +U20 Net-_U10-Pad2_ Net-_U20-Pad2_ d_inverter +U37 Net-_U33-Pad3_ Net-_U37-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand +U12 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U12-Pad3_ d_nor +U8 Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U21-Pad1_ d_nand +U9 Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U15-Pad1_ d_nor +U4 Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U17-Pad1_ d_nand +U5 Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U13-Pad1_ d_nor +U6 Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U19-Pad1_ d_nand +U7 Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U14-Pad1_ d_nor +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad8_ Net-_U1-Pad14_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ adc_bridge_8 +U3 Net-_U1-Pad7_ Net-_U10-Pad1_ adc_bridge_1 +U42 Net-_U40-Pad2_ Net-_U39-Pad3_ Net-_U41-Pad3_ Net-_U38-Pad3_ Net-_U32-Pad3_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U1-Pad1_ Net-_U1-Pad4_ dac_bridge_5 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir.out b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir.out new file mode 100644 index 00000000..4230bedc --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.cir.out @@ -0,0 +1,188 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn7483a_sub\sn7483a_sub.cir + +.include 3_and.sub +.include 4_OR.sub +.include 4_and.sub +.include 5_and.sub +* u23 net-_u12-pad3_ net-_u23-pad2_ d_buffer +* u24 net-_u15-pad1_ net-_u11-pad3_ net-_u24-pad3_ d_and +x1 net-_u13-pad1_ net-_u11-pad3_ net-_u21-pad1_ net-_x1-pad4_ 3_and +x2 net-_u14-pad1_ net-_u11-pad3_ net-_u21-pad1_ net-_u17-pad1_ net-_x2-pad5_ 4_and +x4 net-_u11-pad3_ net-_u21-pad1_ net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_u36-pad2_ 5_and +x8 net-_u23-pad2_ net-_u24-pad3_ net-_x1-pad4_ net-_x2-pad5_ net-_u36-pad1_ 4_OR +* u36 net-_u36-pad1_ net-_u36-pad2_ net-_u36-pad3_ d_or +* u40 net-_u36-pad3_ net-_u40-pad2_ d_inverter +* u26 net-_u11-pad3_ net-_u16-pad2_ net-_u26-pad3_ d_and +* u16 net-_u12-pad3_ net-_u16-pad2_ d_inverter +* u27 net-_u15-pad1_ net-_u27-pad2_ d_buffer +* u29 net-_u13-pad1_ net-_u21-pad1_ net-_u29-pad3_ d_and +x5 net-_u14-pad1_ net-_u21-pad1_ net-_u17-pad1_ net-_x5-pad4_ 3_and +x6 net-_u21-pad1_ net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_x6-pad5_ 4_and +x7 net-_u27-pad2_ net-_u29-pad3_ net-_x5-pad4_ net-_x6-pad5_ net-_u35-pad1_ 4_OR +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u39 net-_u26-pad3_ net-_u35-pad2_ net-_u39-pad3_ d_xor +* u21 net-_u21-pad1_ net-_u15-pad2_ net-_u21-pad3_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u22 net-_u13-pad1_ net-_u22-pad2_ d_buffer +* u28 net-_u14-pad1_ net-_u17-pad1_ net-_u28-pad3_ d_and +x3 net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_u33-pad2_ 3_and +* u30 net-_u22-pad2_ net-_u28-pad3_ net-_u30-pad3_ d_or +* u33 net-_u30-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or +* u41 net-_u21-pad3_ net-_u37-pad2_ net-_u41-pad3_ d_xor +* u17 net-_u17-pad1_ net-_u13-pad2_ net-_u17-pad3_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u18 net-_u14-pad1_ net-_u18-pad2_ d_buffer +* u25 net-_u19-pad1_ net-_u10-pad2_ net-_u25-pad3_ d_and +* u19 net-_u19-pad1_ net-_u14-pad2_ net-_u19-pad3_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u34 net-_u31-pad3_ net-_u34-pad2_ d_inverter +* u38 net-_u17-pad3_ net-_u34-pad2_ net-_u38-pad3_ d_xor +* u32 net-_u19-pad3_ net-_u20-pad2_ net-_u32-pad3_ d_xor +* u31 net-_u18-pad2_ net-_u25-pad3_ net-_u31-pad3_ d_or +* u20 net-_u10-pad2_ net-_u20-pad2_ d_inverter +* u37 net-_u33-pad3_ net-_u37-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u12 net-_u11-pad1_ net-_u11-pad2_ net-_u12-pad3_ d_nor +* u8 net-_u2-pad11_ net-_u2-pad12_ net-_u21-pad1_ d_nand +* u9 net-_u2-pad11_ net-_u2-pad12_ net-_u15-pad1_ d_nor +* u4 net-_u2-pad13_ net-_u2-pad14_ net-_u17-pad1_ d_nand +* u5 net-_u2-pad13_ net-_u2-pad14_ net-_u13-pad1_ d_nor +* u6 net-_u2-pad15_ net-_u2-pad16_ net-_u19-pad1_ d_nand +* u7 net-_u2-pad15_ net-_u2-pad16_ net-_u14-pad1_ d_nor +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad8_ net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ net-_u11-pad1_ net-_u11-pad2_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8 +* u3 net-_u1-pad7_ net-_u10-pad1_ adc_bridge_1 +* u42 net-_u40-pad2_ net-_u39-pad3_ net-_u41-pad3_ net-_u38-pad3_ net-_u32-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad1_ net-_u1-pad4_ dac_bridge_5 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 net-_u12-pad3_ net-_u23-pad2_ u23 +a2 [net-_u15-pad1_ net-_u11-pad3_ ] net-_u24-pad3_ u24 +a3 [net-_u36-pad1_ net-_u36-pad2_ ] net-_u36-pad3_ u36 +a4 net-_u36-pad3_ net-_u40-pad2_ u40 +a5 [net-_u11-pad3_ net-_u16-pad2_ ] net-_u26-pad3_ u26 +a6 net-_u12-pad3_ net-_u16-pad2_ u16 +a7 net-_u15-pad1_ net-_u27-pad2_ u27 +a8 [net-_u13-pad1_ net-_u21-pad1_ ] net-_u29-pad3_ u29 +a9 net-_u35-pad1_ net-_u35-pad2_ u35 +a10 [net-_u26-pad3_ net-_u35-pad2_ ] net-_u39-pad3_ u39 +a11 [net-_u21-pad1_ net-_u15-pad2_ ] net-_u21-pad3_ u21 +a12 net-_u15-pad1_ net-_u15-pad2_ u15 +a13 net-_u13-pad1_ net-_u22-pad2_ u22 +a14 [net-_u14-pad1_ net-_u17-pad1_ ] net-_u28-pad3_ u28 +a15 [net-_u22-pad2_ net-_u28-pad3_ ] net-_u30-pad3_ u30 +a16 [net-_u30-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33 +a17 [net-_u21-pad3_ net-_u37-pad2_ ] net-_u41-pad3_ u41 +a18 [net-_u17-pad1_ net-_u13-pad2_ ] net-_u17-pad3_ u17 +a19 net-_u13-pad1_ net-_u13-pad2_ u13 +a20 net-_u14-pad1_ net-_u18-pad2_ u18 +a21 [net-_u19-pad1_ net-_u10-pad2_ ] net-_u25-pad3_ u25 +a22 [net-_u19-pad1_ net-_u14-pad2_ ] net-_u19-pad3_ u19 +a23 net-_u14-pad1_ net-_u14-pad2_ u14 +a24 net-_u31-pad3_ net-_u34-pad2_ u34 +a25 [net-_u17-pad3_ net-_u34-pad2_ ] net-_u38-pad3_ u38 +a26 [net-_u19-pad3_ net-_u20-pad2_ ] net-_u32-pad3_ u32 +a27 [net-_u18-pad2_ net-_u25-pad3_ ] net-_u31-pad3_ u31 +a28 net-_u10-pad2_ net-_u20-pad2_ u20 +a29 net-_u33-pad3_ net-_u37-pad2_ u37 +a30 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a31 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u12-pad3_ u12 +a32 [net-_u2-pad11_ net-_u2-pad12_ ] net-_u21-pad1_ u8 +a33 [net-_u2-pad11_ net-_u2-pad12_ ] net-_u15-pad1_ u9 +a34 [net-_u2-pad13_ net-_u2-pad14_ ] net-_u17-pad1_ u4 +a35 [net-_u2-pad13_ net-_u2-pad14_ ] net-_u13-pad1_ u5 +a36 [net-_u2-pad15_ net-_u2-pad16_ ] net-_u19-pad1_ u6 +a37 [net-_u2-pad15_ net-_u2-pad16_ ] net-_u14-pad1_ u7 +a38 net-_u10-pad1_ net-_u10-pad2_ u10 +a39 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad8_ net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ ] [net-_u11-pad1_ net-_u11-pad2_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2 +a40 [net-_u1-pad7_ ] [net-_u10-pad1_ ] u3 +a41 [net-_u40-pad2_ net-_u39-pad3_ net-_u41-pad3_ net-_u38-pad3_ net-_u32-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad1_ net-_u1-pad4_ ] u42 +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u39 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u30 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u41 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u38 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u32 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u42 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.pro b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch new file mode 100644 index 00000000..4987c996 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sch @@ -0,0 +1,1136 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN7483A-cache +EELAYER 25 0 +EELAYER END +$Descr User 27559 19685 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_buffer U23 +U 1 1 666AB8B2 +P 14450 3100 +F 0 "U23" H 14450 3050 60 0000 C CNN +F 1 "d_buffer" H 14450 3150 60 0000 C CNN +F 2 "" H 14450 3100 60 0000 C CNN +F 3 "" H 14450 3100 60 0000 C CNN + 1 14450 3100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 666AB8B3 +P 14450 3750 +F 0 "U24" H 14450 3750 60 0000 C CNN +F 1 "d_and" H 14500 3850 60 0000 C CNN +F 2 "" H 14450 3750 60 0000 C CNN +F 3 "" H 14450 3750 60 0000 C CNN + 1 14450 3750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 666AB8B4 +P 14350 4350 +F 0 "X1" H 14450 4300 60 0000 C CNN +F 1 "3_and" H 14500 4500 60 0000 C CNN +F 2 "" H 14350 4350 60 0000 C CNN +F 3 "" H 14350 4350 60 0000 C CNN + 1 14350 4350 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X2 +U 1 1 666AB8B5 +P 14400 4950 +F 0 "X2" H 14450 4900 60 0000 C CNN +F 1 "4_and" H 14500 5050 60 0000 C CNN +F 2 "" H 14400 4950 60 0000 C CNN +F 3 "" H 14400 4950 60 0000 C CNN + 1 14400 4950 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X4 +U 1 1 666AB8B6 +P 14450 5700 +F 0 "X4" H 14500 5600 60 0000 C CNN +F 1 "5_and" H 14550 5850 60 0000 C CNN +F 2 "" H 14450 5700 60 0000 C CNN +F 3 "" H 14450 5700 60 0000 C CNN + 1 14450 5700 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X8 +U 1 1 666AB8B7 +P 16400 4200 +F 0 "X8" H 16550 4100 60 0000 C CNN +F 1 "4_OR" H 16550 4300 60 0000 C CNN +F 2 "" H 16400 4200 60 0000 C CNN +F 3 "" H 16400 4200 60 0000 C CNN + 1 16400 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U36 +U 1 1 666AB8B8 +P 17500 4600 +F 0 "U36" H 17500 4600 60 0000 C CNN +F 1 "d_or" H 17500 4700 60 0000 C CNN +F 2 "" H 17500 4600 60 0000 C CNN +F 3 "" H 17500 4600 60 0000 C CNN + 1 17500 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U40 +U 1 1 666AB8B9 +P 18500 4550 +F 0 "U40" H 18500 4450 60 0000 C CNN +F 1 "d_inverter" H 18500 4700 60 0000 C CNN +F 2 "" H 18550 4500 60 0000 C CNN +F 3 "" H 18550 4500 60 0000 C CNN + 1 18500 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 666AB8BA +P 14500 7100 +F 0 "U26" H 14500 7100 60 0000 C CNN +F 1 "d_and" H 14550 7200 60 0000 C CNN +F 2 "" H 14500 7100 60 0000 C CNN +F 3 "" H 14500 7100 60 0000 C CNN + 1 14500 7100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 666AB8BB +P 13450 7100 +F 0 "U16" H 13450 7000 60 0000 C CNN +F 1 "d_inverter" H 13450 7250 60 0000 C CNN +F 2 "" H 13500 7050 60 0000 C CNN +F 3 "" H 13500 7050 60 0000 C CNN + 1 13450 7100 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U27 +U 1 1 666AB8BC +P 14500 7600 +F 0 "U27" H 14500 7550 60 0000 C CNN +F 1 "d_buffer" H 14500 7650 60 0000 C CNN +F 2 "" H 14500 7600 60 0000 C CNN +F 3 "" H 14500 7600 60 0000 C CNN + 1 14500 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U29 +U 1 1 666AB8BD +P 14550 8250 +F 0 "U29" H 14550 8250 60 0000 C CNN +F 1 "d_and" H 14600 8350 60 0000 C CNN +F 2 "" H 14550 8250 60 0000 C CNN +F 3 "" H 14550 8250 60 0000 C CNN + 1 14550 8250 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 666AB8BE +P 14500 8800 +F 0 "X5" H 14600 8750 60 0000 C CNN +F 1 "3_and" H 14650 8950 60 0000 C CNN +F 2 "" H 14500 8800 60 0000 C CNN +F 3 "" H 14500 8800 60 0000 C CNN + 1 14500 8800 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 666AB8BF +P 14550 9350 +F 0 "X6" H 14600 9300 60 0000 C CNN +F 1 "4_and" H 14650 9450 60 0000 C CNN +F 2 "" H 14550 9350 60 0000 C CNN +F 3 "" H 14550 9350 60 0000 C CNN + 1 14550 9350 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X7 +U 1 1 666AB8C0 +P 16200 8450 +F 0 "X7" H 16350 8350 60 0000 C CNN +F 1 "4_OR" H 16350 8550 60 0000 C CNN +F 2 "" H 16200 8450 60 0000 C CNN +F 3 "" H 16200 8450 60 0000 C CNN + 1 16200 8450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 666AB8C1 +P 17200 8450 +F 0 "U35" H 17200 8350 60 0000 C CNN +F 1 "d_inverter" H 17200 8600 60 0000 C CNN +F 2 "" H 17250 8400 60 0000 C CNN +F 3 "" H 17250 8400 60 0000 C CNN + 1 17200 8450 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U39 +U 1 1 666AB8C2 +P 18150 7800 +F 0 "U39" H 18150 7800 60 0000 C CNN +F 1 "d_xor" H 18200 7900 47 0000 C CNN +F 2 "" H 18150 7800 60 0000 C CNN +F 3 "" H 18150 7800 60 0000 C CNN + 1 18150 7800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 666AB8C3 +P 14400 10350 +F 0 "U21" H 14400 10350 60 0000 C CNN +F 1 "d_and" H 14450 10450 60 0000 C CNN +F 2 "" H 14400 10350 60 0000 C CNN +F 3 "" H 14400 10350 60 0000 C CNN + 1 14400 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 666AB8C4 +P 13350 10350 +F 0 "U15" H 13350 10250 60 0000 C CNN +F 1 "d_inverter" H 13350 10500 60 0000 C CNN +F 2 "" H 13400 10300 60 0000 C CNN +F 3 "" H 13400 10300 60 0000 C CNN + 1 13350 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U22 +U 1 1 666AB8C5 +P 14400 10900 +F 0 "U22" H 14400 10850 60 0000 C CNN +F 1 "d_buffer" H 14400 10950 60 0000 C CNN +F 2 "" H 14400 10900 60 0000 C CNN +F 3 "" H 14400 10900 60 0000 C CNN + 1 14400 10900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U28 +U 1 1 666AB8C6 +P 14500 11550 +F 0 "U28" H 14500 11550 60 0000 C CNN +F 1 "d_and" H 14550 11650 60 0000 C CNN +F 2 "" H 14500 11550 60 0000 C CNN +F 3 "" H 14500 11550 60 0000 C CNN + 1 14500 11550 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 666AB8C7 +P 14400 12050 +F 0 "X3" H 14500 12000 60 0000 C CNN +F 1 "3_and" H 14550 12200 60 0000 C CNN +F 2 "" H 14400 12050 60 0000 C CNN +F 3 "" H 14400 12050 60 0000 C CNN + 1 14400 12050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U30 +U 1 1 666AB8C8 +P 16050 11350 +F 0 "U30" H 16050 11350 60 0000 C CNN +F 1 "d_or" H 16050 11450 60 0000 C CNN +F 2 "" H 16050 11350 60 0000 C CNN +F 3 "" H 16050 11350 60 0000 C CNN + 1 16050 11350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U33 +U 1 1 666AB8C9 +P 17050 11600 +F 0 "U33" H 17050 11600 60 0000 C CNN +F 1 "d_or" H 17050 11700 60 0000 C CNN +F 2 "" H 17050 11600 60 0000 C CNN +F 3 "" H 17050 11600 60 0000 C CNN + 1 17050 11600 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U41 +U 1 1 666AB8CA +P 18950 10650 +F 0 "U41" H 18950 10650 60 0000 C CNN +F 1 "d_xor" H 19000 10750 47 0000 C CNN +F 2 "" H 18950 10650 60 0000 C CNN +F 3 "" H 18950 10650 60 0000 C CNN + 1 18950 10650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 666AB8CB +P 14350 13000 +F 0 "U17" H 14350 13000 60 0000 C CNN +F 1 "d_and" H 14400 13100 60 0000 C CNN +F 2 "" H 14350 13000 60 0000 C CNN +F 3 "" H 14350 13000 60 0000 C CNN + 1 14350 13000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 666AB8CC +P 13300 13000 +F 0 "U13" H 13300 12900 60 0000 C CNN +F 1 "d_inverter" H 13300 13150 60 0000 C CNN +F 2 "" H 13350 12950 60 0000 C CNN +F 3 "" H 13350 12950 60 0000 C CNN + 1 13300 13000 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U18 +U 1 1 666AB8CD +P 14350 13550 +F 0 "U18" H 14350 13500 60 0000 C CNN +F 1 "d_buffer" H 14350 13600 60 0000 C CNN +F 2 "" H 14350 13550 60 0000 C CNN +F 3 "" H 14350 13550 60 0000 C CNN + 1 14350 13550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 666AB8CE +P 14450 14200 +F 0 "U25" H 14450 14200 60 0000 C CNN +F 1 "d_and" H 14500 14300 60 0000 C CNN +F 2 "" H 14450 14200 60 0000 C CNN +F 3 "" H 14450 14200 60 0000 C CNN + 1 14450 14200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 666AB8CF +P 14350 15050 +F 0 "U19" H 14350 15050 60 0000 C CNN +F 1 "d_and" H 14400 15150 60 0000 C CNN +F 2 "" H 14350 15050 60 0000 C CNN +F 3 "" H 14350 15050 60 0000 C CNN + 1 14350 15050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 666AB8D0 +P 13300 15050 +F 0 "U14" H 13300 14950 60 0000 C CNN +F 1 "d_inverter" H 13300 15200 60 0000 C CNN +F 2 "" H 13350 15000 60 0000 C CNN +F 3 "" H 13350 15000 60 0000 C CNN + 1 13300 15050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 666AB8D1 +P 17050 13800 +F 0 "U34" H 17050 13700 60 0000 C CNN +F 1 "d_inverter" H 17050 13950 60 0000 C CNN +F 2 "" H 17100 13750 60 0000 C CNN +F 3 "" H 17100 13750 60 0000 C CNN + 1 17050 13800 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U38 +U 1 1 666AB8D2 +P 18050 13300 +F 0 "U38" H 18050 13300 60 0000 C CNN +F 1 "d_xor" H 18100 13400 47 0000 C CNN +F 2 "" H 18050 13300 60 0000 C CNN +F 3 "" H 18050 13300 60 0000 C CNN + 1 18050 13300 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U32 +U 1 1 666AB8D3 +P 16400 15300 +F 0 "U32" H 16400 15300 60 0000 C CNN +F 1 "d_xor" H 16450 15400 47 0000 C CNN +F 2 "" H 16400 15300 60 0000 C CNN +F 3 "" H 16400 15300 60 0000 C CNN + 1 16400 15300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U31 +U 1 1 666AB8D4 +P 16100 13850 +F 0 "U31" H 16100 13850 60 0000 C CNN +F 1 "d_or" H 16100 13950 60 0000 C CNN +F 2 "" H 16100 13850 60 0000 C CNN +F 3 "" H 16100 13850 60 0000 C CNN + 1 16100 13850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 666AB8D5 +P 14350 15600 +F 0 "U20" H 14350 15500 60 0000 C CNN +F 1 "d_inverter" H 14350 15750 60 0000 C CNN +F 2 "" H 14400 15550 60 0000 C CNN +F 3 "" H 14400 15550 60 0000 C CNN + 1 14350 15600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U37 +U 1 1 666AB8D6 +P 17900 11550 +F 0 "U37" H 17900 11450 60 0000 C CNN +F 1 "d_inverter" H 17900 11700 60 0000 C CNN +F 2 "" H 17950 11500 60 0000 C CNN +F 3 "" H 17950 11500 60 0000 C CNN + 1 17900 11550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U11 +U 1 1 666AB8D7 +P 8300 7050 +F 0 "U11" H 8300 7050 60 0000 C CNN +F 1 "d_nand" H 8350 7150 60 0000 C CNN +F 2 "" H 8300 7050 60 0000 C CNN +F 3 "" H 8300 7050 60 0000 C CNN + 1 8300 7050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U12 +U 1 1 666AB8D8 +P 8300 7450 +F 0 "U12" H 8300 7450 60 0000 C CNN +F 1 "d_nor" H 8350 7550 60 0000 C CNN +F 2 "" H 8300 7450 60 0000 C CNN +F 3 "" H 8300 7450 60 0000 C CNN + 1 8300 7450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U8 +U 1 1 666AB8D9 +P 8200 10300 +F 0 "U8" H 8200 10300 60 0000 C CNN +F 1 "d_nand" H 8250 10400 60 0000 C CNN +F 2 "" H 8200 10300 60 0000 C CNN +F 3 "" H 8200 10300 60 0000 C CNN + 1 8200 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U9 +U 1 1 666AB8DA +P 8200 10700 +F 0 "U9" H 8200 10700 60 0000 C CNN +F 1 "d_nor" H 8250 10800 60 0000 C CNN +F 2 "" H 8200 10700 60 0000 C CNN +F 3 "" H 8200 10700 60 0000 C CNN + 1 8200 10700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U4 +U 1 1 666AB8DB +P 8150 12950 +F 0 "U4" H 8150 12950 60 0000 C CNN +F 1 "d_nand" H 8200 13050 60 0000 C CNN +F 2 "" H 8150 12950 60 0000 C CNN +F 3 "" H 8150 12950 60 0000 C CNN + 1 8150 12950 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U5 +U 1 1 666AB8DC +P 8150 13350 +F 0 "U5" H 8150 13350 60 0000 C CNN +F 1 "d_nor" H 8200 13450 60 0000 C CNN +F 2 "" H 8150 13350 60 0000 C CNN +F 3 "" H 8150 13350 60 0000 C CNN + 1 8150 13350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U6 +U 1 1 666AB8DD +P 8150 15000 +F 0 "U6" H 8150 15000 60 0000 C CNN +F 1 "d_nand" H 8200 15100 60 0000 C CNN +F 2 "" H 8150 15000 60 0000 C CNN +F 3 "" H 8150 15000 60 0000 C CNN + 1 8150 15000 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U7 +U 1 1 666AB8DE +P 8150 15400 +F 0 "U7" H 8150 15400 60 0000 C CNN +F 1 "d_nor" H 8200 15500 60 0000 C CNN +F 2 "" H 8150 15400 60 0000 C CNN +F 3 "" H 8150 15400 60 0000 C CNN + 1 8150 15400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 666AB8DF +P 8250 16050 +F 0 "U10" H 8250 15950 60 0000 C CNN +F 1 "d_inverter" H 8250 16200 60 0000 C CNN +F 2 "" H 8300 16000 60 0000 C CNN +F 3 "" H 8300 16000 60 0000 C CNN + 1 8250 16050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U2 +U 1 1 666AB8E0 +P 4600 10800 +F 0 "U2" H 4600 10800 60 0000 C CNN +F 1 "adc_bridge_8" H 4600 10950 60 0000 C CNN +F 2 "" H 4600 10800 60 0000 C CNN +F 3 "" H 4600 10800 60 0000 C CNN + 1 4600 10800 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U3 +U 1 1 666AB8E1 +P 5100 16100 +F 0 "U3" H 5100 16100 60 0000 C CNN +F 1 "adc_bridge_1" H 5100 16250 60 0000 C CNN +F 2 "" H 5100 16100 60 0000 C CNN +F 3 "" H 5100 16100 60 0000 C CNN + 1 5100 16100 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_5 U42 +U 1 1 666AB8E2 +P 21600 8950 +F 0 "U42" H 21600 8950 60 0000 C CNN +F 1 "dac_bridge_5" H 21600 9100 60 0000 C CNN +F 2 "" H 21600 8950 60 0000 C CNN +F 3 "" H 21600 8950 60 0000 C CNN + 1 21600 8950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15100 3100 16050 3100 +Wire Wire Line + 16050 3100 16050 4050 +Wire Wire Line + 14900 3700 15850 3700 +Wire Wire Line + 15850 3700 15850 4150 +Wire Wire Line + 15850 4150 16050 4150 +Wire Wire Line + 14850 4300 15800 4300 +Wire Wire Line + 15800 4300 15800 4250 +Wire Wire Line + 15800 4250 16050 4250 +Wire Wire Line + 14900 4950 16050 4950 +Wire Wire Line + 16050 4950 16050 4350 +Wire Wire Line + 16950 4200 17050 4200 +Wire Wire Line + 17050 4200 17050 4500 +Wire Wire Line + 17950 4550 18200 4550 +Wire Wire Line + 14050 7100 13750 7100 +Wire Wire Line + 15050 9350 15850 9350 +Wire Wire Line + 15850 9350 15850 8600 +Wire Wire Line + 15000 8750 15550 8750 +Wire Wire Line + 15550 8750 15550 8500 +Wire Wire Line + 15550 8500 15850 8500 +Wire Wire Line + 15000 8200 15550 8200 +Wire Wire Line + 15550 8200 15550 8400 +Wire Wire Line + 15550 8400 15850 8400 +Wire Wire Line + 15150 7600 15850 7600 +Wire Wire Line + 15850 7600 15850 8300 +Wire Wire Line + 16750 8450 16900 8450 +Wire Wire Line + 14950 7050 17700 7050 +Wire Wire Line + 17700 7050 17700 7700 +Wire Wire Line + 17500 8450 17700 8450 +Wire Wire Line + 17700 8450 17700 7800 +Wire Wire Line + 13950 10350 13650 10350 +Wire Wire Line + 13900 13000 13600 13000 +Wire Wire Line + 13900 15050 13600 15050 +Wire Wire Line + 14650 15600 15950 15600 +Wire Wire Line + 15950 15600 15950 15300 +Wire Wire Line + 15950 15200 15950 15000 +Wire Wire Line + 15950 15000 14800 15000 +Wire Wire Line + 14900 14150 15650 14150 +Wire Wire Line + 15650 14150 15650 13850 +Wire Wire Line + 15000 13550 15650 13550 +Wire Wire Line + 15650 13550 15650 13750 +Wire Wire Line + 16550 13800 16750 13800 +Wire Wire Line + 17350 13800 17600 13800 +Wire Wire Line + 17600 13800 17600 13300 +Wire Wire Line + 14800 12950 17600 12950 +Wire Wire Line + 17600 12950 17600 13200 +Wire Wire Line + 14900 12000 16600 12000 +Wire Wire Line + 16600 12000 16600 11600 +Wire Wire Line + 16500 11300 16500 11500 +Wire Wire Line + 16500 11500 16600 11500 +Wire Wire Line + 14950 11500 15600 11500 +Wire Wire Line + 15600 11500 15600 11350 +Wire Wire Line + 15050 10900 15600 10900 +Wire Wire Line + 15600 10900 15600 11250 +Wire Wire Line + 17500 11550 17600 11550 +Wire Wire Line + 18200 11550 18500 11550 +Wire Wire Line + 18500 11550 18500 10650 +Wire Wire Line + 14850 10300 18500 10300 +Wire Wire Line + 18500 10300 18500 10550 +Wire Wire Line + 14050 7000 8750 7000 +Wire Wire Line + 5150 6950 7850 6950 +Wire Wire Line + 7850 7350 7450 7350 +Wire Wire Line + 7450 7350 7450 6950 +Connection ~ 7450 6950 +Wire Wire Line + 5850 7450 7850 7450 +Wire Wire Line + 7850 7050 7700 7050 +Wire Wire Line + 7700 7050 7700 7450 +Connection ~ 7700 7450 +Wire Wire Line + 13950 10250 8650 10250 +Wire Wire Line + 6200 10200 7750 10200 +Wire Wire Line + 7750 10600 7350 10600 +Wire Wire Line + 7350 10600 7350 10200 +Connection ~ 7350 10200 +Wire Wire Line + 7750 10700 6600 10700 +Wire Wire Line + 7750 10300 7600 10300 +Wire Wire Line + 7600 10300 7600 10700 +Connection ~ 7600 10700 +Wire Wire Line + 13900 12900 8600 12900 +Wire Wire Line + 7700 12850 6550 12850 +Wire Wire Line + 7700 13250 7300 13250 +Wire Wire Line + 7300 13250 7300 12850 +Connection ~ 7300 12850 +Wire Wire Line + 6400 13350 7700 13350 +Wire Wire Line + 7700 12950 7550 12950 +Wire Wire Line + 7550 12950 7550 13350 +Connection ~ 7550 13350 +Wire Wire Line + 13900 14950 8600 14950 +Wire Wire Line + 5900 14900 7700 14900 +Wire Wire Line + 7700 15300 7300 15300 +Wire Wire Line + 7300 15300 7300 14900 +Connection ~ 7300 14900 +Wire Wire Line + 5550 15400 7700 15400 +Wire Wire Line + 7700 15000 7550 15000 +Wire Wire Line + 7550 15000 7550 15400 +Connection ~ 7550 15400 +Wire Wire Line + 13950 3100 8800 3100 +Wire Wire Line + 8800 3100 8800 7400 +Wire Wire Line + 8800 7400 8750 7400 +Wire Wire Line + 13150 7100 8800 7100 +Connection ~ 8800 7100 +Wire Wire Line + 14000 3650 8950 3650 +Wire Wire Line + 8950 3650 8950 10650 +Wire Wire Line + 8950 10650 8650 10650 +Wire Wire Line + 14000 4200 9100 4200 +Wire Wire Line + 9100 4200 9100 13300 +Wire Wire Line + 9100 13300 8600 13300 +Wire Wire Line + 14000 4800 9250 4800 +Wire Wire Line + 9250 4800 9250 15350 +Wire Wire Line + 9250 15350 8600 15350 +Wire Wire Line + 14000 3750 9650 3750 +Wire Wire Line + 9650 3750 9650 7000 +Connection ~ 9650 7000 +Wire Wire Line + 14000 4300 9650 4300 +Connection ~ 9650 4300 +Wire Wire Line + 14000 4900 9650 4900 +Connection ~ 9650 4900 +Wire Wire Line + 14000 5500 9650 5500 +Connection ~ 9650 5500 +Wire Wire Line + 14000 4400 9800 4400 +Wire Wire Line + 9800 4400 9800 10250 +Connection ~ 9800 10250 +Wire Wire Line + 14000 5000 9800 5000 +Connection ~ 9800 5000 +Wire Wire Line + 14000 5600 9800 5600 +Connection ~ 9800 5600 +Wire Wire Line + 14000 5100 10000 5100 +Wire Wire Line + 10000 5100 10000 12900 +Connection ~ 10000 12900 +Wire Wire Line + 13050 10350 8950 10350 +Connection ~ 8950 10350 +Wire Wire Line + 14000 5700 10000 5700 +Connection ~ 10000 5700 +Wire Wire Line + 14000 5800 10200 5800 +Wire Wire Line + 10200 5800 10200 14950 +Connection ~ 10200 14950 +Wire Wire Line + 14000 5900 10400 5900 +Wire Wire Line + 10400 5900 10400 16050 +Wire Wire Line + 10400 16050 8550 16050 +Wire Wire Line + 13000 15050 9250 15050 +Connection ~ 9250 15050 +Wire Wire Line + 13000 13000 9100 13000 +Connection ~ 9100 13000 +Wire Wire Line + 17050 4600 16650 4600 +Wire Wire Line + 16650 4600 16650 5700 +Wire Wire Line + 16650 5700 15000 5700 +Wire Wire Line + 14000 7600 8950 7600 +Connection ~ 8950 7600 +Wire Wire Line + 14100 8150 9100 8150 +Connection ~ 9100 8150 +Wire Wire Line + 14150 8650 9250 8650 +Connection ~ 9250 8650 +Wire Wire Line + 14100 8250 9800 8250 +Connection ~ 9800 8250 +Wire Wire Line + 14150 8750 9800 8750 +Connection ~ 9800 8750 +Wire Wire Line + 14150 9200 9800 9200 +Connection ~ 9800 9200 +Wire Wire Line + 14150 9300 10000 9300 +Connection ~ 10000 9300 +Wire Wire Line + 14150 9400 10200 9400 +Connection ~ 10200 9400 +Wire Wire Line + 14150 9500 10400 9500 +Connection ~ 10400 9500 +Wire Wire Line + 14150 8850 10000 8850 +Connection ~ 10000 8850 +Wire Wire Line + 13900 10900 9100 10900 +Connection ~ 9100 10900 +Wire Wire Line + 14050 11450 9250 11450 +Connection ~ 9250 11450 +Wire Wire Line + 14050 11900 10000 11900 +Connection ~ 10000 11900 +Wire Wire Line + 14050 11550 10000 11550 +Connection ~ 10000 11550 +Wire Wire Line + 13850 13550 9250 13550 +Connection ~ 9250 13550 +Wire Wire Line + 14000 14100 10200 14100 +Connection ~ 10200 14100 +Wire Wire Line + 14000 14200 10400 14200 +Connection ~ 10400 14200 +Wire Wire Line + 14050 15600 10400 15600 +Connection ~ 10400 15600 +Wire Wire Line + 5150 6950 5150 10750 +Wire Wire Line + 5150 10850 5850 10850 +Wire Wire Line + 5850 10850 5850 7450 +Wire Wire Line + 5150 10950 6200 10950 +Wire Wire Line + 6200 10950 6200 10200 +Wire Wire Line + 6600 10700 6600 11050 +Wire Wire Line + 6600 11050 5150 11050 +Wire Wire Line + 6550 12850 6550 11150 +Wire Wire Line + 6550 11150 5150 11150 +Wire Wire Line + 5150 11250 6400 11250 +Wire Wire Line + 6400 11250 6400 13350 +Wire Wire Line + 5900 14900 5900 11350 +Wire Wire Line + 5900 11350 5150 11350 +Wire Wire Line + 5150 11450 5550 11450 +Wire Wire Line + 5550 11450 5550 15400 +Wire Wire Line + 7950 16050 5650 16050 +Wire Wire Line + 16850 15250 21000 15250 +Wire Wire Line + 21000 15250 21000 9300 +Wire Wire Line + 18500 13250 20700 13250 +Wire Wire Line + 20700 13250 20700 9200 +Wire Wire Line + 20700 9200 21000 9200 +Wire Wire Line + 19400 10600 20400 10600 +Wire Wire Line + 20400 10600 20400 9100 +Wire Wire Line + 20400 9100 21000 9100 +Wire Wire Line + 18600 7750 20400 7750 +Wire Wire Line + 20400 7750 20400 9000 +Wire Wire Line + 20400 9000 21000 9000 +Wire Wire Line + 21000 8900 20750 8900 +Wire Wire Line + 20750 8900 20750 4550 +Wire Wire Line + 20750 4550 18800 4550 +Wire Wire Line + 14050 12000 10200 12000 +Connection ~ 10200 12000 +Wire Wire Line + 14050 12100 10400 12100 +Connection ~ 10400 12100 +$Comp +L PORT U1 +U 1 1 666AF136 +P 22400 9200 +F 0 "U1" H 22450 9300 30 0000 C CNN +F 1 "PORT" H 22400 9200 30 0000 C CNN +F 2 "" H 22400 9200 60 0000 C CNN +F 3 "" H 22400 9200 60 0000 C CNN + 1 22400 9200 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 666AF2A9 +P 3750 11150 +F 0 "U1" H 3800 11250 30 0000 C CNN +F 1 "PORT" H 3750 11150 30 0000 C CNN +F 2 "" H 3750 11150 60 0000 C CNN +F 3 "" H 3750 11150 60 0000 C CNN + 2 3750 11150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 666AF360 +P 3750 11250 +F 0 "U1" H 3800 11350 30 0000 C CNN +F 1 "PORT" H 3750 11250 30 0000 C CNN +F 2 "" H 3750 11250 60 0000 C CNN +F 3 "" H 3750 11250 60 0000 C CNN + 3 3750 11250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 666AF433 +P 22400 9300 +F 0 "U1" H 22450 9400 30 0000 C CNN +F 1 "PORT" H 22400 9300 30 0000 C CNN +F 2 "" H 22400 9300 60 0000 C CNN +F 3 "" H 22400 9300 60 0000 C CNN + 4 22400 9300 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 666AF51E +P 3750 11450 +F 0 "U1" H 3800 11550 30 0000 C CNN +F 1 "PORT" H 3750 11450 30 0000 C CNN +F 2 "" H 3750 11450 60 0000 C CNN +F 3 "" H 3750 11450 60 0000 C CNN + 5 3750 11450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 666AF5E5 +P 3750 11350 +F 0 "U1" H 3800 11450 30 0000 C CNN +F 1 "PORT" H 3750 11350 30 0000 C CNN +F 2 "" H 3750 11350 60 0000 C CNN +F 3 "" H 3750 11350 60 0000 C CNN + 6 3750 11350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 666AF6EA +P 4250 16050 +F 0 "U1" H 4300 16150 30 0000 C CNN +F 1 "PORT" H 4250 16050 30 0000 C CNN +F 2 "" H 4250 16050 60 0000 C CNN +F 3 "" H 4250 16050 60 0000 C CNN + 7 4250 16050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 666AF819 +P 22400 8900 +F 0 "U1" H 22450 9000 30 0000 C CNN +F 1 "PORT" H 22400 8900 30 0000 C CNN +F 2 "" H 22400 8900 60 0000 C CNN +F 3 "" H 22400 8900 60 0000 C CNN + 9 22400 8900 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 666AF8D8 +P 3750 11050 +F 0 "U1" H 3800 11150 30 0000 C CNN +F 1 "PORT" H 3750 11050 30 0000 C CNN +F 2 "" H 3750 11050 60 0000 C CNN +F 3 "" H 3750 11050 60 0000 C CNN + 14 3750 11050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 666AF9BF +P 22400 9000 +F 0 "U1" H 22450 9100 30 0000 C CNN +F 1 "PORT" H 22400 9000 30 0000 C CNN +F 2 "" H 22400 9000 60 0000 C CNN +F 3 "" H 22400 9000 60 0000 C CNN + 10 22400 9000 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 666AFAA0 +P 3750 10750 +F 0 "U1" H 3800 10850 30 0000 C CNN +F 1 "PORT" H 3750 10750 30 0000 C CNN +F 2 "" H 3750 10750 60 0000 C CNN +F 3 "" H 3750 10750 60 0000 C CNN + 11 3750 10750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 666AFB91 +P 3750 10850 +F 0 "U1" H 3800 10950 30 0000 C CNN +F 1 "PORT" H 3750 10850 30 0000 C CNN +F 2 "" H 3750 10850 60 0000 C CNN +F 3 "" H 3750 10850 60 0000 C CNN + 12 3750 10850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 666AFC6E +P 3750 10950 +F 0 "U1" H 3800 11050 30 0000 C CNN +F 1 "PORT" H 3750 10950 30 0000 C CNN +F 2 "" H 3750 10950 60 0000 C CNN +F 3 "" H 3750 10950 60 0000 C CNN + 8 3750 10950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 666AFD37 +P 22400 9100 +F 0 "U1" H 22450 9200 30 0000 C CNN +F 1 "PORT" H 22400 9100 30 0000 C CNN +F 2 "" H 22400 9100 60 0000 C CNN +F 3 "" H 22400 9100 60 0000 C CNN + 13 22400 9100 + -1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sub b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sub new file mode 100644 index 00000000..206847bc --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub.sub @@ -0,0 +1,182 @@ +* Subcircuit SN7483A_sub +.subckt SN7483A_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\sn7483a_sub\sn7483a_sub.cir +.include 3_and.sub +.include 4_OR.sub +.include 4_and.sub +.include 5_and.sub +* u23 net-_u12-pad3_ net-_u23-pad2_ d_buffer +* u24 net-_u15-pad1_ net-_u11-pad3_ net-_u24-pad3_ d_and +x1 net-_u13-pad1_ net-_u11-pad3_ net-_u21-pad1_ net-_x1-pad4_ 3_and +x2 net-_u14-pad1_ net-_u11-pad3_ net-_u21-pad1_ net-_u17-pad1_ net-_x2-pad5_ 4_and +x4 net-_u11-pad3_ net-_u21-pad1_ net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_u36-pad2_ 5_and +x8 net-_u23-pad2_ net-_u24-pad3_ net-_x1-pad4_ net-_x2-pad5_ net-_u36-pad1_ 4_OR +* u36 net-_u36-pad1_ net-_u36-pad2_ net-_u36-pad3_ d_or +* u40 net-_u36-pad3_ net-_u40-pad2_ d_inverter +* u26 net-_u11-pad3_ net-_u16-pad2_ net-_u26-pad3_ d_and +* u16 net-_u12-pad3_ net-_u16-pad2_ d_inverter +* u27 net-_u15-pad1_ net-_u27-pad2_ d_buffer +* u29 net-_u13-pad1_ net-_u21-pad1_ net-_u29-pad3_ d_and +x5 net-_u14-pad1_ net-_u21-pad1_ net-_u17-pad1_ net-_x5-pad4_ 3_and +x6 net-_u21-pad1_ net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_x6-pad5_ 4_and +x7 net-_u27-pad2_ net-_u29-pad3_ net-_x5-pad4_ net-_x6-pad5_ net-_u35-pad1_ 4_OR +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u39 net-_u26-pad3_ net-_u35-pad2_ net-_u39-pad3_ d_xor +* u21 net-_u21-pad1_ net-_u15-pad2_ net-_u21-pad3_ d_and +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u22 net-_u13-pad1_ net-_u22-pad2_ d_buffer +* u28 net-_u14-pad1_ net-_u17-pad1_ net-_u28-pad3_ d_and +x3 net-_u17-pad1_ net-_u19-pad1_ net-_u10-pad2_ net-_u33-pad2_ 3_and +* u30 net-_u22-pad2_ net-_u28-pad3_ net-_u30-pad3_ d_or +* u33 net-_u30-pad3_ net-_u33-pad2_ net-_u33-pad3_ d_or +* u41 net-_u21-pad3_ net-_u37-pad2_ net-_u41-pad3_ d_xor +* u17 net-_u17-pad1_ net-_u13-pad2_ net-_u17-pad3_ d_and +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u18 net-_u14-pad1_ net-_u18-pad2_ d_buffer +* u25 net-_u19-pad1_ net-_u10-pad2_ net-_u25-pad3_ d_and +* u19 net-_u19-pad1_ net-_u14-pad2_ net-_u19-pad3_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u34 net-_u31-pad3_ net-_u34-pad2_ d_inverter +* u38 net-_u17-pad3_ net-_u34-pad2_ net-_u38-pad3_ d_xor +* u32 net-_u19-pad3_ net-_u20-pad2_ net-_u32-pad3_ d_xor +* u31 net-_u18-pad2_ net-_u25-pad3_ net-_u31-pad3_ d_or +* u20 net-_u10-pad2_ net-_u20-pad2_ d_inverter +* u37 net-_u33-pad3_ net-_u37-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u12 net-_u11-pad1_ net-_u11-pad2_ net-_u12-pad3_ d_nor +* u8 net-_u2-pad11_ net-_u2-pad12_ net-_u21-pad1_ d_nand +* u9 net-_u2-pad11_ net-_u2-pad12_ net-_u15-pad1_ d_nor +* u4 net-_u2-pad13_ net-_u2-pad14_ net-_u17-pad1_ d_nand +* u5 net-_u2-pad13_ net-_u2-pad14_ net-_u13-pad1_ d_nor +* u6 net-_u2-pad15_ net-_u2-pad16_ net-_u19-pad1_ d_nand +* u7 net-_u2-pad15_ net-_u2-pad16_ net-_u14-pad1_ d_nor +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad8_ net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ net-_u11-pad1_ net-_u11-pad2_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8 +* u3 net-_u1-pad7_ net-_u10-pad1_ adc_bridge_1 +* u42 net-_u40-pad2_ net-_u39-pad3_ net-_u41-pad3_ net-_u38-pad3_ net-_u32-pad3_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad1_ net-_u1-pad4_ dac_bridge_5 +a1 net-_u12-pad3_ net-_u23-pad2_ u23 +a2 [net-_u15-pad1_ net-_u11-pad3_ ] net-_u24-pad3_ u24 +a3 [net-_u36-pad1_ net-_u36-pad2_ ] net-_u36-pad3_ u36 +a4 net-_u36-pad3_ net-_u40-pad2_ u40 +a5 [net-_u11-pad3_ net-_u16-pad2_ ] net-_u26-pad3_ u26 +a6 net-_u12-pad3_ net-_u16-pad2_ u16 +a7 net-_u15-pad1_ net-_u27-pad2_ u27 +a8 [net-_u13-pad1_ net-_u21-pad1_ ] net-_u29-pad3_ u29 +a9 net-_u35-pad1_ net-_u35-pad2_ u35 +a10 [net-_u26-pad3_ net-_u35-pad2_ ] net-_u39-pad3_ u39 +a11 [net-_u21-pad1_ net-_u15-pad2_ ] net-_u21-pad3_ u21 +a12 net-_u15-pad1_ net-_u15-pad2_ u15 +a13 net-_u13-pad1_ net-_u22-pad2_ u22 +a14 [net-_u14-pad1_ net-_u17-pad1_ ] net-_u28-pad3_ u28 +a15 [net-_u22-pad2_ net-_u28-pad3_ ] net-_u30-pad3_ u30 +a16 [net-_u30-pad3_ net-_u33-pad2_ ] net-_u33-pad3_ u33 +a17 [net-_u21-pad3_ net-_u37-pad2_ ] net-_u41-pad3_ u41 +a18 [net-_u17-pad1_ net-_u13-pad2_ ] net-_u17-pad3_ u17 +a19 net-_u13-pad1_ net-_u13-pad2_ u13 +a20 net-_u14-pad1_ net-_u18-pad2_ u18 +a21 [net-_u19-pad1_ net-_u10-pad2_ ] net-_u25-pad3_ u25 +a22 [net-_u19-pad1_ net-_u14-pad2_ ] net-_u19-pad3_ u19 +a23 net-_u14-pad1_ net-_u14-pad2_ u14 +a24 net-_u31-pad3_ net-_u34-pad2_ u34 +a25 [net-_u17-pad3_ net-_u34-pad2_ ] net-_u38-pad3_ u38 +a26 [net-_u19-pad3_ net-_u20-pad2_ ] net-_u32-pad3_ u32 +a27 [net-_u18-pad2_ net-_u25-pad3_ ] net-_u31-pad3_ u31 +a28 net-_u10-pad2_ net-_u20-pad2_ u20 +a29 net-_u33-pad3_ net-_u37-pad2_ u37 +a30 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a31 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u12-pad3_ u12 +a32 [net-_u2-pad11_ net-_u2-pad12_ ] net-_u21-pad1_ u8 +a33 [net-_u2-pad11_ net-_u2-pad12_ ] net-_u15-pad1_ u9 +a34 [net-_u2-pad13_ net-_u2-pad14_ ] net-_u17-pad1_ u4 +a35 [net-_u2-pad13_ net-_u2-pad14_ ] net-_u13-pad1_ u5 +a36 [net-_u2-pad15_ net-_u2-pad16_ ] net-_u19-pad1_ u6 +a37 [net-_u2-pad15_ net-_u2-pad16_ ] net-_u14-pad1_ u7 +a38 net-_u10-pad1_ net-_u10-pad2_ u10 +a39 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad8_ net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad5_ ] [net-_u11-pad1_ net-_u11-pad2_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2 +a40 [net-_u1-pad7_ ] [net-_u10-pad1_ ] u3 +a41 [net-_u40-pad2_ net-_u39-pad3_ net-_u41-pad3_ net-_u38-pad3_ net-_u32-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad13_ net-_u1-pad1_ net-_u1-pad4_ ] u42 +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u39 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u30 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u41 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u38 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u32 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u42 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends SN7483A_sub
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub_Previous_Values.xml b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub_Previous_Values.xml new file mode 100644 index 00000000..13a8b429 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/SN7483A_sub_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u23 name="type">d_buffer<field1 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field1><field2 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field2><field3 name="Enter Input Load (default=1.0e-12)">1.0e-12</field3></u23><u24 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field4><field5 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field5><field6 name="Enter Input Load (default=1.0e-12)">1.0e-12</field6></u24><u36 name="type">d_or<field7 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field7><field8 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field8><field9 name="Enter Input Load (default=1.0e-12)">1.0e-12</field9></u36><u40 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field10><field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field11><field12 name="Enter Input Load (default=1.0e-12)">1.0e-12</field12></u40><u26 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field13><field14 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field14><field15 name="Enter Input Load (default=1.0e-12)">1.0e-12</field15></u26><u16 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field16><field17 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field17><field18 name="Enter Input Load (default=1.0e-12)">1.0e-12</field18></u16><u27 name="type">d_buffer<field19 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field19><field20 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field20><field21 name="Enter Input Load (default=1.0e-12)">1.0e-12</field21></u27><u29 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field22><field23 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field23><field24 name="Enter Input Load (default=1.0e-12)">1.0e-12</field24></u29><u35 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field25><field26 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field26><field27 name="Enter Input Load (default=1.0e-12)">1.0e-12</field27></u35><u39 name="type">d_xor<field28 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field28><field29 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field29><field30 name="Enter Input Load (default=1.0e-12)">1.0e-12</field30></u39><u21 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field31><field32 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field32><field33 name="Enter Input Load (default=1.0e-12)">1.0e-12</field33></u21><u15 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field34><field35 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field35><field36 name="Enter Input Load (default=1.0e-12)">1.0e-12</field36></u15><u22 name="type">d_buffer<field37 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field37><field38 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field38><field39 name="Enter Input Load (default=1.0e-12)">1.0e-12</field39></u22><u28 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field40><field41 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field41><field42 name="Enter Input Load (default=1.0e-12)">1.0e-12</field42></u28><u30 name="type">d_or<field43 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field43><field44 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field44><field45 name="Enter Input Load (default=1.0e-12)">1.0e-12</field45></u30><u33 name="type">d_or<field46 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field46><field47 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field47><field48 name="Enter Input Load (default=1.0e-12)">1.0e-12</field48></u33><u41 name="type">d_xor<field49 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field49><field50 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field50><field51 name="Enter Input Load (default=1.0e-12)">1.0e-12</field51></u41><u17 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field52><field53 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field53><field54 name="Enter Input Load (default=1.0e-12)">1.0e-12</field54></u17><u13 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field55><field56 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field56><field57 name="Enter Input Load (default=1.0e-12)">1.0e-12</field57></u13><u18 name="type">d_buffer<field58 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field58><field59 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field59><field60 name="Enter Input Load (default=1.0e-12)">1.0e-12</field60></u18><u25 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field61><field62 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field62><field63 name="Enter Input Load (default=1.0e-12)">1.0e-12</field63></u25><u19 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field64><field65 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field65><field66 name="Enter Input Load (default=1.0e-12)">1.0e-12</field66></u19><u14 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field67><field68 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field68><field69 name="Enter Input Load (default=1.0e-12)">1.0e-12</field69></u14><u34 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field70><field71 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field71><field72 name="Enter Input Load (default=1.0e-12)">1.0e-12</field72></u34><u38 name="type">d_xor<field73 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field73><field74 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field74><field75 name="Enter Input Load (default=1.0e-12)">1.0e-12</field75></u38><u32 name="type">d_xor<field76 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field76><field77 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field77><field78 name="Enter Input Load (default=1.0e-12)">1.0e-12</field78></u32><u31 name="type">d_or<field79 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field79><field80 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field80><field81 name="Enter Input Load (default=1.0e-12)">1.0e-12</field81></u31><u20 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field82><field83 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field83><field84 name="Enter Input Load (default=1.0e-12)">1.0e-12</field84></u20><u37 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field85><field86 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field86><field87 name="Enter Input Load (default=1.0e-12)">1.0e-12</field87></u37><u11 name="type">d_nand<field88 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field88><field89 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field89><field90 name="Enter Input Load (default=1.0e-12)">1.0e-12</field90></u11><u12 name="type">d_nor<field91 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field91><field92 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field92><field93 name="Enter Input Load (default=1.0e-12)">1.0e-12</field93></u12><u8 name="type">d_nand<field94 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field94><field95 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field95><field96 name="Enter Input Load (default=1.0e-12)">1.0e-12</field96></u8><u9 name="type">d_nor<field97 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field97><field98 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field98><field99 name="Enter Input Load (default=1.0e-12)">1.0e-12</field99></u9><u4 name="type">d_nand<field100 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field100><field101 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field101><field102 name="Enter Input Load (default=1.0e-12)">1.0e-12</field102></u4><u5 name="type">d_nor<field103 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field103><field104 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field104><field105 name="Enter Input Load (default=1.0e-12)">1.0e-12</field105></u5><u6 name="type">d_nand<field106 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field106><field107 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field107><field108 name="Enter Input Load (default=1.0e-12)">1.0e-12</field108></u6><u7 name="type">d_nor<field109 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field109><field110 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field110><field111 name="Enter Input Load (default=1.0e-12)">1.0e-12</field111></u7><u10 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field112><field113 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field113><field114 name="Enter Input Load (default=1.0e-12)">1.0e-12</field114></u10><u2 name="type">adc_bridge<field115 name="Enter value for in_low (default=1.0)">1.0</field115><field116 name="Enter value for in_high (default=2.0)">2.0</field116><field117 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field117><field118 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field118></u2><u3 name="type">adc_bridge<field119 name="Enter value for in_low (default=1.0)">1.0</field119><field120 name="Enter value for in_high (default=2.0)">2.0</field120><field121 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field121><field122 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field122></u3><u42 name="type">dac_bridge<field123 name="Enter value for out_low (default=0.0)">0.0</field123><field124 name="Enter value for out_high (default=5.0)">5.0</field124><field125 name="Enter value for out_undef (default=0.5)">0.5</field125><field126 name="Enter value for input load (default=1.0e-12)">1.0e-12</field126><field127 name="Enter the Rise Time (default=1.0e-9)">1.0e-9</field127><field128 name="Enter the Fall Time (default=1.0e-9)">1.0e-9</field128></u42></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x8><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x7><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7483A_sub/analysis b/library/SubcircuitLibrary/SN7483A_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |