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| author | Sumanto Kar | 2024-11-21 20:48:19 +0530 |
|---|---|---|
| committer | Sumanto Kar | 2024-11-21 20:48:19 +0530 |
| commit | ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3 (patch) | |
| tree | 6affc84ae61bd25a629881ba5b61c947b6cacf3d /library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out | |
| parent | eacf5ca52184c22dfb8f9e01789acda4ab96dcf3 (diff) | |
| download | eSim-ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3.tar.gz eSim-ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3.tar.bz2 eSim-ac1c0c32e68fb7c4d1d738e9721f76b612eda5c3.zip | |
SN7483A is a 4-bit binary full adder
Diffstat (limited to 'library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/SN7483A_sub/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |