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authorMaanit2025-02-16 19:36:48 +0530
committerMaanit2025-02-16 19:36:48 +0530
commit5b7ef235576d903e20c11e348fcaf5c2b30bb059 (patch)
tree311ef44076c4dea6be25eef07da5fd7c3e18aa4b /library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub
parent4ffd6c2f3e762b97739af70fff7bc14cf51e9b54 (diff)
downloadeSim-5b7ef235576d903e20c11e348fcaf5c2b30bb059.tar.gz
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NAND Gate TTL required for SN74LS00
Diffstat (limited to 'library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub')
-rw-r--r--library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub18
1 files changed, 18 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub
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index 00000000..544c5e10
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+++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub
@@ -0,0 +1,18 @@
+* Subcircuit NAND_GATE_FINAL
+.subckt NAND_GATE_FINAL net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir
+.include D.lib
+.include NPN.lib
+q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r1 net-_r1-pad1_ net-_q1-pad2_ 500
+r2 net-_r1-pad1_ net-_q3-pad1_ 60k
+r4 net-_q4-pad1_ net-_r1-pad1_ 10k
+q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222
+q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222
+r3 net-_q3-pad3_ gnd 10k
+* Control Statements
+
+.ends NAND_GATE_FINAL \ No newline at end of file