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authorAditya Minocha2024-08-25 21:58:26 +0530
committerGitHub2024-08-25 21:58:26 +0530
commit7b98810d458d8cf7a68ff62831ab8ea1cc5846f8 (patch)
tree68cabb9841a619ecc0280dde27f0be7b3ba39d0f /library/SubcircuitLibrary/Logic_Gates/NOT.cir
parente8f999d879320df46aaec04605cb92ff06ad4809 (diff)
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Logic Gates
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+* C:\FOSSEE\eSim\library\SubcircuitLibrary\NOT\NOT.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/24 16:04:31
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ GND GND mosfet_n
+M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ mosfet_p
+v1 Net-_M2-Pad1_ GND DC
+U1 Net-_M1-Pad2_ Net-_M1-Pad1_ PORT
+
+.end