From 7b98810d458d8cf7a68ff62831ab8ea1cc5846f8 Mon Sep 17 00:00:00 2001
From: Aditya Minocha
Date: Sun, 25 Aug 2024 21:58:26 +0530
Subject: Logic Gates

---
 library/SubcircuitLibrary/Logic_Gates/NOT.cir | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 library/SubcircuitLibrary/Logic_Gates/NOT.cir

(limited to 'library/SubcircuitLibrary/Logic_Gates/NOT.cir')

diff --git a/library/SubcircuitLibrary/Logic_Gates/NOT.cir b/library/SubcircuitLibrary/Logic_Gates/NOT.cir
new file mode 100644
index 00000000..7cb59370
--- /dev/null
+++ b/library/SubcircuitLibrary/Logic_Gates/NOT.cir
@@ -0,0 +1,14 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\NOT\NOT.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/24/24 16:04:31
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ GND GND mosfet_n		
+M2  Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ mosfet_p		
+v1  Net-_M2-Pad1_ GND DC		
+U1  Net-_M1-Pad2_ Net-_M1-Pad1_ PORT		
+
+.end
-- 
cgit