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| author | Aditya Minocha | 2024-08-25 21:58:26 +0530 |
|---|---|---|
| committer | GitHub | 2024-08-25 21:58:26 +0530 |
| commit | 7b98810d458d8cf7a68ff62831ab8ea1cc5846f8 (patch) | |
| tree | 68cabb9841a619ecc0280dde27f0be7b3ba39d0f /library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir | |
| parent | e8f999d879320df46aaec04605cb92ff06ad4809 (diff) | |
| download | eSim-7b98810d458d8cf7a68ff62831ab8ea1cc5846f8.tar.gz eSim-7b98810d458d8cf7a68ff62831ab8ea1cc5846f8.tar.bz2 eSim-7b98810d458d8cf7a68ff62831ab8ea1cc5846f8.zip | |
Logic Gates
Diffstat (limited to 'library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir')
| -rw-r--r-- | library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir b/library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir new file mode 100644 index 00000000..a3bd7689 --- /dev/null +++ b/library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir @@ -0,0 +1,18 @@ +* C:\Users\Aditya\eSim-Workspace\Logic_Gates\Logic_Gates.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/28/24 11:42:35
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v1 A GND pulse
+v2 B GND pulse
+R1 OutA GND 1000k
+X1 A OutA NOT_Gate
+X2 B OutB NOT_Gate
+R2 OutB GND 1000k
+U1 A B OutC XOR_Gate
+R3 OutC GND 1000k
+
+.end
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