From 7b98810d458d8cf7a68ff62831ab8ea1cc5846f8 Mon Sep 17 00:00:00 2001
From: Aditya Minocha
Date: Sun, 25 Aug 2024 21:58:26 +0530
Subject: Logic Gates

---
 library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir

(limited to 'library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir')

diff --git a/library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir b/library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir
new file mode 100644
index 00000000..a3bd7689
--- /dev/null
+++ b/library/SubcircuitLibrary/Logic_Gates/Logic_Gates.cir
@@ -0,0 +1,18 @@
+* C:\Users\Aditya\eSim-Workspace\Logic_Gates\Logic_Gates.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/28/24 11:42:35
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v1  A GND pulse		
+v2  B GND pulse		
+R1  OutA GND 1000k		
+X1  A OutA NOT_Gate		
+X2  B OutB NOT_Gate		
+R2  OutB GND 1000k		
+U1  A B OutC XOR_Gate		
+R3  OutC GND 1000k		
+
+.end
-- 
cgit