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| author | Rachith-H | 2025-02-22 19:59:09 +0530 |
|---|---|---|
| committer | Rachith-H | 2025-02-22 19:59:09 +0530 |
| commit | 513741280468dff85f04eae21b89aa0a9f5da7d5 (patch) | |
| tree | 91d5626fc6f875890643dd0204aef84248d0fe25 /library/SubcircuitLibrary/CD4532B/4_and.cir.out | |
| parent | 1ad2e9d32d9b811d38e3f6ab63fb76d97030c293 (diff) | |
| download | eSim-513741280468dff85f04eae21b89aa0a9f5da7d5.tar.gz eSim-513741280468dff85f04eae21b89aa0a9f5da7d5.tar.bz2 eSim-513741280468dff85f04eae21b89aa0a9f5da7d5.zip | |
CD4532B is a 8 bit priority encoder
Diffstat (limited to 'library/SubcircuitLibrary/CD4532B/4_and.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/CD4532B/4_and.cir.out | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4532B/4_and.cir.out b/library/SubcircuitLibrary/CD4532B/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |