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| author | Rachith-H | 2025-02-22 19:59:09 +0530 |
|---|---|---|
| committer | Rachith-H | 2025-02-22 19:59:09 +0530 |
| commit | 513741280468dff85f04eae21b89aa0a9f5da7d5 (patch) | |
| tree | 91d5626fc6f875890643dd0204aef84248d0fe25 /library/SubcircuitLibrary/CD4532B | |
| parent | 1ad2e9d32d9b811d38e3f6ab63fb76d97030c293 (diff) | |
| download | eSim-513741280468dff85f04eae21b89aa0a9f5da7d5.tar.gz eSim-513741280468dff85f04eae21b89aa0a9f5da7d5.tar.bz2 eSim-513741280468dff85f04eae21b89aa0a9f5da7d5.zip | |
CD4532B is a 8 bit priority encoder
Diffstat (limited to 'library/SubcircuitLibrary/CD4532B')
30 files changed, 2594 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4532B/3_and-cache.lib b/library/SubcircuitLibrary/CD4532B/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/3_and.cir b/library/SubcircuitLibrary/CD4532B/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/3_and.cir.out b/library/SubcircuitLibrary/CD4532B/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/3_and.pro b/library/SubcircuitLibrary/CD4532B/3_and.pro new file mode 100644 index 00000000..06813ca7 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/CD4532B/3_and.sch b/library/SubcircuitLibrary/CD4532B/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/3_and.sub b/library/SubcircuitLibrary/CD4532B/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib b/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.cir b/library/SubcircuitLibrary/CD4532B/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.cir.out b/library/SubcircuitLibrary/CD4532B/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.pro b/library/SubcircuitLibrary/CD4532B/4_OR.pro new file mode 100644 index 00000000..881563eb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.sch b/library/SubcircuitLibrary/CD4532B/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.sub b/library/SubcircuitLibrary/CD4532B/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_and-cache.lib b/library/SubcircuitLibrary/CD4532B/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib b/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_and.cir b/library/SubcircuitLibrary/CD4532B/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_and.cir.out b/library/SubcircuitLibrary/CD4532B/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_and.pro b/library/SubcircuitLibrary/CD4532B/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/CD4532B/4_and.sch b/library/SubcircuitLibrary/CD4532B/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/4_and.sub b/library/SubcircuitLibrary/CD4532B/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib b/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib new file mode 100644 index 00000000..fbb8d926 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib @@ -0,0 +1,134 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.cir b/library/SubcircuitLibrary/CD4532B/CD4532B.cir new file mode 100644 index 00000000..cd581690 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.cir @@ -0,0 +1,54 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\CD4532B\CD4532B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/10/25 20:14:54 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad11_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U4 Net-_U1-Pad13_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad1_ Net-_U11-Pad1_ d_inverter +U7 Net-_U1-Pad2_ Net-_U12-Pad1_ d_inverter +U8 Net-_U1-Pad3_ Net-_U13-Pad1_ d_inverter +U6 Net-_U1-Pad4_ Net-_U6-Pad2_ d_inverter +U9 Net-_U1-Pad5_ Net-_U14-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +X1 Net-_U2-Pad2_ Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_X1-Pad5_ 4_OR +X2 Net-_U13-Pad2_ Net-_U11-Pad2_ Net-_U4-Pad2_ ? Net-_X2-Pad5_ 4_OR +X3 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U12-Pad2_ ? Net-_X3-Pad5_ 4_OR +X4 Net-_U4-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ ? Net-_X4-Pad5_ 4_OR +U22 Net-_U22-Pad1_ Net-_U16-Pad1_ d_inverter +U23 Net-_U23-Pad1_ Net-_U15-Pad1_ d_inverter +U24 Net-_U16-Pad1_ Net-_U15-Pad1_ Net-_U24-Pad3_ d_nand +X5 Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U19-Pad3_ Net-_U6-Pad2_ Net-_U25-Pad1_ 4_and +X6 Net-_X3-Pad5_ Net-_X4-Pad5_ Net-_U13-Pad1_ Net-_U6-Pad2_ Net-_U27-Pad1_ 4_and +X7 Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U6-Pad2_ Net-_U26-Pad1_ 4_and +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ d_inverter +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter +U26 Net-_U26-Pad1_ Net-_U26-Pad2_ d_inverter +U29 Net-_U25-Pad2_ Net-_U14-Pad2_ Net-_U29-Pad3_ d_nand +U30 Net-_U27-Pad2_ Net-_U14-Pad2_ Net-_U30-Pad3_ d_nand +U31 Net-_U26-Pad2_ Net-_U14-Pad2_ Net-_U31-Pad3_ d_nand +U32 Net-_U24-Pad3_ Net-_U1-Pad5_ Net-_U32-Pad3_ d_nand +U34 Net-_U29-Pad3_ Net-_U1-Pad9_ d_inverter +U33 Net-_U30-Pad3_ Net-_U1-Pad7_ d_inverter +U36 Net-_U31-Pad3_ Net-_U1-Pad6_ d_inverter +U37 Net-_U32-Pad3_ Net-_U1-Pad14_ d_inverter +U35 Net-_U20-Pad3_ Net-_U1-Pad15_ d_inverter +U19 Net-_U13-Pad2_ Net-_U12-Pad1_ Net-_U19-Pad3_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +X8 Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U22-Pad1_ 4_OR +X9 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad10_ Net-_U23-Pad1_ 4_OR +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U17 Net-_U1-Pad5_ Net-_U17-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U18 Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U18-Pad3_ d_or +U20 Net-_U18-Pad3_ Net-_U17-Pad2_ Net-_U20-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out b/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out new file mode 100644 index 00000000..40e32465 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out @@ -0,0 +1,159 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\cd4532b\cd4532b.cir + +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad11_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u1-pad2_ net-_u12-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad4_ net-_u6-pad2_ d_inverter +* u9 net-_u1-pad5_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x1-pad5_ 4_OR +x2 net-_u13-pad2_ net-_u11-pad2_ net-_u4-pad2_ ? net-_x2-pad5_ 4_OR +x3 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x3-pad5_ 4_OR +x4 net-_u4-pad2_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x4-pad5_ 4_OR +* u22 net-_u22-pad1_ net-_u16-pad1_ d_inverter +* u23 net-_u23-pad1_ net-_u15-pad1_ d_inverter +* u24 net-_u16-pad1_ net-_u15-pad1_ net-_u24-pad3_ d_nand +x5 net-_x1-pad5_ net-_x2-pad5_ net-_u19-pad3_ net-_u6-pad2_ net-_u25-pad1_ 4_and +x6 net-_x3-pad5_ net-_x4-pad5_ net-_u13-pad1_ net-_u6-pad2_ net-_u27-pad1_ 4_and +x7 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u6-pad2_ net-_u26-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u29 net-_u25-pad2_ net-_u14-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u27-pad2_ net-_u14-pad2_ net-_u30-pad3_ d_nand +* u31 net-_u26-pad2_ net-_u14-pad2_ net-_u31-pad3_ d_nand +* u32 net-_u24-pad3_ net-_u1-pad5_ net-_u32-pad3_ d_nand +* u34 net-_u29-pad3_ net-_u1-pad9_ d_inverter +* u33 net-_u30-pad3_ net-_u1-pad7_ d_inverter +* u36 net-_u31-pad3_ net-_u1-pad6_ d_inverter +* u37 net-_u32-pad3_ net-_u1-pad14_ d_inverter +* u35 net-_u20-pad3_ net-_u1-pad15_ d_inverter +* u19 net-_u13-pad2_ net-_u12-pad1_ net-_u19-pad3_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +x8 net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u22-pad1_ 4_OR +x9 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad10_ net-_u23-pad1_ 4_OR +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u1-pad5_ net-_u17-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u18 net-_u15-pad2_ net-_u16-pad2_ net-_u18-pad3_ d_or +* u20 net-_u18-pad3_ net-_u17-pad2_ net-_u20-pad3_ d_or +a1 net-_u1-pad11_ net-_u2-pad2_ u2 +a2 net-_u1-pad12_ net-_u10-pad1_ u3 +a3 net-_u1-pad13_ net-_u4-pad2_ u4 +a4 net-_u1-pad1_ net-_u11-pad1_ u5 +a5 net-_u1-pad2_ net-_u12-pad1_ u7 +a6 net-_u1-pad3_ net-_u13-pad1_ u8 +a7 net-_u1-pad4_ net-_u6-pad2_ u6 +a8 net-_u1-pad5_ net-_u14-pad1_ u9 +a9 net-_u10-pad1_ net-_u10-pad2_ u10 +a10 net-_u11-pad1_ net-_u11-pad2_ u11 +a11 net-_u12-pad1_ net-_u12-pad2_ u12 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u14-pad1_ net-_u14-pad2_ u14 +a14 net-_u22-pad1_ net-_u16-pad1_ u22 +a15 net-_u23-pad1_ net-_u15-pad1_ u23 +a16 [net-_u16-pad1_ net-_u15-pad1_ ] net-_u24-pad3_ u24 +a17 net-_u25-pad1_ net-_u25-pad2_ u25 +a18 net-_u27-pad1_ net-_u27-pad2_ u27 +a19 net-_u26-pad1_ net-_u26-pad2_ u26 +a20 [net-_u25-pad2_ net-_u14-pad2_ ] net-_u29-pad3_ u29 +a21 [net-_u27-pad2_ net-_u14-pad2_ ] net-_u30-pad3_ u30 +a22 [net-_u26-pad2_ net-_u14-pad2_ ] net-_u31-pad3_ u31 +a23 [net-_u24-pad3_ net-_u1-pad5_ ] net-_u32-pad3_ u32 +a24 net-_u29-pad3_ net-_u1-pad9_ u34 +a25 net-_u30-pad3_ net-_u1-pad7_ u33 +a26 net-_u31-pad3_ net-_u1-pad6_ u36 +a27 net-_u32-pad3_ net-_u1-pad14_ u37 +a28 net-_u20-pad3_ net-_u1-pad15_ u35 +a29 [net-_u13-pad2_ net-_u12-pad1_ ] net-_u19-pad3_ u19 +a30 net-_u16-pad1_ net-_u16-pad2_ u16 +a31 net-_u1-pad5_ net-_u17-pad2_ u17 +a32 net-_u15-pad1_ net-_u15-pad2_ u15 +a33 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a34 [net-_u18-pad3_ net-_u17-pad2_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.pro b/library/SubcircuitLibrary/CD4532B/CD4532B.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.sch b/library/SubcircuitLibrary/CD4532B/CD4532B.sch new file mode 100644 index 00000000..626b76df --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.sch @@ -0,0 +1,1074 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:CD4532B-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 67A4FD25 +P 7050 4200 +F 0 "U2" H 7050 4100 60 0000 C CNN +F 1 "d_inverter" H 7050 4350 60 0000 C CNN +F 2 "" H 7100 4150 60 0000 C CNN +F 3 "" H 7100 4150 60 0000 C CNN + 1 7050 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67A4FD58 +P 7050 4850 +F 0 "U3" H 7050 4750 60 0000 C CNN +F 1 "d_inverter" H 7050 5000 60 0000 C CNN +F 2 "" H 7100 4800 60 0000 C CNN +F 3 "" H 7100 4800 60 0000 C CNN + 1 7050 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67A4FD79 +P 7050 6350 +F 0 "U4" H 7050 6250 60 0000 C CNN +F 1 "d_inverter" H 7050 6500 60 0000 C CNN +F 2 "" H 7100 6300 60 0000 C CNN +F 3 "" H 7100 6300 60 0000 C CNN + 1 7050 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 67A4FDA4 +P 7050 7350 +F 0 "U5" H 7050 7250 60 0000 C CNN +F 1 "d_inverter" H 7050 7500 60 0000 C CNN +F 2 "" H 7100 7300 60 0000 C CNN +F 3 "" H 7100 7300 60 0000 C CNN + 1 7050 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 67A4FE34 +P 7100 8050 +F 0 "U7" H 7100 7950 60 0000 C CNN +F 1 "d_inverter" H 7100 8200 60 0000 C CNN +F 2 "" H 7150 8000 60 0000 C CNN +F 3 "" H 7150 8000 60 0000 C CNN + 1 7100 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 67A4FE3A +P 7100 8700 +F 0 "U8" H 7100 8600 60 0000 C CNN +F 1 "d_inverter" H 7100 8850 60 0000 C CNN +F 2 "" H 7150 8650 60 0000 C CNN +F 3 "" H 7150 8650 60 0000 C CNN + 1 7100 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 67A4FE40 +P 7050 9300 +F 0 "U6" H 7050 9200 60 0000 C CNN +F 1 "d_inverter" H 7050 9450 60 0000 C CNN +F 2 "" H 7100 9250 60 0000 C CNN +F 3 "" H 7100 9250 60 0000 C CNN + 1 7050 9300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 67A4FE4F +P 7150 11450 +F 0 "U9" H 7150 11350 60 0000 C CNN +F 1 "d_inverter" H 7150 11600 60 0000 C CNN +F 2 "" H 7200 11400 60 0000 C CNN +F 3 "" H 7200 11400 60 0000 C CNN + 1 7150 11450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 67A4FF04 +P 8400 4850 +F 0 "U10" H 8400 4750 60 0000 C CNN +F 1 "d_inverter" H 8400 5000 60 0000 C CNN +F 2 "" H 8450 4800 60 0000 C CNN +F 3 "" H 8450 4800 60 0000 C CNN + 1 8400 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 67A4FF41 +P 8400 7350 +F 0 "U11" H 8400 7250 60 0000 C CNN +F 1 "d_inverter" H 8400 7500 60 0000 C CNN +F 2 "" H 8450 7300 60 0000 C CNN +F 3 "" H 8450 7300 60 0000 C CNN + 1 8400 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 67A4FF6C +P 8400 8050 +F 0 "U12" H 8400 7950 60 0000 C CNN +F 1 "d_inverter" H 8400 8200 60 0000 C CNN +F 2 "" H 8450 8000 60 0000 C CNN +F 3 "" H 8450 8000 60 0000 C CNN + 1 8400 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 67A4FF9D +P 8400 8700 +F 0 "U13" H 8400 8600 60 0000 C CNN +F 1 "d_inverter" H 8400 8850 60 0000 C CNN +F 2 "" H 8450 8650 60 0000 C CNN +F 3 "" H 8450 8650 60 0000 C CNN + 1 8400 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 67A4FFE2 +P 8550 11450 +F 0 "U14" H 8550 11350 60 0000 C CNN +F 1 "d_inverter" H 8550 11600 60 0000 C CNN +F 2 "" H 8600 11400 60 0000 C CNN +F 3 "" H 8600 11400 60 0000 C CNN + 1 8550 11450 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X1 +U 1 1 67A500F9 +P 10400 4300 +F 0 "X1" H 10550 4200 60 0000 C CNN +F 1 "4_OR" H 10550 4400 60 0000 C CNN +F 2 "" H 10400 4300 60 0000 C CNN +F 3 "" H 10400 4300 60 0000 C CNN + 1 10400 4300 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X2 +U 1 1 67A5B522 +P 10400 5150 +F 0 "X2" H 10550 5050 60 0000 C CNN +F 1 "4_OR" H 10550 5250 60 0000 C CNN +F 2 "" H 10400 5150 60 0000 C CNN +F 3 "" H 10400 5150 60 0000 C CNN + 1 10400 5150 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X3 +U 1 1 67A5B8C6 +P 10400 7350 +F 0 "X3" H 10550 7250 60 0000 C CNN +F 1 "4_OR" H 10550 7450 60 0000 C CNN +F 2 "" H 10400 7350 60 0000 C CNN +F 3 "" H 10400 7350 60 0000 C CNN + 1 10400 7350 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X4 +U 1 1 67A5B911 +P 10400 8400 +F 0 "X4" H 10550 8300 60 0000 C CNN +F 1 "4_OR" H 10550 8500 60 0000 C CNN +F 2 "" H 10400 8400 60 0000 C CNN +F 3 "" H 10400 8400 60 0000 C CNN + 1 10400 8400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 67A5BD44 +P 11550 9600 +F 0 "U22" H 11550 9500 60 0000 C CNN +F 1 "d_inverter" H 11550 9750 60 0000 C CNN +F 2 "" H 11600 9550 60 0000 C CNN +F 3 "" H 11600 9550 60 0000 C CNN + 1 11550 9600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 67A5BDD7 +P 11650 10300 +F 0 "U23" H 11650 10200 60 0000 C CNN +F 1 "d_inverter" H 11650 10450 60 0000 C CNN +F 2 "" H 11700 10250 60 0000 C CNN +F 3 "" H 11700 10250 60 0000 C CNN + 1 11650 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U24 +U 1 1 67A5BEDF +P 13350 9650 +F 0 "U24" H 13350 9650 60 0000 C CNN +F 1 "d_nand" H 13400 9750 60 0000 C CNN +F 2 "" H 13350 9650 60 0000 C CNN +F 3 "" H 13350 9650 60 0000 C CNN + 1 13350 9650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 67A5BF59 +P 12500 4600 +F 0 "X5" H 12550 4550 60 0000 C CNN +F 1 "4_and" H 12600 4700 60 0000 C CNN +F 2 "" H 12500 4600 60 0000 C CNN +F 3 "" H 12500 4600 60 0000 C CNN + 1 12500 4600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 67A5BFC2 +P 12550 6050 +F 0 "X6" H 12600 6000 60 0000 C CNN +F 1 "4_and" H 12650 6150 60 0000 C CNN +F 2 "" H 12550 6050 60 0000 C CNN +F 3 "" H 12550 6050 60 0000 C CNN + 1 12550 6050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 67A5C035 +P 12550 7900 +F 0 "X7" H 12600 7850 60 0000 C CNN +F 1 "4_and" H 12650 8000 60 0000 C CNN +F 2 "" H 12550 7900 60 0000 C CNN +F 3 "" H 12550 7900 60 0000 C CNN + 1 12550 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 67A5C183 +P 13500 4600 +F 0 "U25" H 13500 4500 60 0000 C CNN +F 1 "d_inverter" H 13500 4750 60 0000 C CNN +F 2 "" H 13550 4550 60 0000 C CNN +F 3 "" H 13550 4550 60 0000 C CNN + 1 13500 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 67A5C189 +P 13650 6050 +F 0 "U27" H 13650 5950 60 0000 C CNN +F 1 "d_inverter" H 13650 6200 60 0000 C CNN +F 2 "" H 13700 6000 60 0000 C CNN +F 3 "" H 13700 6000 60 0000 C CNN + 1 13650 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U26 +U 1 1 67A5C18F +P 13600 7900 +F 0 "U26" H 13600 7800 60 0000 C CNN +F 1 "d_inverter" H 13600 8050 60 0000 C CNN +F 2 "" H 13650 7850 60 0000 C CNN +F 3 "" H 13650 7850 60 0000 C CNN + 1 13600 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U29 +U 1 1 67A5C873 +P 15300 4900 +F 0 "U29" H 15300 4900 60 0000 C CNN +F 1 "d_nand" H 15350 5000 60 0000 C CNN +F 2 "" H 15300 4900 60 0000 C CNN +F 3 "" H 15300 4900 60 0000 C CNN + 1 15300 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U30 +U 1 1 67A5C90C +P 15300 6800 +F 0 "U30" H 15300 6800 60 0000 C CNN +F 1 "d_nand" H 15350 6900 60 0000 C CNN +F 2 "" H 15300 6800 60 0000 C CNN +F 3 "" H 15300 6800 60 0000 C CNN + 1 15300 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U31 +U 1 1 67A5C99B +P 15350 8550 +F 0 "U31" H 15350 8550 60 0000 C CNN +F 1 "d_nand" H 15400 8650 60 0000 C CNN +F 2 "" H 15350 8550 60 0000 C CNN +F 3 "" H 15350 8550 60 0000 C CNN + 1 15350 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U32 +U 1 1 67A5CA32 +P 15400 10350 +F 0 "U32" H 15400 10350 60 0000 C CNN +F 1 "d_nand" H 15450 10450 60 0000 C CNN +F 2 "" H 15400 10350 60 0000 C CNN +F 3 "" H 15400 10350 60 0000 C CNN + 1 15400 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 67A5CB45 +P 16750 4850 +F 0 "U34" H 16750 4750 60 0000 C CNN +F 1 "d_inverter" H 16750 5000 60 0000 C CNN +F 2 "" H 16800 4800 60 0000 C CNN +F 3 "" H 16800 4800 60 0000 C CNN + 1 16750 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U33 +U 1 1 67A5CB4B +P 16700 6750 +F 0 "U33" H 16700 6650 60 0000 C CNN +F 1 "d_inverter" H 16700 6900 60 0000 C CNN +F 2 "" H 16750 6700 60 0000 C CNN +F 3 "" H 16750 6700 60 0000 C CNN + 1 16700 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U36 +U 1 1 67A5CB51 +P 16800 8500 +F 0 "U36" H 16800 8400 60 0000 C CNN +F 1 "d_inverter" H 16800 8650 60 0000 C CNN +F 2 "" H 16850 8450 60 0000 C CNN +F 3 "" H 16850 8450 60 0000 C CNN + 1 16800 8500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U37 +U 1 1 67A5CB57 +P 16800 10300 +F 0 "U37" H 16800 10200 60 0000 C CNN +F 1 "d_inverter" H 16800 10450 60 0000 C CNN +F 2 "" H 16850 10250 60 0000 C CNN +F 3 "" H 16850 10250 60 0000 C CNN + 1 16800 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 67A5CB5D +P 16750 10900 +F 0 "U35" H 16750 10800 60 0000 C CNN +F 1 "d_inverter" H 16750 11050 60 0000 C CNN +F 2 "" H 16800 10850 60 0000 C CNN +F 3 "" H 16800 10850 60 0000 C CNN + 1 16750 10900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U19 +U 1 1 67A5EBCA +P 10650 6200 +F 0 "U19" H 10650 6200 60 0000 C CNN +F 1 "d_or" H 10650 6300 60 0000 C CNN +F 2 "" H 10650 6200 60 0000 C CNN +F 3 "" H 10650 6200 60 0000 C CNN + 1 10650 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 4200 4450 4200 +Wire Wire Line + 6750 4850 4400 4850 +Wire Wire Line + 6750 6350 4350 6350 +Wire Wire Line + 6750 7350 4300 7350 +Wire Wire Line + 6800 8050 4200 8050 +Wire Wire Line + 6800 8700 4200 8700 +Wire Wire Line + 6750 9300 4200 9300 +Wire Wire Line + 6850 11450 3450 11450 +Wire Wire Line + 7450 11450 8250 11450 +Wire Wire Line + 7350 4200 7450 4200 +Wire Wire Line + 7450 4200 7450 4150 +Wire Wire Line + 7450 4150 10050 4150 +Wire Wire Line + 7350 4850 8100 4850 +Wire Wire Line + 8700 4850 9000 4850 +Wire Wire Line + 9000 4850 9000 4250 +Wire Wire Line + 9000 4250 10050 4250 +Wire Wire Line + 10050 4450 9800 4450 +Wire Wire Line + 9800 4450 9800 6900 +Wire Wire Line + 9800 5000 10050 5000 +Wire Wire Line + 9150 4350 10050 4350 +Wire Wire Line + 9800 6100 10200 6100 +Connection ~ 9800 5000 +Wire Wire Line + 9150 7300 10050 7300 +Wire Wire Line + 7850 4850 7850 5350 +Wire Wire Line + 7850 5350 9400 5350 +Wire Wire Line + 9400 5350 9400 7200 +Wire Wire Line + 9400 7200 10050 7200 +Connection ~ 7850 4850 +Wire Wire Line + 7350 6350 9250 6350 +Wire Wire Line + 9250 5200 9250 7600 +Wire Wire Line + 9250 7600 9850 7600 +Wire Wire Line + 9850 7600 9850 8250 +Wire Wire Line + 9850 8250 10050 8250 +Wire Wire Line + 9250 5200 10050 5200 +Connection ~ 9250 6350 +Wire Wire Line + 7350 7350 8100 7350 +Wire Wire Line + 7400 8050 8100 8050 +Wire Wire Line + 8100 8700 7400 8700 +Wire Wire Line + 8700 7350 9150 7350 +Wire Wire Line + 9150 4350 9150 7700 +Wire Wire Line + 9150 7700 9750 7700 +Wire Wire Line + 9750 7700 9750 8350 +Wire Wire Line + 9750 8350 10050 8350 +Connection ~ 9150 7350 +Wire Wire Line + 10050 5100 9150 5100 +Connection ~ 9150 5100 +Connection ~ 9150 7300 +Wire Wire Line + 7800 7350 7800 7800 +Wire Wire Line + 7800 7800 11450 7800 +Wire Wire Line + 11450 7800 11450 7750 +Wire Wire Line + 11450 7750 12150 7750 +Connection ~ 7800 7350 +Wire Wire Line + 8700 8050 9650 8050 +Wire Wire Line + 9650 7400 9650 8450 +Wire Wire Line + 9650 8450 10050 8450 +Wire Wire Line + 9650 7400 10050 7400 +Connection ~ 9650 8050 +Wire Wire Line + 7800 8050 7800 8250 +Wire Wire Line + 7800 8250 9500 8250 +Wire Wire Line + 9500 8250 9500 6200 +Wire Wire Line + 9500 6200 10200 6200 +Connection ~ 7800 8050 +Wire Wire Line + 9500 7900 11550 7900 +Wire Wire Line + 11550 7900 11550 7850 +Wire Wire Line + 11550 7850 12150 7850 +Connection ~ 9500 7900 +Wire Wire Line + 9800 6900 9300 6900 +Wire Wire Line + 9300 6900 9300 8700 +Wire Wire Line + 9300 8700 8700 8700 +Connection ~ 9800 6100 +Wire Wire Line + 7850 8700 7850 8900 +Wire Wire Line + 7850 8900 11800 8900 +Wire Wire Line + 11800 8900 11800 6100 +Wire Wire Line + 11800 7950 12150 7950 +Connection ~ 7850 8700 +Wire Wire Line + 11800 6100 12150 6100 +Connection ~ 11800 7950 +Wire Wire Line + 13050 6050 13350 6050 +Wire Wire Line + 13300 7900 13050 7900 +Wire Wire Line + 7350 9300 7650 9300 +Wire Wire Line + 7650 9300 7650 9000 +Wire Wire Line + 7650 9000 11950 9000 +Wire Wire Line + 11950 9000 11950 4750 +Wire Wire Line + 11950 8050 12150 8050 +Wire Wire Line + 11950 6200 12150 6200 +Connection ~ 11950 8050 +Wire Wire Line + 11950 4750 12100 4750 +Connection ~ 11950 6200 +Wire Wire Line + 6600 9300 6600 9500 +Wire Wire Line + 6600 9500 7750 9500 +Wire Wire Line + 7750 9500 7750 9450 +Wire Wire Line + 7750 9450 10200 9450 +Connection ~ 6600 9300 +Wire Wire Line + 6400 8700 6400 9600 +Wire Wire Line + 6400 9600 9750 9600 +Wire Wire Line + 9750 9600 9750 9550 +Wire Wire Line + 9750 9550 10200 9550 +Connection ~ 6400 8700 +Wire Wire Line + 6200 8050 6200 9700 +Wire Wire Line + 6200 9700 10200 9700 +Connection ~ 6200 8050 +Wire Wire Line + 6000 9800 10200 9800 +Wire Wire Line + 6000 9800 6000 7350 +Connection ~ 6000 7350 +Wire Wire Line + 5700 6350 5700 10150 +Wire Wire Line + 5700 10150 10250 10150 +Connection ~ 5700 6350 +Wire Wire Line + 5500 10250 10250 10250 +Wire Wire Line + 5500 10250 5500 4850 +Connection ~ 5500 4850 +Wire Wire Line + 10100 10400 5300 10400 +Wire Wire Line + 5300 10400 5300 4200 +Connection ~ 5300 4200 +Wire Wire Line + 3650 10500 10250 10500 +Connection ~ 6400 11450 +Wire Wire Line + 14650 10900 16450 10900 +Wire Wire Line + 8850 11450 14700 11450 +Wire Wire Line + 14700 11450 14700 4900 +Wire Wire Line + 14700 4900 14850 4900 +Wire Wire Line + 14850 6800 14700 6800 +Connection ~ 14700 6800 +Wire Wire Line + 14900 8550 14700 8550 +Connection ~ 14700 8550 +Wire Wire Line + 13800 9600 14300 9600 +Wire Wire Line + 14300 9600 14300 10250 +Wire Wire Line + 14300 10250 14950 10250 +Wire Wire Line + 15850 10300 16500 10300 +Wire Wire Line + 10950 4300 11850 4300 +Wire Wire Line + 11850 4300 11850 4450 +Wire Wire Line + 11850 4450 12100 4450 +Wire Wire Line + 10950 5150 11150 5150 +Wire Wire Line + 11150 5150 11150 4550 +Wire Wire Line + 11150 4550 12100 4550 +Wire Wire Line + 11100 6150 11450 6150 +Wire Wire Line + 11450 6150 11450 4650 +Wire Wire Line + 11450 4650 12100 4650 +Wire Wire Line + 10950 7350 11600 7350 +Wire Wire Line + 11600 7350 11600 5900 +Wire Wire Line + 11600 5900 12150 5900 +Wire Wire Line + 10950 8400 11700 8400 +Wire Wire Line + 11700 8400 11700 6000 +Wire Wire Line + 11700 6000 12150 6000 +Wire Wire Line + 13200 4600 13000 4600 +Wire Wire Line + 13800 4600 14400 4600 +Wire Wire Line + 14400 4600 14400 4800 +Wire Wire Line + 14400 4800 14850 4800 +Wire Wire Line + 13950 6050 14350 6050 +Wire Wire Line + 14350 6050 14350 6700 +Wire Wire Line + 14350 6700 14850 6700 +Wire Wire Line + 13900 7900 14400 7900 +Wire Wire Line + 14400 7900 14400 8450 +Wire Wire Line + 14400 8450 14900 8450 +Wire Wire Line + 15750 4850 16450 4850 +Wire Wire Line + 15750 6750 16400 6750 +Wire Wire Line + 16500 8500 15800 8500 +Wire Wire Line + 17050 4850 17950 4850 +Wire Wire Line + 17000 6750 18500 6750 +Wire Wire Line + 17100 8500 18550 8500 +Wire Wire Line + 17100 10300 18600 10300 +Wire Wire Line + 17050 10900 18600 10900 +$Comp +L PORT U1 +U 11 1 67A67004 +P 4200 4200 +F 0 "U1" H 4250 4300 30 0000 C CNN +F 1 "PORT" H 4200 4200 30 0000 C CNN +F 2 "" H 4200 4200 60 0000 C CNN +F 3 "" H 4200 4200 60 0000 C CNN + 11 4200 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 67A671AB +P 4150 4850 +F 0 "U1" H 4200 4950 30 0000 C CNN +F 1 "PORT" H 4150 4850 30 0000 C CNN +F 2 "" H 4150 4850 60 0000 C CNN +F 3 "" H 4150 4850 60 0000 C CNN + 12 4150 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67A673CE +P 4100 6350 +F 0 "U1" H 4150 6450 30 0000 C CNN +F 1 "PORT" H 4100 6350 30 0000 C CNN +F 2 "" H 4100 6350 60 0000 C CNN +F 3 "" H 4100 6350 60 0000 C CNN + 13 4100 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 67A675BD +P 4050 7350 +F 0 "U1" H 4100 7450 30 0000 C CNN +F 1 "PORT" H 4050 7350 30 0000 C CNN +F 2 "" H 4050 7350 60 0000 C CNN +F 3 "" H 4050 7350 60 0000 C CNN + 1 4050 7350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67A67752 +P 3950 8050 +F 0 "U1" H 4000 8150 30 0000 C CNN +F 1 "PORT" H 3950 8050 30 0000 C CNN +F 2 "" H 3950 8050 60 0000 C CNN +F 3 "" H 3950 8050 60 0000 C CNN + 2 3950 8050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67A67986 +P 3950 8700 +F 0 "U1" H 4000 8800 30 0000 C CNN +F 1 "PORT" H 3950 8700 30 0000 C CNN +F 2 "" H 3950 8700 60 0000 C CNN +F 3 "" H 3950 8700 60 0000 C CNN + 3 3950 8700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67A67BC3 +P 3950 9300 +F 0 "U1" H 4000 9400 30 0000 C CNN +F 1 "PORT" H 3950 9300 30 0000 C CNN +F 2 "" H 3950 9300 60 0000 C CNN +F 3 "" H 3950 9300 60 0000 C CNN + 4 3950 9300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67A67DDA +P 3400 10500 +F 0 "U1" H 3450 10600 30 0000 C CNN +F 1 "PORT" H 3400 10500 30 0000 C CNN +F 2 "" H 3400 10500 60 0000 C CNN +F 3 "" H 3400 10500 60 0000 C CNN + 10 3400 10500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67A67EF9 +P 3200 11450 +F 0 "U1" H 3250 11550 30 0000 C CNN +F 1 "PORT" H 3200 11450 30 0000 C CNN +F 2 "" H 3200 11450 60 0000 C CNN +F 3 "" H 3200 11450 60 0000 C CNN + 5 3200 11450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67A681F4 +P 18200 4850 +F 0 "U1" H 18250 4950 30 0000 C CNN +F 1 "PORT" H 18200 4850 30 0000 C CNN +F 2 "" H 18200 4850 60 0000 C CNN +F 3 "" H 18200 4850 60 0000 C CNN + 9 18200 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 67A68454 +P 18750 6750 +F 0 "U1" H 18800 6850 30 0000 C CNN +F 1 "PORT" H 18750 6750 30 0000 C CNN +F 2 "" H 18750 6750 60 0000 C CNN +F 3 "" H 18750 6750 60 0000 C CNN + 7 18750 6750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 67A68779 +P 18800 8500 +F 0 "U1" H 18850 8600 30 0000 C CNN +F 1 "PORT" H 18800 8500 30 0000 C CNN +F 2 "" H 18800 8500 60 0000 C CNN +F 3 "" H 18800 8500 60 0000 C CNN + 6 18800 8500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 67A68A78 +P 18850 10300 +F 0 "U1" H 18900 10400 30 0000 C CNN +F 1 "PORT" H 18850 10300 30 0000 C CNN +F 2 "" H 18850 10300 60 0000 C CNN +F 3 "" H 18850 10300 60 0000 C CNN + 14 18850 10300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 67A68BEF +P 18850 10900 +F 0 "U1" H 18900 11000 30 0000 C CNN +F 1 "PORT" H 18850 10900 30 0000 C CNN +F 2 "" H 18850 10900 60 0000 C CNN +F 3 "" H 18850 10900 60 0000 C CNN + 15 18850 10900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 67A68CDF +P 18650 9150 +F 0 "U1" H 18700 9250 30 0000 C CNN +F 1 "PORT" H 18650 9150 30 0000 C CNN +F 2 "" H 18650 9150 60 0000 C CNN +F 3 "" H 18650 9150 60 0000 C CNN + 8 18650 9150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 67A68D6C +P 18650 9350 +F 0 "U1" H 18700 9450 30 0000 C CNN +F 1 "PORT" H 18650 9350 30 0000 C CNN +F 2 "" H 18650 9350 60 0000 C CNN +F 3 "" H 18650 9350 60 0000 C CNN + 16 18650 9350 + 1 0 0 -1 +$EndComp +NoConn ~ 18900 9150 +NoConn ~ 18900 9350 +$Comp +L 4_OR X8 +U 1 1 67AA119F +P 10550 9600 +F 0 "X8" H 10700 9500 60 0000 C CNN +F 1 "4_OR" H 10700 9700 60 0000 C CNN +F 2 "" H 10550 9600 60 0000 C CNN +F 3 "" H 10550 9600 60 0000 C CNN + 1 10550 9600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10200 9700 10200 9650 +Wire Wire Line + 10200 9800 10200 9750 +$Comp +L 4_OR X9 +U 1 1 67AA15F9 +P 10600 10300 +F 0 "X9" H 10750 10200 60 0000 C CNN +F 1 "4_OR" H 10750 10400 60 0000 C CNN +F 2 "" H 10600 10300 60 0000 C CNN +F 3 "" H 10600 10300 60 0000 C CNN + 1 10600 10300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10250 10350 10100 10350 +Wire Wire Line + 10100 10350 10100 10400 +Wire Wire Line + 10250 10500 10250 10450 +Wire Wire Line + 11250 9600 11100 9600 +Wire Wire Line + 11350 10300 11150 10300 +$Comp +L d_inverter U16 +U 1 1 67AA23A3 +P 12750 10700 +F 0 "U16" H 12750 10600 60 0000 C CNN +F 1 "d_inverter" H 12750 10850 60 0000 C CNN +F 2 "" H 12800 10650 60 0000 C CNN +F 3 "" H 12800 10650 60 0000 C CNN + 1 12750 10700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 67AA2430 +P 12750 11050 +F 0 "U17" H 12750 10950 60 0000 C CNN +F 1 "d_inverter" H 12750 11200 60 0000 C CNN +F 2 "" H 12800 11000 60 0000 C CNN +F 3 "" H 12800 11000 60 0000 C CNN + 1 12750 11050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 67AA24BF +P 12750 10350 +F 0 "U15" H 12750 10250 60 0000 C CNN +F 1 "d_inverter" H 12750 10500 60 0000 C CNN +F 2 "" H 12800 10300 60 0000 C CNN +F 3 "" H 12800 10300 60 0000 C CNN + 1 12750 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U18 +U 1 1 67AA2582 +P 13650 10500 +F 0 "U18" H 13650 10500 60 0000 C CNN +F 1 "d_or" H 13650 10600 60 0000 C CNN +F 2 "" H 13650 10500 60 0000 C CNN +F 3 "" H 13650 10500 60 0000 C CNN + 1 13650 10500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U20 +U 1 1 67AA2694 +P 14200 10950 +F 0 "U20" H 14200 10950 60 0000 C CNN +F 1 "d_or" H 14200 11050 60 0000 C CNN +F 2 "" H 14200 10950 60 0000 C CNN +F 3 "" H 14200 10950 60 0000 C CNN + 1 14200 10950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14100 10450 14200 10450 +Wire Wire Line + 14200 10450 14200 10700 +Wire Wire Line + 14200 10700 13650 10700 +Wire Wire Line + 13650 10700 13650 10850 +Wire Wire Line + 13650 10850 13750 10850 +Wire Wire Line + 13050 10350 13200 10350 +Wire Wire Line + 13200 10350 13200 10400 +Wire Wire Line + 13200 10500 13200 10700 +Wire Wire Line + 13200 10700 13050 10700 +Wire Wire Line + 13050 11050 13650 11050 +Wire Wire Line + 13650 11050 13650 10950 +Wire Wire Line + 13650 10950 13750 10950 +Wire Wire Line + 6400 11050 12450 11050 +Wire Wire Line + 6400 11050 6400 11450 +Wire Wire Line + 11950 11050 11950 11250 +Wire Wire Line + 11950 11250 14800 11250 +Connection ~ 11950 11050 +Wire Wire Line + 14950 10350 14800 10350 +Wire Wire Line + 14800 10350 14800 11250 +Wire Wire Line + 11850 9600 12300 9600 +Wire Wire Line + 12300 9600 12300 9550 +Wire Wire Line + 12300 9550 12900 9550 +Wire Wire Line + 11950 10300 12250 10300 +Wire Wire Line + 12250 9950 12250 10350 +Wire Wire Line + 12250 9950 12650 9950 +Wire Wire Line + 12650 9950 12650 9650 +Wire Wire Line + 12650 9650 12900 9650 +Wire Wire Line + 12250 10350 12450 10350 +Connection ~ 12250 10300 +Wire Wire Line + 12100 9600 12100 10700 +Wire Wire Line + 12100 10700 12450 10700 +Connection ~ 12100 9600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.sub b/library/SubcircuitLibrary/CD4532B/CD4532B.sub new file mode 100644 index 00000000..4f812629 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.sub @@ -0,0 +1,153 @@ +* Subcircuit CD4532B +.subckt CD4532B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\cd4532b\cd4532b.cir +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad11_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u1-pad2_ net-_u12-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad4_ net-_u6-pad2_ d_inverter +* u9 net-_u1-pad5_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x1-pad5_ 4_OR +x2 net-_u13-pad2_ net-_u11-pad2_ net-_u4-pad2_ ? net-_x2-pad5_ 4_OR +x3 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x3-pad5_ 4_OR +x4 net-_u4-pad2_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x4-pad5_ 4_OR +* u22 net-_u22-pad1_ net-_u16-pad1_ d_inverter +* u23 net-_u23-pad1_ net-_u15-pad1_ d_inverter +* u24 net-_u16-pad1_ net-_u15-pad1_ net-_u24-pad3_ d_nand +x5 net-_x1-pad5_ net-_x2-pad5_ net-_u19-pad3_ net-_u6-pad2_ net-_u25-pad1_ 4_and +x6 net-_x3-pad5_ net-_x4-pad5_ net-_u13-pad1_ net-_u6-pad2_ net-_u27-pad1_ 4_and +x7 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u6-pad2_ net-_u26-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u29 net-_u25-pad2_ net-_u14-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u27-pad2_ net-_u14-pad2_ net-_u30-pad3_ d_nand +* u31 net-_u26-pad2_ net-_u14-pad2_ net-_u31-pad3_ d_nand +* u32 net-_u24-pad3_ net-_u1-pad5_ net-_u32-pad3_ d_nand +* u34 net-_u29-pad3_ net-_u1-pad9_ d_inverter +* u33 net-_u30-pad3_ net-_u1-pad7_ d_inverter +* u36 net-_u31-pad3_ net-_u1-pad6_ d_inverter +* u37 net-_u32-pad3_ net-_u1-pad14_ d_inverter +* u35 net-_u20-pad3_ net-_u1-pad15_ d_inverter +* u19 net-_u13-pad2_ net-_u12-pad1_ net-_u19-pad3_ d_or +x8 net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u22-pad1_ 4_OR +x9 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad10_ net-_u23-pad1_ 4_OR +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u1-pad5_ net-_u17-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u18 net-_u15-pad2_ net-_u16-pad2_ net-_u18-pad3_ d_or +* u20 net-_u18-pad3_ net-_u17-pad2_ net-_u20-pad3_ d_or +a1 net-_u1-pad11_ net-_u2-pad2_ u2 +a2 net-_u1-pad12_ net-_u10-pad1_ u3 +a3 net-_u1-pad13_ net-_u4-pad2_ u4 +a4 net-_u1-pad1_ net-_u11-pad1_ u5 +a5 net-_u1-pad2_ net-_u12-pad1_ u7 +a6 net-_u1-pad3_ net-_u13-pad1_ u8 +a7 net-_u1-pad4_ net-_u6-pad2_ u6 +a8 net-_u1-pad5_ net-_u14-pad1_ u9 +a9 net-_u10-pad1_ net-_u10-pad2_ u10 +a10 net-_u11-pad1_ net-_u11-pad2_ u11 +a11 net-_u12-pad1_ net-_u12-pad2_ u12 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u14-pad1_ net-_u14-pad2_ u14 +a14 net-_u22-pad1_ net-_u16-pad1_ u22 +a15 net-_u23-pad1_ net-_u15-pad1_ u23 +a16 [net-_u16-pad1_ net-_u15-pad1_ ] net-_u24-pad3_ u24 +a17 net-_u25-pad1_ net-_u25-pad2_ u25 +a18 net-_u27-pad1_ net-_u27-pad2_ u27 +a19 net-_u26-pad1_ net-_u26-pad2_ u26 +a20 [net-_u25-pad2_ net-_u14-pad2_ ] net-_u29-pad3_ u29 +a21 [net-_u27-pad2_ net-_u14-pad2_ ] net-_u30-pad3_ u30 +a22 [net-_u26-pad2_ net-_u14-pad2_ ] net-_u31-pad3_ u31 +a23 [net-_u24-pad3_ net-_u1-pad5_ ] net-_u32-pad3_ u32 +a24 net-_u29-pad3_ net-_u1-pad9_ u34 +a25 net-_u30-pad3_ net-_u1-pad7_ u33 +a26 net-_u31-pad3_ net-_u1-pad6_ u36 +a27 net-_u32-pad3_ net-_u1-pad14_ u37 +a28 net-_u20-pad3_ net-_u1-pad15_ u35 +a29 [net-_u13-pad2_ net-_u12-pad1_ ] net-_u19-pad3_ u19 +a30 net-_u16-pad1_ net-_u16-pad2_ u16 +a31 net-_u1-pad5_ net-_u17-pad2_ u17 +a32 net-_u15-pad1_ net-_u15-pad2_ u15 +a33 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a34 [net-_u18-pad3_ net-_u17-pad2_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends CD4532B
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml new file mode 100644 index 00000000..cd7a8a8d --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Rise Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Rise Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u22 name="type">d_inverter<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u22><u17 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u18><u23 name="type">d_inverter<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u27 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u27><u26 name="type">d_inverter<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u26><u28 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_nand<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_nand<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_nand<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_nand<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u32><u34 name="type">d_inverter<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u34><u33 name="type">d_inverter<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u33><u36 name="type">d_inverter<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u36><u37 name="type">d_inverter<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u37><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u35><u19 name="type">d_or<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_or<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_or<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u21><u38 name="type">d_inverter<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u38><u39 name="type">d_inverter<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u39><u16 name="type">d_inverter<field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /></u16><u17 name="type">d_inverter<field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /></u17><u15 name="type">d_inverter<field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /></u15></model><devicemodel /><subcircuit><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x8><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x4><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x7><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x3><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x2><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x9><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/analysis b/library/SubcircuitLibrary/CD4532B/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |