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| author | Sumanto Kar | 2024-11-21 22:09:07 +0530 |
|---|---|---|
| committer | GitHub | 2024-11-21 22:09:07 +0530 |
| commit | c7f8a75e51d3c79aaa994b25849bcb358543f12c (patch) | |
| tree | e0164ce8ed66b4b6d26fb522b37daed7d3d14dde /library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sub | |
| parent | 5aa4943922ff5af9bbb840782aaf26e72de40576 (diff) | |
| parent | 8e6fb624fda240239f9bfff67b40c28fba44e744 (diff) | |
| download | eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.tar.gz eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.tar.bz2 eSim-c7f8a75e51d3c79aaa994b25849bcb358543f12c.zip | |
Merge pull request #289 from Eyantra698Sumanto/master
Subcircuit Files of ICs(Contributor: Varad Patil)
Diffstat (limited to 'library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sub')
| -rw-r--r-- | library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sub | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sub b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sub new file mode 100644 index 00000000..8900cec3 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.sub @@ -0,0 +1,42 @@ +* Subcircuit 74LVC1G97 +.subckt 74LVC1G97 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\fossee\esim\library\subcircuitlibrary\74lvc1g97\74lvc1g97.cir +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u8 net-_u6-pad2_ net-_u5-pad2_ net-_u10-pad1_ d_and +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad4_ d_or +* u9 net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ d_and +* u7 net-_u3-pad2_ net-_u7-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +a1 net-_u1-pad2_ net-_u3-pad2_ u3 +a2 [net-_u6-pad2_ net-_u5-pad2_ ] net-_u10-pad1_ u8 +a3 net-_u2-pad2_ net-_u6-pad2_ u6 +a4 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad4_ u10 +a5 [net-_u7-pad2_ net-_u4-pad2_ ] net-_u10-pad2_ u9 +a6 net-_u3-pad2_ net-_u7-pad2_ u7 +a7 net-_u1-pad1_ net-_u2-pad2_ u2 +a8 net-_u1-pad3_ net-_u4-pad2_ u4 +a9 net-_u4-pad2_ net-_u5-pad2_ u5 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74LVC1G97
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