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| author | Sumanto Kar | 2024-11-21 21:32:02 +0530 |
|---|---|---|
| committer | Sumanto Kar | 2024-11-21 21:32:02 +0530 |
| commit | af9d45808f946536aeed78f96ab45dbdf01893ef (patch) | |
| tree | bdcdfe496d950b3b428266a5c706d768496f67f6 /library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir.out | |
| parent | 679f4f84b34014baa784d9f14ce4d0938244120c (diff) | |
| download | eSim-af9d45808f946536aeed78f96ab45dbdf01893ef.tar.gz eSim-af9d45808f946536aeed78f96ab45dbdf01893ef.tar.bz2 eSim-af9d45808f946536aeed78f96ab45dbdf01893ef.zip | |
74LVC1G97 is a configurable multiple-function gate
Diffstat (limited to 'library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir.out | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir.out b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir.out new file mode 100644 index 00000000..9148aa48 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G97/74LVC1G97.cir.out @@ -0,0 +1,48 @@ +* c:\fossee\esim\library\subcircuitlibrary\74lvc1g97\74lvc1g97.cir + +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u8 net-_u6-pad2_ net-_u5-pad2_ net-_u10-pad1_ d_and +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad4_ d_or +* u9 net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ d_and +* u7 net-_u3-pad2_ net-_u7-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 net-_u1-pad2_ net-_u3-pad2_ u3 +a2 [net-_u6-pad2_ net-_u5-pad2_ ] net-_u10-pad1_ u8 +a3 net-_u2-pad2_ net-_u6-pad2_ u6 +a4 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad4_ u10 +a5 [net-_u7-pad2_ net-_u4-pad2_ ] net-_u10-pad2_ u9 +a6 net-_u3-pad2_ net-_u7-pad2_ u7 +a7 net-_u1-pad1_ net-_u2-pad2_ u2 +a8 net-_u1-pad3_ net-_u4-pad2_ u4 +a9 net-_u4-pad2_ net-_u5-pad2_ u5 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |