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| author | Fahim | 2016-03-03 23:00:00 +0530 |
|---|---|---|
| committer | Fahim | 2016-03-03 23:00:00 +0530 |
| commit | 7e4774656997c34eae3ab09b37c8f82b5b046d48 (patch) | |
| tree | fe72483af0c1feba7f97d5b9290f647f50840fc1 /Examples/FullAdder | |
| parent | 823d892cbafccc47287ffebd01316754e7efad56 (diff) | |
| download | eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.tar.gz eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.tar.bz2 eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.zip | |
Remove unwanted example
Diffstat (limited to 'Examples/FullAdder')
25 files changed, 1862 insertions, 0 deletions
diff --git a/Examples/FullAdder/FullAdder-cache.lib b/Examples/FullAdder/FullAdder-cache.lib new file mode 100644 index 00000000..5669fdaf --- /dev/null +++ b/Examples/FullAdder/FullAdder-cache.lib @@ -0,0 +1,116 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/FullAdder/FullAdder.bak b/Examples/FullAdder/FullAdder.bak new file mode 100644 index 00000000..fb0b6864 --- /dev/null +++ b/Examples/FullAdder/FullAdder.bak @@ -0,0 +1,328 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L full_adder X1 +U 1 1 56D58C2E +P 4350 4050 +F 0 "X1" H 5750 4750 60 0000 C CNN +F 1 "full_adder" H 5750 4650 60 0000 C CNN +F 2 "" H 4350 4050 60 0000 C CNN +F 3 "" H 4350 4050 60 0000 C CNN + 1 4350 4050 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 56D58CB2 +P 1300 3550 +F 0 "v1" H 1100 3650 60 0000 C CNN +F 1 "DC" H 1100 3500 60 0000 C CNN +F 2 "R1" H 1000 3550 60 0000 C CNN +F 3 "" H 1300 3550 60 0000 C CNN + 1 1300 3550 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 56D58D3D +P 1950 3950 +F 0 "v2" H 1750 4050 60 0000 C CNN +F 1 "DC" H 1750 3900 60 0000 C CNN +F 2 "R1" H 1650 3950 60 0000 C CNN +F 3 "" H 1950 3950 60 0000 C CNN + 1 1950 3950 + 1 0 0 -1 +$EndComp +$Comp +L DC v3 +U 1 1 56D58D84 +P 2700 4350 +F 0 "v3" H 2500 4450 60 0000 C CNN +F 1 "DC" H 2500 4300 60 0000 C CNN +F 2 "R1" H 2400 4350 60 0000 C CNN +F 3 "" H 2700 4350 60 0000 C CNN + 1 2700 4350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 56D58F73 +P 8200 3200 +F 0 "R1" H 8250 3330 50 0000 C CNN +F 1 "1k" H 8250 3250 50 0000 C CNN +F 2 "" H 8250 3180 30 0000 C CNN +F 3 "" V 8250 3250 30 0000 C CNN + 1 8200 3200 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 56D58FBB +P 8200 4000 +F 0 "R2" H 8250 4130 50 0000 C CNN +F 1 "1k" H 8250 4050 50 0000 C CNN +F 2 "" H 8250 3980 30 0000 C CNN +F 3 "" V 8250 4050 30 0000 C CNN + 1 8200 4000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 56D59061 +P 8400 3150 +F 0 "#PWR01" H 8400 2900 50 0001 C CNN +F 1 "GND" H 8400 3000 50 0000 C CNN +F 2 "" H 8400 3150 50 0000 C CNN +F 3 "" H 8400 3150 50 0000 C CNN + 1 8400 3150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 56D590A3 +P 8400 3950 +F 0 "#PWR02" H 8400 3700 50 0001 C CNN +F 1 "GND" H 8400 3800 50 0000 C CNN +F 2 "" H 8400 3950 50 0000 C CNN +F 3 "" H 8400 3950 50 0000 C CNN + 1 8400 3950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 56D590F0 +P 2700 4800 +F 0 "#PWR03" H 2700 4550 50 0001 C CNN +F 1 "GND" H 2700 4650 50 0000 C CNN +F 2 "" H 2700 4800 50 0000 C CNN +F 3 "" H 2700 4800 50 0000 C CNN + 1 2700 4800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 56D59137 +P 1950 4450 +F 0 "#PWR04" H 1950 4200 50 0001 C CNN +F 1 "GND" H 1950 4300 50 0000 C CNN +F 2 "" H 1950 4450 50 0000 C CNN +F 3 "" H 1950 4450 50 0000 C CNN + 1 1950 4450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 56D59154 +P 1300 4000 +F 0 "#PWR05" H 1300 3750 50 0001 C CNN +F 1 "GND" H 1300 3850 50 0000 C CNN +F 2 "" H 1300 4000 50 0000 C CNN +F 3 "" H 1300 4000 50 0000 C CNN + 1 1300 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 3100 3300 3100 +Wire Wire Line + 1950 3500 3300 3500 +Wire Wire Line + 2700 3900 3300 3900 +$Comp +L plot_v1 U2 +U 1 1 56D59201 +P 2800 3250 +F 0 "U2" H 2800 3750 60 0000 C CNN +F 1 "plot_v1" H 3000 3600 60 0000 C CNN +F 2 "" H 2800 3250 60 0000 C CNN +F 3 "" H 2800 3250 60 0000 C CNN + 1 2800 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 56D59261 +P 2700 3700 +F 0 "U1" H 2700 4200 60 0000 C CNN +F 1 "plot_v1" H 2900 4050 60 0000 C CNN +F 2 "" H 2700 3700 60 0000 C CNN +F 3 "" H 2700 3700 60 0000 C CNN + 1 2700 3700 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 56D592AF +P 3050 4100 +F 0 "U3" H 3050 4600 60 0000 C CNN +F 1 "plot_v1" H 3250 4450 60 0000 C CNN +F 2 "" H 3050 4100 60 0000 C CNN +F 3 "" H 3050 4100 60 0000 C CNN + 1 3050 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 3050 2800 3100 +Connection ~ 2800 3100 +Connection ~ 2700 3500 +Connection ~ 3050 3900 +Wire Wire Line + 7850 3150 8100 3150 +Wire Wire Line + 7850 3950 8100 3950 +$Comp +L plot_v1 U4 +U 1 1 56D59437 +P 7900 3300 +F 0 "U4" H 7900 3800 60 0000 C CNN +F 1 "plot_v1" H 8100 3650 60 0000 C CNN +F 2 "" H 7900 3300 60 0000 C CNN +F 3 "" H 7900 3300 60 0000 C CNN + 1 7900 3300 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 56D59491 +P 7950 4100 +F 0 "U5" H 7950 4600 60 0000 C CNN +F 1 "plot_v1" H 8150 4450 60 0000 C CNN +F 2 "" H 7950 4100 60 0000 C CNN +F 3 "" H 7950 4100 60 0000 C CNN + 1 7950 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7950 3900 7950 3950 +Connection ~ 7950 3950 +Text GLabel 1900 3050 1 60 Input ~ 0 +in1 +Text GLabel 2150 3450 1 60 Input ~ 0 +in2 +Text GLabel 2850 3850 1 60 Input ~ 0 +cin +Text GLabel 8050 3200 3 60 Input ~ 0 +sum +Text GLabel 8050 4050 3 60 Input ~ 0 +cout +Wire Wire Line + 8050 3200 8050 3150 +Connection ~ 8050 3150 +Wire Wire Line + 8050 4050 8050 3950 +Connection ~ 8050 3950 +Wire Wire Line + 2850 3850 2850 3900 +Connection ~ 2850 3900 +Wire Wire Line + 2150 3450 2150 3500 +Connection ~ 2150 3500 +Wire Wire Line + 1900 3050 1900 3100 +Connection ~ 1900 3100 +$Comp +L adc_bridge_3 U6 +U 1 1 56D59BD2 +P 3900 3450 +F 0 "U6" H 3900 3450 60 0000 C CNN +F 1 "adc_bridge_3" H 3900 3600 60 0000 C CNN +F 2 "" H 3900 3450 60 0000 C CNN +F 3 "" H 3900 3450 60 0000 C CNN + 1 3900 3450 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U7 +U 1 1 56D5AD2F +P 7150 3450 +F 0 "U7" H 7150 3450 60 0000 C CNN +F 1 "dac_bridge_2" H 7200 3600 60 0000 C CNN +F 2 "" H 7150 3450 60 0000 C CNN +F 3 "" H 7150 3450 60 0000 C CNN + 1 7150 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 3100 6700 3100 +Wire Wire Line + 6700 3100 6700 3400 +Wire Wire Line + 6500 3900 6700 3900 +Wire Wire Line + 6700 3900 6700 3500 +Wire Wire Line + 7700 3400 7850 3400 +Wire Wire Line + 7850 3400 7850 3150 +Wire Wire Line + 7900 3100 7900 3150 +Connection ~ 7900 3150 +Wire Wire Line + 7700 3500 7850 3500 +Wire Wire Line + 7850 3500 7850 3950 +Wire Wire Line + 3300 3900 3300 3600 +Wire Wire Line + 3300 3100 3300 3400 +Wire Wire Line + 4450 3500 4950 3500 +Wire Wire Line + 4450 3400 4450 3100 +Wire Wire Line + 4450 3100 4950 3100 +Wire Wire Line + 4450 3600 4450 3900 +Wire Wire Line + 4450 3900 4950 3900 +$EndSCHEMATC diff --git a/Examples/FullAdder/FullAdder.cir b/Examples/FullAdder/FullAdder.cir new file mode 100644 index 00000000..c4eb27c7 --- /dev/null +++ b/Examples/FullAdder/FullAdder.cir @@ -0,0 +1,23 @@ +* /home/fossee/eSim-Workspace/FullAdder/FullAdder.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Mar 1 18:16:27 2016 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U6-Pad4_ Net-_U6-Pad5_ Net-_U6-Pad6_ Net-_U7-Pad1_ Net-_U7-Pad2_ full_adder +v1 in1 GND DC +v2 in2 GND DC +v3 cin GND DC +R1 sum GND 1k +R2 cout GND 1k +U2 in1 plot_v1 +U1 in2 plot_v1 +U3 cin plot_v1 +U4 sum plot_v1 +U5 cout plot_v1 +U6 in1 in2 cin Net-_U6-Pad4_ Net-_U6-Pad5_ Net-_U6-Pad6_ adc_bridge_3 +U7 Net-_U7-Pad1_ Net-_U7-Pad2_ sum cout dac_bridge_2 + +.end diff --git a/Examples/FullAdder/FullAdder.cir.out b/Examples/FullAdder/FullAdder.cir.out new file mode 100644 index 00000000..89cd256c --- /dev/null +++ b/Examples/FullAdder/FullAdder.cir.out @@ -0,0 +1,36 @@ +* /home/fossee/esim-workspace/fulladder/fulladder.cir + +.include full_adder.sub +x1 net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ net-_u7-pad1_ net-_u7-pad2_ full_adder +v1 in1 gnd dc 5 +v2 in2 gnd dc 0 +v3 cin gnd dc 5 +r1 sum gnd 1k +r2 cout gnd 1k +* u2 in1 plot_v1 +* u1 in2 plot_v1 +* u3 cin plot_v1 +* u4 sum plot_v1 +* u5 cout plot_v1 +* u6 in1 in2 cin net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ adc_bridge_3 +* u7 net-_u7-pad1_ net-_u7-pad2_ sum cout dac_bridge_2 +a1 [in1 in2 cin ] [net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ ] u6 +a2 [net-_u7-pad1_ net-_u7-pad2_ ] [sum cout ] u7 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u6 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u7 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-00 100e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in1) +plot v(in2) +plot v(cin) +plot v(sum) +plot v(cout) +.endc +.end diff --git a/Examples/FullAdder/FullAdder.pro b/Examples/FullAdder/FullAdder.pro new file mode 100644 index 00000000..afdcf2d3 --- /dev/null +++ b/Examples/FullAdder/FullAdder.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Power +LibName7=eSim_Sources +LibName8=eSim_Subckt +LibName9=eSim_User +LibName10=eSim_Plot +LibName11=adc-dac +LibName12=memory +LibName13=xilinx +LibName14=microcontrollers +LibName15=dsp +LibName16=microchip +LibName17=analog_switches +LibName18=motorola +LibName19=texas +LibName20=intel +LibName21=audio +LibName22=interface +LibName23=digital-audio +LibName24=philips +LibName25=display +LibName26=cypress +LibName27=siliconi +LibName28=opto +LibName29=atmel +LibName30=contrib +LibName31=power +LibName32=device +LibName33=transistors +LibName34=conn +LibName35=linear +LibName36=regul +LibName37=74xx +LibName38=cmos4000 diff --git a/Examples/FullAdder/FullAdder.proj b/Examples/FullAdder/FullAdder.proj new file mode 100644 index 00000000..2a30e6b7 --- /dev/null +++ b/Examples/FullAdder/FullAdder.proj @@ -0,0 +1 @@ +schematicFile FullAdder.sch diff --git a/Examples/FullAdder/FullAdder.sch b/Examples/FullAdder/FullAdder.sch new file mode 100644 index 00000000..7e0995aa --- /dev/null +++ b/Examples/FullAdder/FullAdder.sch @@ -0,0 +1,330 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L full_adder X1 +U 1 1 56D58C2E +P 4350 4050 +F 0 "X1" H 5750 4750 60 0000 C CNN +F 1 "full_adder" H 5750 4650 60 0000 C CNN +F 2 "" H 4350 4050 60 0000 C CNN +F 3 "" H 4350 4050 60 0000 C CNN + 1 4350 4050 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 56D58CB2 +P 1300 3550 +F 0 "v1" H 1100 3650 60 0000 C CNN +F 1 "DC" H 1100 3500 60 0000 C CNN +F 2 "R1" H 1000 3550 60 0000 C CNN +F 3 "" H 1300 3550 60 0000 C CNN + 1 1300 3550 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 56D58D3D +P 1950 3950 +F 0 "v2" H 1750 4050 60 0000 C CNN +F 1 "DC" H 1750 3900 60 0000 C CNN +F 2 "R1" H 1650 3950 60 0000 C CNN +F 3 "" H 1950 3950 60 0000 C CNN + 1 1950 3950 + 1 0 0 -1 +$EndComp +$Comp +L DC v3 +U 1 1 56D58D84 +P 2700 4350 +F 0 "v3" H 2500 4450 60 0000 C CNN +F 1 "DC" H 2500 4300 60 0000 C CNN +F 2 "R1" H 2400 4350 60 0000 C CNN +F 3 "" H 2700 4350 60 0000 C CNN + 1 2700 4350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 56D58F73 +P 8200 3200 +F 0 "R1" H 8250 3330 50 0000 C CNN +F 1 "1k" H 8250 3250 50 0000 C CNN +F 2 "" H 8250 3180 30 0000 C CNN +F 3 "" V 8250 3250 30 0000 C CNN + 1 8200 3200 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 56D58FBB +P 8200 4000 +F 0 "R2" H 8250 4130 50 0000 C CNN +F 1 "1k" H 8250 4050 50 0000 C CNN +F 2 "" H 8250 3980 30 0000 C CNN +F 3 "" V 8250 4050 30 0000 C CNN + 1 8200 4000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 56D59061 +P 8400 3150 +F 0 "#PWR01" H 8400 2900 50 0001 C CNN +F 1 "GND" H 8400 3000 50 0000 C CNN +F 2 "" H 8400 3150 50 0000 C CNN +F 3 "" H 8400 3150 50 0000 C CNN + 1 8400 3150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 56D590A3 +P 8400 3950 +F 0 "#PWR02" H 8400 3700 50 0001 C CNN +F 1 "GND" H 8400 3800 50 0000 C CNN +F 2 "" H 8400 3950 50 0000 C CNN +F 3 "" H 8400 3950 50 0000 C CNN + 1 8400 3950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 56D590F0 +P 2700 4800 +F 0 "#PWR03" H 2700 4550 50 0001 C CNN +F 1 "GND" H 2700 4650 50 0000 C CNN +F 2 "" H 2700 4800 50 0000 C CNN +F 3 "" H 2700 4800 50 0000 C CNN + 1 2700 4800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 56D59137 +P 1950 4450 +F 0 "#PWR04" H 1950 4200 50 0001 C CNN +F 1 "GND" H 1950 4300 50 0000 C CNN +F 2 "" H 1950 4450 50 0000 C CNN +F 3 "" H 1950 4450 50 0000 C CNN + 1 1950 4450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 56D59154 +P 1300 4000 +F 0 "#PWR05" H 1300 3750 50 0001 C CNN +F 1 "GND" H 1300 3850 50 0000 C CNN +F 2 "" H 1300 4000 50 0000 C CNN +F 3 "" H 1300 4000 50 0000 C CNN + 1 1300 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 3100 3300 3100 +Wire Wire Line + 2700 3900 3300 3900 +$Comp +L plot_v1 U2 +U 1 1 56D59201 +P 2800 3250 +F 0 "U2" H 2800 3750 60 0000 C CNN +F 1 "plot_v1" H 3000 3600 60 0000 C CNN +F 2 "" H 2800 3250 60 0000 C CNN +F 3 "" H 2800 3250 60 0000 C CNN + 1 2800 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 56D59261 +P 2700 3700 +F 0 "U1" H 2700 4200 60 0000 C CNN +F 1 "plot_v1" H 2900 4050 60 0000 C CNN +F 2 "" H 2700 3700 60 0000 C CNN +F 3 "" H 2700 3700 60 0000 C CNN + 1 2700 3700 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 56D592AF +P 3050 4100 +F 0 "U3" H 3050 4600 60 0000 C CNN +F 1 "plot_v1" H 3250 4450 60 0000 C CNN +F 2 "" H 3050 4100 60 0000 C CNN +F 3 "" H 3050 4100 60 0000 C CNN + 1 3050 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 3050 2800 3100 +Connection ~ 2800 3100 +Connection ~ 2700 3500 +Connection ~ 3050 3900 +Wire Wire Line + 7850 3150 8100 3150 +Wire Wire Line + 7850 3950 8100 3950 +$Comp +L plot_v1 U4 +U 1 1 56D59437 +P 7900 3300 +F 0 "U4" H 7900 3800 60 0000 C CNN +F 1 "plot_v1" H 8100 3650 60 0000 C CNN +F 2 "" H 7900 3300 60 0000 C CNN +F 3 "" H 7900 3300 60 0000 C CNN + 1 7900 3300 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 56D59491 +P 7950 4100 +F 0 "U5" H 7950 4600 60 0000 C CNN +F 1 "plot_v1" H 8150 4450 60 0000 C CNN +F 2 "" H 7950 4100 60 0000 C CNN +F 3 "" H 7950 4100 60 0000 C CNN + 1 7950 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7950 3900 7950 3950 +Connection ~ 7950 3950 +Text GLabel 1900 3050 1 60 Input ~ 0 +in1 +Text GLabel 2150 3450 1 60 Input ~ 0 +in2 +Text GLabel 2850 3850 1 60 Input ~ 0 +cin +Text GLabel 8050 3200 3 60 Input ~ 0 +sum +Text GLabel 8050 4050 3 60 Input ~ 0 +cout +Wire Wire Line + 8050 3200 8050 3150 +Connection ~ 8050 3150 +Wire Wire Line + 8050 4050 8050 3950 +Connection ~ 8050 3950 +Wire Wire Line + 2850 3850 2850 3900 +Connection ~ 2850 3900 +Wire Wire Line + 2150 3450 2150 3500 +Connection ~ 2150 3500 +Wire Wire Line + 1900 3050 1900 3100 +Connection ~ 1900 3100 +$Comp +L adc_bridge_3 U6 +U 1 1 56D59BD2 +P 3900 3450 +F 0 "U6" H 3900 3450 60 0000 C CNN +F 1 "adc_bridge_3" H 3900 3600 60 0000 C CNN +F 2 "" H 3900 3450 60 0000 C CNN +F 3 "" H 3900 3450 60 0000 C CNN + 1 3900 3450 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U7 +U 1 1 56D5AD2F +P 7150 3450 +F 0 "U7" H 7150 3450 60 0000 C CNN +F 1 "dac_bridge_2" H 7200 3600 60 0000 C CNN +F 2 "" H 7150 3450 60 0000 C CNN +F 3 "" H 7150 3450 60 0000 C CNN + 1 7150 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 3100 6700 3100 +Wire Wire Line + 6700 3100 6700 3400 +Wire Wire Line + 6500 3900 6700 3900 +Wire Wire Line + 6700 3900 6700 3500 +Wire Wire Line + 7700 3400 7850 3400 +Wire Wire Line + 7850 3400 7850 3150 +Wire Wire Line + 7900 3100 7900 3150 +Connection ~ 7900 3150 +Wire Wire Line + 7700 3500 7850 3500 +Wire Wire Line + 7850 3500 7850 3950 +Wire Wire Line + 3300 3900 3300 3600 +Wire Wire Line + 3300 3100 3300 3400 +Wire Wire Line + 4450 3500 4950 3500 +Wire Wire Line + 4450 3400 4450 3100 +Wire Wire Line + 4450 3100 4950 3100 +Wire Wire Line + 4450 3600 4450 3900 +Wire Wire Line + 4450 3900 4950 3900 +Wire Wire Line + 1950 3500 3300 3500 +Wire Wire Line + 1950 4400 1950 4450 +$EndSCHEMATC diff --git a/Examples/FullAdder/FullAdder_Previous_Values.xml b/Examples/FullAdder/FullAdder_Previous_Values.xml new file mode 100644 index 00000000..3265600d --- /dev/null +++ b/Examples/FullAdder/FullAdder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v3 name="Source type">dc<field1 name="Value">5</field1></v3></source><model><u6 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u6><u7 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/fossee/esim-clones/eSim/src/SubcircuitLibrary/full_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/FullAdder/analysis b/Examples/FullAdder/analysis new file mode 100644 index 00000000..27cb8231 --- /dev/null +++ b/Examples/FullAdder/analysis @@ -0,0 +1 @@ +.tran 10e-00 100e-00 0e-00
\ No newline at end of file diff --git a/Examples/FullAdder/full_adder-cache.lib b/Examples/FullAdder/full_adder-cache.lib new file mode 100644 index 00000000..623a7f41 --- /dev/null +++ b/Examples/FullAdder/full_adder-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/FullAdder/full_adder.cir b/Examples/FullAdder/full_adder.cir new file mode 100644 index 00000000..6461b5b6 --- /dev/null +++ b/Examples/FullAdder/full_adder.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 8 7 6 2 half_adder +X2 5 6 4 3 half_adder +U1 8 7 5 4 1 PORT +U2 3 2 1 d_or + +.end diff --git a/Examples/FullAdder/full_adder.cir.out b/Examples/FullAdder/full_adder.cir.out new file mode 100644 index 00000000..b90ce70d --- /dev/null +++ b/Examples/FullAdder/full_adder.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 + +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u1 8 7 5 4 1 port +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/FullAdder/full_adder.pro b/Examples/FullAdder/full_adder.pro new file mode 100644 index 00000000..c0db0775 --- /dev/null +++ b/Examples/FullAdder/full_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 12:19:16 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/FullAdder/full_adder.sch b/Examples/FullAdder/full_adder.sch new file mode 100644 index 00000000..8bd400f2 --- /dev/null +++ b/Examples/FullAdder/full_adder.sch @@ -0,0 +1,180 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L half_adder X1 +U 1 1 558AA064 +P 3800 3350 +F 0 "X1" H 4700 3850 60 0000 C CNN +F 1 "half_adder" H 4700 3750 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L half_adder X2 +U 1 1 558AA0C1 +P 5700 3350 +F 0 "X2" H 6600 3850 60 0000 C CNN +F 1 "half_adder" H 6600 3750 60 0000 C CNN +F 2 "" H 5700 3350 60 0000 C CNN +F 3 "" H 5700 3350 60 0000 C CNN + 1 5700 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558AA277 +P 3450 2650 +F 0 "U1" H 3500 2750 30 0000 C CNN +F 1 "PORT" H 3450 2650 30 0000 C CNN +F 2 "" H 3450 2650 60 0000 C CNN +F 3 "" H 3450 2650 60 0000 C CNN + 1 3450 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558AA29E +P 3450 3250 +F 0 "U1" H 3500 3350 30 0000 C CNN +F 1 "PORT" H 3450 3250 30 0000 C CNN +F 2 "" H 3450 3250 60 0000 C CNN +F 3 "" H 3450 3250 60 0000 C CNN + 2 3450 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558AA2D8 +P 5650 2300 +F 0 "U1" H 5700 2400 30 0000 C CNN +F 1 "PORT" H 5650 2300 30 0000 C CNN +F 2 "" H 5650 2300 60 0000 C CNN +F 3 "" H 5650 2300 60 0000 C CNN + 3 5650 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 558AA378 +P 7900 2650 +F 0 "U1" H 7950 2750 30 0000 C CNN +F 1 "PORT" H 7900 2650 30 0000 C CNN +F 2 "" H 7900 2650 60 0000 C CNN +F 3 "" H 7900 2650 60 0000 C CNN + 4 7900 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 558AA3E0 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 5 8700 3400 + -1 0 0 1 +$EndComp +$Comp +L d_or U2 +U 1 1 558AA43B +P 7900 3450 +F 0 "U2" H 7900 3450 60 0000 C CNN +F 1 "d_or" H 7900 3550 60 0000 C CNN +F 2 "" H 7900 3450 60 0000 C CNN +F 3 "" H 7900 3450 60 0000 C CNN + 1 7900 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 2650 4100 2650 +Wire Wire Line + 3700 3250 4100 3250 +Wire Wire Line + 5250 2650 5650 2650 +Wire Wire Line + 5650 2650 5650 3250 +Wire Wire Line + 5650 3250 6000 3250 +Wire Wire Line + 5900 2300 5900 2650 +Wire Wire Line + 5900 2650 6000 2650 +Wire Wire Line + 7150 2650 7650 2650 +Wire Wire Line + 7150 3250 7350 3250 +Wire Wire Line + 7350 3250 7350 3350 +Wire Wire Line + 7350 3350 7450 3350 +Wire Wire Line + 5250 3250 5400 3250 +Wire Wire Line + 5400 3250 5400 3450 +Wire Wire Line + 5400 3450 7450 3450 +Wire Wire Line + 8350 3400 8450 3400 +Text Notes 3850 2500 0 60 ~ 0 +IN1 +Text Notes 3850 3150 0 60 ~ 0 +IN2 +Text Notes 6000 2350 0 60 ~ 0 +CIN +Text Notes 7350 2550 0 60 ~ 0 +SUM +Text Notes 8300 3200 0 60 ~ 0 +COUT +$EndSCHEMATC diff --git a/Examples/FullAdder/full_adder.sub b/Examples/FullAdder/full_adder.sub new file mode 100644 index 00000000..5f261f78 --- /dev/null +++ b/Examples/FullAdder/full_adder.sub @@ -0,0 +1,13 @@ +* Subcircuit full_adder +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder
\ No newline at end of file diff --git a/Examples/FullAdder/full_adder_Previous_Values.xml b/Examples/FullAdder/full_adder_Previous_Values.xml new file mode 100644 index 00000000..b63184d6 --- /dev/null +++ b/Examples/FullAdder/full_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/FullAdder/half_adder-cache.lib b/Examples/FullAdder/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/Examples/FullAdder/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/FullAdder/half_adder.cir b/Examples/FullAdder/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/Examples/FullAdder/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/Examples/FullAdder/half_adder.cir.out b/Examples/FullAdder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/Examples/FullAdder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/FullAdder/half_adder.pro b/Examples/FullAdder/half_adder.pro new file mode 100644 index 00000000..695ae0f6 --- /dev/null +++ b/Examples/FullAdder/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Jun 24 11:27:22 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources +LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt diff --git a/Examples/FullAdder/half_adder.sch b/Examples/FullAdder/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/Examples/FullAdder/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/Examples/FullAdder/half_adder.sub b/Examples/FullAdder/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/Examples/FullAdder/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/Examples/FullAdder/half_adder_Previous_Values.xml b/Examples/FullAdder/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/Examples/FullAdder/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/FullAdder/plot_data_i.txt b/Examples/FullAdder/plot_data_i.txt new file mode 100644 index 00000000..5181eed8 --- /dev/null +++ b/Examples/FullAdder/plot_data_i.txt @@ -0,0 +1,135 @@ + * /home/fossee/esim-workspace/fulladder/fulladder.cir + Transient Analysis Thu Mar 3 21:20:17 2016 +-------------------------------------------------------------------------------- +Index time a2#branch_1_0 a2#branch_1_1 v1#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 -5.00000e-03 0.000000e+00 +1 1.000000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +2 2.000000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +3 4.000000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +4 8.000000e-02 0.000000e+00 -5.00000e-03 0.000000e+00 +5 1.600000e-01 0.000000e+00 -5.00000e-03 0.000000e+00 +6 3.200000e-01 0.000000e+00 -5.00000e-03 0.000000e+00 +7 6.400000e-01 0.000000e+00 -5.00000e-03 0.000000e+00 +8 1.280000e+00 0.000000e+00 -5.00000e-03 0.000000e+00 +9 2.560000e+00 0.000000e+00 -5.00000e-03 0.000000e+00 +10 4.560000e+00 0.000000e+00 -5.00000e-03 0.000000e+00 +11 6.560000e+00 0.000000e+00 -5.00000e-03 0.000000e+00 +12 8.560000e+00 0.000000e+00 -5.00000e-03 0.000000e+00 +13 1.056000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +14 1.256000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +15 1.456000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +16 1.656000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +17 1.856000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +18 2.056000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +19 2.256000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +20 2.456000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +21 2.656000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +22 2.856000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +23 3.056000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +24 3.256000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +25 3.456000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +26 3.656000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +27 3.856000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +28 4.056000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +29 4.256000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +30 4.456000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +31 4.656000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +32 4.856000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +33 5.056000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +34 5.256000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +35 5.456000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +36 5.656000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +37 5.856000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +38 6.056000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +39 6.256000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +40 6.456000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +41 6.656000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +42 6.856000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +43 7.056000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +44 7.256000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +45 7.456000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +46 7.656000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +47 7.856000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +48 8.056000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +49 8.256000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +50 8.456000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +51 8.656000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +52 8.856000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +53 9.056000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +54 9.256000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 + +Index time a2#branch_1_0 a2#branch_1_1 v1#branch +-------------------------------------------------------------------------------- +55 9.456000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +56 9.656000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +57 9.856000e+01 0.000000e+00 -5.00000e-03 0.000000e+00 +58 1.000000e+02 0.000000e+00 -5.00000e-03 0.000000e+00 + + * /home/fossee/esim-workspace/fulladder/fulladder.cir + Transient Analysis Thu Mar 3 21:20:17 2016 +-------------------------------------------------------------------------------- +Index time v2#branch v3#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-02 0.000000e+00 0.000000e+00 +2 2.000000e-02 0.000000e+00 0.000000e+00 +3 4.000000e-02 0.000000e+00 0.000000e+00 +4 8.000000e-02 0.000000e+00 0.000000e+00 +5 1.600000e-01 0.000000e+00 0.000000e+00 +6 3.200000e-01 0.000000e+00 0.000000e+00 +7 6.400000e-01 0.000000e+00 0.000000e+00 +8 1.280000e+00 0.000000e+00 0.000000e+00 +9 2.560000e+00 0.000000e+00 0.000000e+00 +10 4.560000e+00 0.000000e+00 0.000000e+00 +11 6.560000e+00 0.000000e+00 0.000000e+00 +12 8.560000e+00 0.000000e+00 0.000000e+00 +13 1.056000e+01 0.000000e+00 0.000000e+00 +14 1.256000e+01 0.000000e+00 0.000000e+00 +15 1.456000e+01 0.000000e+00 0.000000e+00 +16 1.656000e+01 0.000000e+00 0.000000e+00 +17 1.856000e+01 0.000000e+00 0.000000e+00 +18 2.056000e+01 0.000000e+00 0.000000e+00 +19 2.256000e+01 0.000000e+00 0.000000e+00 +20 2.456000e+01 0.000000e+00 0.000000e+00 +21 2.656000e+01 0.000000e+00 0.000000e+00 +22 2.856000e+01 0.000000e+00 0.000000e+00 +23 3.056000e+01 0.000000e+00 0.000000e+00 +24 3.256000e+01 0.000000e+00 0.000000e+00 +25 3.456000e+01 0.000000e+00 0.000000e+00 +26 3.656000e+01 0.000000e+00 0.000000e+00 +27 3.856000e+01 0.000000e+00 0.000000e+00 +28 4.056000e+01 0.000000e+00 0.000000e+00 +29 4.256000e+01 0.000000e+00 0.000000e+00 +30 4.456000e+01 0.000000e+00 0.000000e+00 +31 4.656000e+01 0.000000e+00 0.000000e+00 +32 4.856000e+01 0.000000e+00 0.000000e+00 +33 5.056000e+01 0.000000e+00 0.000000e+00 +34 5.256000e+01 0.000000e+00 0.000000e+00 +35 5.456000e+01 0.000000e+00 0.000000e+00 +36 5.656000e+01 0.000000e+00 0.000000e+00 +37 5.856000e+01 0.000000e+00 0.000000e+00 +38 6.056000e+01 0.000000e+00 0.000000e+00 +39 6.256000e+01 0.000000e+00 0.000000e+00 +40 6.456000e+01 0.000000e+00 0.000000e+00 +41 6.656000e+01 0.000000e+00 0.000000e+00 +42 6.856000e+01 0.000000e+00 0.000000e+00 +43 7.056000e+01 0.000000e+00 0.000000e+00 +44 7.256000e+01 0.000000e+00 0.000000e+00 +45 7.456000e+01 0.000000e+00 0.000000e+00 +46 7.656000e+01 0.000000e+00 0.000000e+00 +47 7.856000e+01 0.000000e+00 0.000000e+00 +48 8.056000e+01 0.000000e+00 0.000000e+00 +49 8.256000e+01 0.000000e+00 0.000000e+00 +50 8.456000e+01 0.000000e+00 0.000000e+00 +51 8.656000e+01 0.000000e+00 0.000000e+00 +52 8.856000e+01 0.000000e+00 0.000000e+00 +53 9.056000e+01 0.000000e+00 0.000000e+00 +54 9.256000e+01 0.000000e+00 0.000000e+00 + +Index time v2#branch v3#branch +-------------------------------------------------------------------------------- +55 9.456000e+01 0.000000e+00 0.000000e+00 +56 9.656000e+01 0.000000e+00 0.000000e+00 +57 9.856000e+01 0.000000e+00 0.000000e+00 +58 1.000000e+02 0.000000e+00 0.000000e+00 diff --git a/Examples/FullAdder/plot_data_v.txt b/Examples/FullAdder/plot_data_v.txt new file mode 100644 index 00000000..5acf1a03 --- /dev/null +++ b/Examples/FullAdder/plot_data_v.txt @@ -0,0 +1,135 @@ + * /home/fossee/esim-workspace/fulladder/fulladder.cir + Transient Analysis Thu Mar 3 21:20:17 2016 +-------------------------------------------------------------------------------- +Index time cin cout in1 +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 5.000000e+00 5.000000e+00 +1 1.000000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +2 2.000000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +3 4.000000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +4 8.000000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +5 1.600000e-01 5.000000e+00 5.000000e+00 5.000000e+00 +6 3.200000e-01 5.000000e+00 5.000000e+00 5.000000e+00 +7 6.400000e-01 5.000000e+00 5.000000e+00 5.000000e+00 +8 1.280000e+00 5.000000e+00 5.000000e+00 5.000000e+00 +9 2.560000e+00 5.000000e+00 5.000000e+00 5.000000e+00 +10 4.560000e+00 5.000000e+00 5.000000e+00 5.000000e+00 +11 6.560000e+00 5.000000e+00 5.000000e+00 5.000000e+00 +12 8.560000e+00 5.000000e+00 5.000000e+00 5.000000e+00 +13 1.056000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +14 1.256000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +15 1.456000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +16 1.656000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +17 1.856000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +18 2.056000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +19 2.256000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +20 2.456000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +21 2.656000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +22 2.856000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +23 3.056000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +24 3.256000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +25 3.456000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +26 3.656000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +27 3.856000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +28 4.056000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +29 4.256000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +30 4.456000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +31 4.656000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +32 4.856000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +33 5.056000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +34 5.256000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +35 5.456000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +36 5.656000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +37 5.856000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +38 6.056000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +39 6.256000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +40 6.456000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +41 6.656000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +42 6.856000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +43 7.056000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +44 7.256000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +45 7.456000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +46 7.656000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +47 7.856000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +48 8.056000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +49 8.256000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +50 8.456000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +51 8.656000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +52 8.856000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +53 9.056000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +54 9.256000e+01 5.000000e+00 5.000000e+00 5.000000e+00 + +Index time cin cout in1 +-------------------------------------------------------------------------------- +55 9.456000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +56 9.656000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +57 9.856000e+01 5.000000e+00 5.000000e+00 5.000000e+00 +58 1.000000e+02 5.000000e+00 5.000000e+00 5.000000e+00 + + * /home/fossee/esim-workspace/fulladder/fulladder.cir + Transient Analysis Thu Mar 3 21:20:17 2016 +-------------------------------------------------------------------------------- +Index time in2 sum +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-02 0.000000e+00 0.000000e+00 +2 2.000000e-02 0.000000e+00 0.000000e+00 +3 4.000000e-02 0.000000e+00 0.000000e+00 +4 8.000000e-02 0.000000e+00 0.000000e+00 +5 1.600000e-01 0.000000e+00 0.000000e+00 +6 3.200000e-01 0.000000e+00 0.000000e+00 +7 6.400000e-01 0.000000e+00 0.000000e+00 +8 1.280000e+00 0.000000e+00 0.000000e+00 +9 2.560000e+00 0.000000e+00 0.000000e+00 +10 4.560000e+00 0.000000e+00 0.000000e+00 +11 6.560000e+00 0.000000e+00 0.000000e+00 +12 8.560000e+00 0.000000e+00 0.000000e+00 +13 1.056000e+01 0.000000e+00 0.000000e+00 +14 1.256000e+01 0.000000e+00 0.000000e+00 +15 1.456000e+01 0.000000e+00 0.000000e+00 +16 1.656000e+01 0.000000e+00 0.000000e+00 +17 1.856000e+01 0.000000e+00 0.000000e+00 +18 2.056000e+01 0.000000e+00 0.000000e+00 +19 2.256000e+01 0.000000e+00 0.000000e+00 +20 2.456000e+01 0.000000e+00 0.000000e+00 +21 2.656000e+01 0.000000e+00 0.000000e+00 +22 2.856000e+01 0.000000e+00 0.000000e+00 +23 3.056000e+01 0.000000e+00 0.000000e+00 +24 3.256000e+01 0.000000e+00 0.000000e+00 +25 3.456000e+01 0.000000e+00 0.000000e+00 +26 3.656000e+01 0.000000e+00 0.000000e+00 +27 3.856000e+01 0.000000e+00 0.000000e+00 +28 4.056000e+01 0.000000e+00 0.000000e+00 +29 4.256000e+01 0.000000e+00 0.000000e+00 +30 4.456000e+01 0.000000e+00 0.000000e+00 +31 4.656000e+01 0.000000e+00 0.000000e+00 +32 4.856000e+01 0.000000e+00 0.000000e+00 +33 5.056000e+01 0.000000e+00 0.000000e+00 +34 5.256000e+01 0.000000e+00 0.000000e+00 +35 5.456000e+01 0.000000e+00 0.000000e+00 +36 5.656000e+01 0.000000e+00 0.000000e+00 +37 5.856000e+01 0.000000e+00 0.000000e+00 +38 6.056000e+01 0.000000e+00 0.000000e+00 +39 6.256000e+01 0.000000e+00 0.000000e+00 +40 6.456000e+01 0.000000e+00 0.000000e+00 +41 6.656000e+01 0.000000e+00 0.000000e+00 +42 6.856000e+01 0.000000e+00 0.000000e+00 +43 7.056000e+01 0.000000e+00 0.000000e+00 +44 7.256000e+01 0.000000e+00 0.000000e+00 +45 7.456000e+01 0.000000e+00 0.000000e+00 +46 7.656000e+01 0.000000e+00 0.000000e+00 +47 7.856000e+01 0.000000e+00 0.000000e+00 +48 8.056000e+01 0.000000e+00 0.000000e+00 +49 8.256000e+01 0.000000e+00 0.000000e+00 +50 8.456000e+01 0.000000e+00 0.000000e+00 +51 8.656000e+01 0.000000e+00 0.000000e+00 +52 8.856000e+01 0.000000e+00 0.000000e+00 +53 9.056000e+01 0.000000e+00 0.000000e+00 +54 9.256000e+01 0.000000e+00 0.000000e+00 + +Index time in2 sum +-------------------------------------------------------------------------------- +55 9.456000e+01 0.000000e+00 0.000000e+00 +56 9.656000e+01 0.000000e+00 0.000000e+00 +57 9.856000e+01 0.000000e+00 0.000000e+00 +58 1.000000e+02 0.000000e+00 0.000000e+00 |