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Diffstat (limited to 'Examples/FullAdder/FullAdder.cir.out')
| -rw-r--r-- | Examples/FullAdder/FullAdder.cir.out | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/Examples/FullAdder/FullAdder.cir.out b/Examples/FullAdder/FullAdder.cir.out new file mode 100644 index 00000000..89cd256c --- /dev/null +++ b/Examples/FullAdder/FullAdder.cir.out @@ -0,0 +1,36 @@ +* /home/fossee/esim-workspace/fulladder/fulladder.cir + +.include full_adder.sub +x1 net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ net-_u7-pad1_ net-_u7-pad2_ full_adder +v1 in1 gnd dc 5 +v2 in2 gnd dc 0 +v3 cin gnd dc 5 +r1 sum gnd 1k +r2 cout gnd 1k +* u2 in1 plot_v1 +* u1 in2 plot_v1 +* u3 cin plot_v1 +* u4 sum plot_v1 +* u5 cout plot_v1 +* u6 in1 in2 cin net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ adc_bridge_3 +* u7 net-_u7-pad1_ net-_u7-pad2_ sum cout dac_bridge_2 +a1 [in1 in2 cin ] [net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ ] u6 +a2 [net-_u7-pad1_ net-_u7-pad2_ ] [sum cout ] u7 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u6 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u7 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-00 100e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(in1) +plot v(in2) +plot v(cin) +plot v(sum) +plot v(cout) +.endc +.end |