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| author | saurabhb17 | 2020-03-11 15:02:18 +0530 |
|---|---|---|
| committer | GitHub | 2020-03-11 15:02:18 +0530 |
| commit | 113b43f1cdf83b64ab7faf3fc9cea0181740ad50 (patch) | |
| tree | f1bf080150f8e19788b2dc56eeb10021a44b2c2f /Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD | |
| parent | 6ebbcc31ea0ce5c78c94718e2e46d87592c5d22b (diff) | |
| parent | dc61eab5251234f02c0377ea328b929340b3604c (diff) | |
| download | eSim-113b43f1cdf83b64ab7faf3fc9cea0181740ad50.tar.gz eSim-113b43f1cdf83b64ab7faf3fc9cea0181740ad50.tar.bz2 eSim-113b43f1cdf83b64ab7faf3fc9cea0181740ad50.zip | |
Merge pull request #134 from saurabhb17/master
cleanup part2
Diffstat (limited to 'Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD')
| -rw-r--r-- | Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
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