Merge pull request #134 from saurabhb17/master

cleanup part2

18 files changed, 1061 insertions, 0 deletions

diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~HEAD
index 0a3ccf7f..0a3ccf7f 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3
new file mode 100644
index 00000000..af058641
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~HEAD
index e3c96645..e3c96645 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3
new file mode 100644
index 00000000..d7cf79a0
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD
index 15f8954d..15f8954d 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3
new file mode 100644
index 00000000..ba296cf0
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~HEAD
index 0fdf4d25..0fdf4d25 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3
new file mode 100644
index 00000000..2c9ac554
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3
@@ -0,0 +1,58 @@
+update=03/26/19 18:40:23
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_Subckt
+LibName25=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~HEAD
index c853bf49..c853bf49 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3
new file mode 100644
index 00000000..86be0215
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3
@@ -0,0 +1,121 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD
index b949ae4f..b949ae4f 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~fellowship2019-python3
new file mode 100644
index 00000000..3d9120bb
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~fellowship2019-python3
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~HEAD
index abc5faaa..abc5faaa 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3
new file mode 100644
index 00000000..abc5faaa
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib
index 725472f5..9fb7bb13 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 EESchema-LIBRARY Version 2.3

 #encoding utf-8

 #

@@ -120,3 +121,127 @@ ENDDRAW
 ENDDEF

 #

 #End Library

+=======
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4023
+#
+DEF 4023 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "4023" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X A1 1 -500 300 200 R 50 50 1 1 I
+X B1 2 -500 200 200 R 50 50 1 1 I
+X A2 3 -500 100 200 R 50 50 1 1 I
+X B2 4 -500 0 200 R 50 50 1 1 I
+X C2 5 -500 -100 200 R 50 50 1 1 I
+X Q2 6 -500 -200 200 R 50 50 1 1 O
+X Vss 7 -500 -300 200 R 50 50 1 1 I
+X C1 8 500 -300 200 L 50 50 1 1 I
+X Q1 9 500 -200 200 L 50 50 1 1 O
+X Q3 10 500 -100 200 L 50 50 1 1 O
+X C3 11 500 0 200 L 50 50 1 1 I
+X B3 12 500 100 200 L 50 50 1 1 I
+X A3 13 500 200 200 L 50 50 1 1 I
+X Vdd 14 500 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DC-RESCUE-4023_test
+#
+DEF DC-RESCUE-4023_test v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC-RESCUE-4023_test" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_3
+#
+DEF adc_bridge_3 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_3" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -200 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X OUT1 4 550 50 200 L 50 50 1 1 O
+X OUT2 5 550 -50 200 L 50 50 1 1 O
+X OUT3 6 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_3
+#
+DEF dac_bridge_3 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_3" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -200 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X OUT1 4 550 50 200 L 50 50 1 1 O
+X OUT2 5 550 -50 200 L 50 50 1 1 O
+X OUT3 6 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
+>>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-rescue.lib b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-rescue.lib
new file mode 100644
index 00000000..63440d3e
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-rescue.lib
@@ -0,0 +1,21 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC-RESCUE-4023_test
+#
+DEF DC-RESCUE-4023_test v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC-RESCUE-4023_test" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro
index e4c3c722..ec355936 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 update=06/01/19 15:31:12

 version=1

 last_client=eeschema

@@ -43,3 +44,50 @@ LibName9=eSim_PSpice
 LibName10=eSim_Sources

 LibName11=eSim_Subckt

 LibName12=eSim_User

+=======
+update=Wed Mar 11 12:47:38 2020
+version=1
+last_client=eeschema
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+BoardNm=
+[pcbnew]
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+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
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+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
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+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4023_test-rescue
+LibName2=power
+LibName3=eSim_Analog
+LibName4=eSim_Devices
+LibName5=eSim_Digital
+LibName6=eSim_Hybrid
+LibName7=eSim_Miscellaneous
+LibName8=eSim_Plot
+LibName9=eSim_Power
+LibName10=eSim_User
+LibName11=eSim_Sources
+LibName12=eSim_Subckt
+>>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch
index 37e50cf7..b1661fee 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 EESchema Schematic File Version 2

 LIBS:power

 LIBS:eSim_Analog

@@ -573,3 +574,581 @@ Wire Wire Line
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 Connection ~ 3050 5000

 $EndSCHEMATC

+=======
+EESchema Schematic File Version 2
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