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| author | saurabhb17 | 2020-03-18 20:22:53 +0530 |
|---|---|---|
| committer | GitHub | 2020-03-18 20:22:53 +0530 |
| commit | d3395f5bd22cdd99c7bfa41e5efaf3abf9690bf0 (patch) | |
| tree | affe4c16134e0ca17f6678707a602e06970beade /Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir | |
| parent | d536a4002d05233971a08bbae1907ed9e24e3000 (diff) | |
| parent | 7d7964e7c677244e0fd9fd048a116f62553016ce (diff) | |
| download | eSim-d3395f5bd22cdd99c7bfa41e5efaf3abf9690bf0.tar.gz eSim-d3395f5bd22cdd99c7bfa41e5efaf3abf9690bf0.tar.bz2 eSim-d3395f5bd22cdd99c7bfa41e5efaf3abf9690bf0.zip | |
Merge pull request #140 from saurabhb17/master
Changes in .pro across Examples and Subcircuits
Diffstat (limited to 'Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir')
| -rw-r--r-- | Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
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