Merge pull request #140 from saurabhb17/master

Changes in .pro across Examples and Subcircuits

17 files changed, 4 insertions, 1043 deletions

diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib
index 0a3ccf7f..0a3ccf7f 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~HEAD
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3
deleted file mode 100644
index af058641..00000000
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3
+++ /dev/null
@@ -1,61 +0,0 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir
index 15f8954d..15f8954d 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out
index e3c96645..e3c96645 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~HEAD
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3
deleted file mode 100644
index d7cf79a0..00000000
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3
+++ /dev/null
@@ -1,20 +0,0 @@
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements 
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3
deleted file mode 100644
index ba296cf0..00000000
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3
+++ /dev/null
@@ -1,13 +0,0 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
-U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
-U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
-
-.end
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro
index 0fdf4d25..0fdf4d25 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~HEAD
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3
deleted file mode 100644
index 2c9ac554..00000000
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3
+++ /dev/null
@@ -1,58 +0,0 @@
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-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
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-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=texas
-LibName3=intel
-LibName4=audio
-LibName5=interface
-LibName6=digital-audio
-LibName7=philips
-LibName8=display
-LibName9=cypress
-LibName10=siliconi
-LibName11=opto
-LibName12=atmel
-LibName13=contrib
-LibName14=valves
-LibName15=eSim_Analog
-LibName16=eSim_Devices
-LibName17=eSim_Digital
-LibName18=eSim_Hybrid
-LibName19=eSim_Miscellaneous
-LibName20=eSim_Plot
-LibName21=eSim_Power
-LibName22=eSim_PSpice
-LibName23=eSim_Sources
-LibName24=eSim_Subckt
-LibName25=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch
index c853bf49..c853bf49 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~HEAD
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3
deleted file mode 100644
index 86be0215..00000000
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3
+++ /dev/null
@@ -1,121 +0,0 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
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-LIBS:cypress
-LIBS:siliconi
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-LIBS:atmel
-LIBS:contrib
-LIBS:valves
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-LIBS:eSim_Devices
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-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
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-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L d_and U2
-U 1 1 5C9A24D8
-P 4250 2700
-F 0 "U2" H 4250 2700 60  0000 C CNN
-F 1 "d_and" H 4300 2800 60  0000 C CNN
-F 2 "" H 4250 2700 60  0000 C CNN
-F 3 "" H 4250 2700 60  0000 C CNN
-	1    4250 2700
-	1    0    0    -1  
-$EndComp
-$Comp
-L d_and U3
-U 1 1 5C9A2538
-P 5150 2900
-F 0 "U3" H 5150 2900 60  0000 C CNN
-F 1 "d_and" H 5200 3000 60  0000 C CNN
-F 2 "" H 5150 2900 60  0000 C CNN
-F 3 "" H 5150 2900 60  0000 C CNN
-	1    5150 2900
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 1 1 5C9A259A
-P 3050 2600
-F 0 "U1" H 3100 2700 30  0000 C CNN
-F 1 "PORT" H 3050 2600 30  0000 C CNN
-F 2 "" H 3050 2600 60  0000 C CNN
-F 3 "" H 3050 2600 60  0000 C CNN
-	1    3050 2600
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 2 1 5C9A25D9
-P 3050 2800
-F 0 "U1" H 3100 2900 30  0000 C CNN
-F 1 "PORT" H 3050 2800 30  0000 C CNN
-F 2 "" H 3050 2800 60  0000 C CNN
-F 3 "" H 3050 2800 60  0000 C CNN
-	2    3050 2800
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9A260A
-P 3050 3100
-F 0 "U1" H 3100 3200 30  0000 C CNN
-F 1 "PORT" H 3050 3100 30  0000 C CNN
-F 2 "" H 3050 3100 60  0000 C CNN
-F 3 "" H 3050 3100 60  0000 C CNN
-	3    3050 3100
-	1    0    0    -1  
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9A2637
-P 6900 2850
-F 0 "U1" H 6950 2950 30  0000 C CNN
-F 1 "PORT" H 6900 2850 30  0000 C CNN
-F 2 "" H 6900 2850 60  0000 C CNN
-F 3 "" H 6900 2850 60  0000 C CNN
-	4    6900 2850
-	-1   0    0    1   
-$EndComp
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
-	3300 3100 4700 3100
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-$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub
index b949ae4f..b949ae4f 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~fellowship2019-python3
deleted file mode 100644
index 3d9120bb..00000000
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~fellowship2019-python3
+++ /dev/null
@@ -1,14 +0,0 @@
-* Subcircuit 3_and
-.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
-* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
-* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
-* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 3_and
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml
index abc5faaa..abc5faaa 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~HEAD
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3
deleted file mode 100644
index abc5faaa..00000000
--- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3
+++ /dev/null
@@ -1 +0,0 @@
-<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib
index 9fb7bb13..4ef5b7f4 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib
@@ -1,127 +1,3 @@
-<<<<<<< HEAD
-EESchema-LIBRARY Version 2.3

-#encoding utf-8

-#

-# 4023

-#

-DEF 4023 X 0 40 Y Y 1 F N

-F0 "X" 0 -100 60 H V C CNN

-F1 "4023" 0 100 60 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-S -300 450 300 -450 0 1 0 N

-X A1 1 -500 300 200 R 50 50 1 1 I

-X B1 2 -500 200 200 R 50 50 1 1 I

-X A2 3 -500 100 200 R 50 50 1 1 I

-X B2 4 -500 0 200 R 50 50 1 1 I

-X C2 5 -500 -100 200 R 50 50 1 1 I

-X Q2 6 -500 -200 200 R 50 50 1 1 O

-X Vss 7 -500 -300 200 R 50 50 1 1 I

-X C1 8 500 -300 200 L 50 50 1 1 I

-X Q1 9 500 -200 200 L 50 50 1 1 O

-X Q3 10 500 -100 200 L 50 50 1 1 O

-X C3 11 500 0 200 L 50 50 1 1 I

-X B3 12 500 100 200 L 50 50 1 1 I

-X A3 13 500 200 200 L 50 50 1 1 I

-X Vdd 14 500 300 200 L 50 50 1 1 I

-ENDDRAW

-ENDDEF

-#

-# DC

-#

-DEF DC v 0 40 Y Y 1 F N

-F0 "v" -200 100 60 H V C CNN

-F1 "DC" -200 -50 60 H V C CNN

-F2 "R1" -300 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-$FPLIST

- 1_pin

-$ENDFPLIST

-DRAW

-C 0 0 150 0 1 0 N

-X + 1 0 450 300 D 50 50 1 1 P

-X - 2 0 -450 300 U 50 50 1 1 P

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-#

-# PWR_FLAG

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-DEF PWR_FLAG #FLG 0 0 N N 1 F P

-F0 "#FLG" 0 95 50 H I C CNN

-F1 "PWR_FLAG" 0 180 50 H V C CNN

-F2 "" 0 0 50 H V C CNN

-F3 "" 0 0 50 H V C CNN

-DRAW

-X pwr 1 0 0 0 U 20 20 0 0 w

-P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N

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-#

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-#

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-F0 "U" 0 0 60 H V C CNN

-F1 "adc_bridge_3" 0 150 60 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-S -400 200 350 -200 0 1 0 N

-X IN1 1 -600 50 200 R 50 50 1 1 I

-X IN2 2 -600 -50 200 R 50 50 1 1 I

-X IN3 3 -600 -150 200 R 50 50 1 1 I

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-X OUT3 6 550 -150 200 L 50 50 1 1 O

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-DEF dac_bridge_3 U 0 40 Y Y 1 F N

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-F1 "dac_bridge_3" 0 150 60 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-S -400 200 350 -200 0 1 0 N

-X IN1 1 -600 50 200 R 50 50 1 1 I

-X IN2 2 -600 -50 200 R 50 50 1 1 I

-X IN3 3 -600 -150 200 R 50 50 1 1 I

-X OUT1 4 550 50 200 L 50 50 1 1 O

-X OUT2 5 550 -50 200 L 50 50 1 1 O

-X OUT3 6 550 -150 200 L 50 50 1 1 O

-ENDDRAW

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-#

-# eSim_GND

-#

-DEF eSim_GND #PWR 0 0 Y Y 1 F P

-F0 "#PWR" 0 -250 50 H I C CNN

-F1 "eSim_GND" 0 -150 50 H V C CNN

-F2 "" 0 0 50 H I C CNN

-F3 "" 0 0 50 H I C CNN

-DRAW

-P 6 0 1 0  0 0  0 -50  50 -50  0 -100  -50 -50  0 -50 N

-X GND 1 0 0 0 D 50 50 1 1 W N

-ENDDRAW

-ENDDEF

-#

-# plot_v1

-#

-DEF plot_v1 U 0 40 Y Y 1 F N

-F0 "U" 0 500 60 H V C CNN

-F1 "plot_v1" 200 350 60 H V C CNN

-F2 "" 0 0 60 H V C CNN

-F3 "" 0 0 60 H V C CNN

-DRAW

-C 0 500 100 0 1 0 N

-X ~ ~ 0 200 200 U 50 50 1 1 I

-ENDDRAW

-ENDDEF

-#

-#End Library

-=======
 EESchema-LIBRARY Version 2.3
 #encoding utf-8
 #
@@ -244,4 +120,3 @@ ENDDRAW
 ENDDEF
 #
 #End Library
->>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro
index ec355936..d2059e07 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro
@@ -1,51 +1,4 @@
-<<<<<<< HEAD
-update=06/01/19 15:31:12

-version=1

-last_client=eeschema

-[general]

-version=1

-RootSch=

-BoardNm=

-[pcbnew]

-version=1

-LastNetListRead=

-UseCmpFile=1

-PadDrill=0.600000000000

-PadDrillOvalY=0.600000000000

-PadSizeH=1.500000000000

-PadSizeV=1.500000000000

-PcbTextSizeV=1.500000000000

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-PcbTextThickness=0.300000000000

-ModuleTextSizeV=1.000000000000

-ModuleTextSizeH=1.000000000000

-ModuleTextSizeThickness=0.150000000000

-SolderMaskClearance=0.000000000000

-SolderMaskMinWidth=0.000000000000

-DrawSegmentWidth=0.200000000000

-BoardOutlineThickness=0.100000000000

-ModuleOutlineThickness=0.150000000000

-[cvpcb]

-version=1

-NetIExt=net

-[eeschema]

-version=1

-LibDir=../../eSim/kicadSchematicLibrary

-[eeschema/libraries]

-LibName1=power

-LibName2=eSim_Analog

-LibName3=eSim_Devices

-LibName4=eSim_Digital

-LibName5=eSim_Hybrid

-LibName6=eSim_Miscellaneous

-LibName7=eSim_Plot

-LibName8=eSim_Power

-LibName9=eSim_PSpice

-LibName10=eSim_Sources

-LibName11=eSim_Subckt

-LibName12=eSim_User

-=======
-update=Wed Mar 11 12:47:38 2020
+update=Wed Mar 18 18:18:44 2020
 version=1
 last_client=eeschema
 [general]
@@ -87,7 +40,6 @@ LibName6=eSim_Hybrid
 LibName7=eSim_Miscellaneous
 LibName8=eSim_Plot
 LibName9=eSim_Power
-LibName10=eSim_User
-LibName11=eSim_Sources
-LibName12=eSim_Subckt
->>>>>>> fellowship2019-python3
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch
index b1661fee..1052029e 100644
--- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch
+++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch
@@ -1,580 +1,3 @@
-<<<<<<< HEAD
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-LIBS:eSim_PSpice

-LIBS:eSim_Sources

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-=======
 EESchema Schematic File Version 2
 LIBS:4023_test-rescue
 LIBS:power
@@ -1151,4 +574,3 @@ Wire Wire Line
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 Connection ~ 3050 5000
 $EndSCHEMATC
->>>>>>> fellowship2019-python3