SN54147 is a priority encoder

23 files changed, 2785 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and-cache.lib b/library/SubcircuitLibrary/SN54147_sub/3_and-cache.lib
new file mode 100644
index 00000000..af058641
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.cir b/library/SubcircuitLibrary/SN54147_sub/3_and.cir
new file mode 100644
index 00000000..ba296cf0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.cir.out b/library/SubcircuitLibrary/SN54147_sub/3_and.cir.out
new file mode 100644
index 00000000..d7cf79a0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.pro b/library/SubcircuitLibrary/SN54147_sub/3_and.pro
new file mode 100644
index 00000000..da3e199e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 20:00:16 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.sch b/library/SubcircuitLibrary/SN54147_sub/3_and.sch
new file mode 100644
index 00000000..d6ac89f9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+Text Notes 3500 2600 0    60   ~ 12
+in1
+Text Notes 3450 2800 0    60   ~ 12
+in2\n
+Text Notes 3500 3100 0    60   ~ 12
+in3
+Text Notes 6100 2850 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.sub b/library/SubcircuitLibrary/SN54147_sub/3_and.sub
new file mode 100644
index 00000000..3d9120bb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54147_sub/3_and_Previous_Values.xml
new file mode 100644
index 00000000..abc5faaa
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and-cache.lib b/library/SubcircuitLibrary/SN54147_sub/5_and-cache.lib
new file mode 100644
index 00000000..fc177c1f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and-rescue.lib b/library/SubcircuitLibrary/SN54147_sub/5_and-rescue.lib
new file mode 100644
index 00000000..483b8efb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/5_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.cir b/library/SubcircuitLibrary/SN54147_sub/5_and.cir
new file mode 100644
index 00000000..6a05b9b5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and		
+U2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and		
+U3  Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.cir.out b/library/SubcircuitLibrary/SN54147_sub/5_and.cir.out
new file mode 100644
index 00000000..6a6b126a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.pro b/library/SubcircuitLibrary/SN54147_sub/5_and.pro
new file mode 100644
index 00000000..c16a3f85
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/5_and.pro
@@ -0,0 +1,49 @@
+update=Wed Mar 18 19:59:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_User
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.sch b/library/SubcircuitLibrary/SN54147_sub/5_and.sch
new file mode 100644
index 00000000..aef3c043
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2
+LIBS:5_and-rescue
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_User
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-5_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60  0000 C CNN
+F 1 "3_and" H 4750 3850 60  0000 C CNN
+F 2 "" H 3800 3350 60  0000 C CNN
+F 3 "" H 3800 3350 60  0000 C CNN
+	1    3800 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60  0000 C CNN
+F 1 "d_and" H 4700 3500 60  0000 C CNN
+F 2 "" H 4650 3400 60  0000 C CNN
+F 3 "" H 4650 3400 60  0000 C CNN
+	1    4650 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60  0000 C CNN
+F 1 "d_and" H 5600 3300 60  0000 C CNN
+F 2 "" H 5550 3200 60  0000 C CNN
+F 3 "" H 5550 3200 60  0000 C CNN
+	1    5550 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5100 3100 5100 2950
+Wire Wire Line
+	5100 3200 5100 3350
+Wire Wire Line
+	4250 2850 4250 2700
+Wire Wire Line
+	4250 2700 3600 2700
+Wire Wire Line
+	4250 2950 4150 2950
+Wire Wire Line
+	4150 2950 4150 2900
+Wire Wire Line
+	4150 2900 3600 2900
+Wire Wire Line
+	4200 3300 3600 3300
+Wire Wire Line
+	4250 3050 4250 3100
+Wire Wire Line
+	4250 3100 3600 3100
+Wire Wire Line
+	4200 3400 4200 3500
+Wire Wire Line
+	4200 3500 3600 3500
+Wire Wire Line
+	6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30  0000 C CNN
+F 1 "PORT" H 3350 2700 30  0000 C CNN
+F 2 "" H 3350 2700 60  0000 C CNN
+F 3 "" H 3350 2700 60  0000 C CNN
+	1    3350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30  0000 C CNN
+F 1 "PORT" H 3350 2900 30  0000 C CNN
+F 2 "" H 3350 2900 60  0000 C CNN
+F 3 "" H 3350 2900 60  0000 C CNN
+	2    3350 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30  0000 C CNN
+F 1 "PORT" H 3350 3100 30  0000 C CNN
+F 2 "" H 3350 3100 60  0000 C CNN
+F 3 "" H 3350 3100 60  0000 C CNN
+	3    3350 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30  0000 C CNN
+F 1 "PORT" H 3350 3300 30  0000 C CNN
+F 2 "" H 3350 3300 60  0000 C CNN
+F 3 "" H 3350 3300 60  0000 C CNN
+	4    3350 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30  0000 C CNN
+F 1 "PORT" H 3350 3500 30  0000 C CNN
+F 2 "" H 3350 3500 60  0000 C CNN
+F 3 "" H 3350 3500 60  0000 C CNN
+	5    3350 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30  0000 C CNN
+F 1 "PORT" H 6750 3150 30  0000 C CNN
+F 2 "" H 6750 3150 60  0000 C CNN
+F 3 "" H 6750 3150 60  0000 C CNN
+	6    6750 3150
+	-1   0    0    1   
+$EndComp
+Text Notes 3800 2700 0    60   ~ 12
+in1
+Text Notes 3800 2900 0    60   ~ 12
+in2
+Text Notes 3800 3100 0    60   ~ 12
+in3
+Text Notes 3800 3300 0    60   ~ 12
+in4
+Text Notes 3800 3500 0    60   ~ 12
+in5
+Text Notes 6150 3150 0    60   ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.sub b/library/SubcircuitLibrary/SN54147_sub/5_and.sub
new file mode 100644
index 00000000..35b10e17
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2  net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3  net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54147_sub/5_and_Previous_Values.xml
new file mode 100644
index 00000000..ae2c08a7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC-cache.lib b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC-cache.lib
new file mode 100644
index 00000000..45b9ccde
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC-cache.lib
@@ -0,0 +1,189 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 5_and
+#
+DEF 5_and X 0 40 Y Y 1 F N
+F0 "X" 50 -100 60 H V C CNN
+F1 "5_and" 100 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
+P 2 0 1 0 -250 250 150 250 N
+P 3 0 1 0 -250 250 -250 -250 150 -250 N
+X in1 1 -450 200 200 R 50 50 1 1 I
+X in2 2 -450 100 200 R 50 50 1 1 I
+X in3 3 -450 0 200 R 50 50 1 1 I
+X in4 4 -450 -100 200 R 50 50 1 1 I
+X in5 5 -450 -200 200 R 50 50 1 1 I
+X out 6 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_4
+#
+DEF dac_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir
new file mode 100644
index 00000000..772cd6bf
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir
@@ -0,0 +1,64 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN54147_IC\SN54147_IC.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/22/24 18:32:08
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter		
+U28  Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U28-Pad3_ d_and		
+U29  Net-_U15-Pad2_ Net-_U17-Pad3_ Net-_U29-Pad3_ d_and		
+U35  Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U35-Pad3_ d_and		
+U30  Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U30-Pad3_ d_and		
+U36  Net-_U30-Pad3_ Net-_U17-Pad3_ Net-_U36-Pad3_ d_and		
+U31  Net-_U23-Pad1_ Net-_U17-Pad3_ Net-_U31-Pad3_ d_and		
+U18  Net-_U10-Pad2_ Net-_U13-Pad2_ Net-_U18-Pad3_ d_and		
+U19  Net-_U14-Pad2_ Net-_U17-Pad3_ Net-_U19-Pad3_ d_and		
+U33  Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U33-Pad3_ d_and		
+U20  Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U20-Pad3_ d_and		
+U21  Net-_U14-Pad2_ Net-_U17-Pad3_ Net-_U21-Pad3_ d_and		
+U34  Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U34-Pad3_ d_and		
+U22  Net-_U15-Pad1_ Net-_U17-Pad3_ Net-_U22-Pad3_ d_and		
+U23  Net-_U23-Pad1_ Net-_U17-Pad3_ Net-_U23-Pad3_ d_and		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter		
+U7  Net-_U2-Pad11_ Net-_U13-Pad1_ d_inverter		
+U16  Net-_U10-Pad2_ Net-_U16-Pad2_ d_inverter		
+U13  Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter		
+U24  Net-_U13-Pad1_ Net-_U17-Pad3_ Net-_U24-Pad3_ d_and		
+U25  Net-_U14-Pad1_ Net-_U17-Pad3_ Net-_U25-Pad3_ d_and		
+U26  Net-_U15-Pad1_ Net-_U17-Pad3_ Net-_U26-Pad3_ d_and		
+U27  Net-_U23-Pad1_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and		
+U12  Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter		
+U8  Net-_U2-Pad12_ Net-_U14-Pad1_ d_inverter		
+U14  Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter		
+U9  Net-_U2-Pad13_ Net-_U15-Pad1_ d_inverter		
+U15  Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter		
+U6  Net-_U2-Pad14_ Net-_U23-Pad1_ d_inverter		
+U4  Net-_U2-Pad15_ Net-_U17-Pad1_ d_inverter		
+U5  Net-_U2-Pad16_ Net-_U17-Pad2_ d_inverter		
+U17  Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_nor		
+X1  Net-_U11-Pad2_ Net-_U16-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U17-Pad3_ Net-_U42-Pad1_ 5_and		
+U32  Net-_U17-Pad2_ Net-_U17-Pad2_ Net-_U32-Pad3_ d_and		
+U37  Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U37-Pad3_ d_nor		
+U3  Net-_U1-Pad10_ Net-_U11-Pad1_ adc_bridge_1		
+U2  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad9_ Net-_U10-Pad1_ Net-_U12-Pad1_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ adc_bridge_8		
+U53  Net-_U52-Pad3_ Net-_U51-Pad3_ Net-_U46-Pad3_ Net-_U37-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad13_ dac_bridge_4		
+U42  Net-_U42-Pad1_ Net-_U35-Pad3_ Net-_U42-Pad3_ d_nor		
+U49  Net-_U42-Pad3_ Net-_U36-Pad3_ Net-_U49-Pad3_ d_nor		
+U43  Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U43-Pad3_ d_nor		
+U52  Net-_U49-Pad3_ Net-_U50-Pad3_ Net-_U52-Pad3_ d_nor		
+U40  Net-_U33-Pad3_ Net-_U34-Pad3_ Net-_U40-Pad3_ d_nor		
+U47  Net-_U40-Pad3_ Net-_U40-Pad3_ Net-_U47-Pad3_ d_nor		
+U41  Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U41-Pad3_ d_nor		
+U48  Net-_U41-Pad3_ Net-_U41-Pad3_ Net-_U48-Pad3_ d_nor		
+U51  Net-_U47-Pad3_ Net-_U48-Pad3_ Net-_U51-Pad3_ d_nor		
+U38  Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U38-Pad3_ d_nor		
+U39  Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U39-Pad3_ d_nor		
+U44  Net-_U38-Pad3_ Net-_U38-Pad3_ Net-_U44-Pad3_ d_nor		
+U45  Net-_U39-Pad3_ Net-_U39-Pad3_ Net-_U45-Pad3_ d_nor		
+U46  Net-_U44-Pad3_ Net-_U45-Pad3_ Net-_U46-Pad3_ d_nor		
+U50  Net-_U43-Pad3_ Net-_U43-Pad3_ Net-_U50-Pad3_ d_nor		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir.out b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir.out
new file mode 100644
index 00000000..eedd9eba
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir.out
@@ -0,0 +1,222 @@
+* d:\fossee\esim\library\subcircuitlibrary\sn54147_ic\sn54147_ic.cir
+
+.include 5_and.sub
+* u11  net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u28  net-_u12-pad2_ net-_u13-pad2_ net-_u28-pad3_ d_and
+* u29  net-_u15-pad2_ net-_u17-pad3_ net-_u29-pad3_ d_and
+* u35  net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_and
+* u30  net-_u14-pad1_ net-_u15-pad2_ net-_u30-pad3_ d_and
+* u36  net-_u30-pad3_ net-_u17-pad3_ net-_u36-pad3_ d_and
+* u31  net-_u23-pad1_ net-_u17-pad3_ net-_u31-pad3_ d_and
+* u18  net-_u10-pad2_ net-_u13-pad2_ net-_u18-pad3_ d_and
+* u19  net-_u14-pad2_ net-_u17-pad3_ net-_u19-pad3_ d_and
+* u33  net-_u18-pad3_ net-_u19-pad3_ net-_u33-pad3_ d_and
+* u20  net-_u12-pad2_ net-_u13-pad2_ net-_u20-pad3_ d_and
+* u21  net-_u14-pad2_ net-_u17-pad3_ net-_u21-pad3_ d_and
+* u34  net-_u20-pad3_ net-_u21-pad3_ net-_u34-pad3_ d_and
+* u22  net-_u15-pad1_ net-_u17-pad3_ net-_u22-pad3_ d_and
+* u23  net-_u23-pad1_ net-_u17-pad3_ net-_u23-pad3_ d_and
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u7  net-_u2-pad11_ net-_u13-pad1_ d_inverter
+* u16  net-_u10-pad2_ net-_u16-pad2_ d_inverter
+* u13  net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u24  net-_u13-pad1_ net-_u17-pad3_ net-_u24-pad3_ d_and
+* u25  net-_u14-pad1_ net-_u17-pad3_ net-_u25-pad3_ d_and
+* u26  net-_u15-pad1_ net-_u17-pad3_ net-_u26-pad3_ d_and
+* u27  net-_u23-pad1_ net-_u17-pad3_ net-_u27-pad3_ d_and
+* u12  net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u8  net-_u2-pad12_ net-_u14-pad1_ d_inverter
+* u14  net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u9  net-_u2-pad13_ net-_u15-pad1_ d_inverter
+* u15  net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u6  net-_u2-pad14_ net-_u23-pad1_ d_inverter
+* u4  net-_u2-pad15_ net-_u17-pad1_ d_inverter
+* u5  net-_u2-pad16_ net-_u17-pad2_ d_inverter
+* u17  net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nor
+x1 net-_u11-pad2_ net-_u16-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u17-pad3_ net-_u42-pad1_ 5_and
+* u32  net-_u17-pad2_ net-_u17-pad2_ net-_u32-pad3_ d_and
+* u37  net-_u17-pad1_ net-_u17-pad2_ net-_u37-pad3_ d_nor
+* u3  net-_u1-pad10_ net-_u11-pad1_ adc_bridge_1
+* u2  net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8
+* u53  net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ dac_bridge_4
+* u42  net-_u42-pad1_ net-_u35-pad3_ net-_u42-pad3_ d_nor
+* u49  net-_u42-pad3_ net-_u36-pad3_ net-_u49-pad3_ d_nor
+* u43  net-_u31-pad3_ net-_u32-pad3_ net-_u43-pad3_ d_nor
+* u52  net-_u49-pad3_ net-_u50-pad3_ net-_u52-pad3_ d_nor
+* u40  net-_u33-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor
+* u47  net-_u40-pad3_ net-_u40-pad3_ net-_u47-pad3_ d_nor
+* u41  net-_u22-pad3_ net-_u23-pad3_ net-_u41-pad3_ d_nor
+* u48  net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nor
+* u51  net-_u47-pad3_ net-_u48-pad3_ net-_u51-pad3_ d_nor
+* u38  net-_u24-pad3_ net-_u25-pad3_ net-_u38-pad3_ d_nor
+* u39  net-_u26-pad3_ net-_u27-pad3_ net-_u39-pad3_ d_nor
+* u44  net-_u38-pad3_ net-_u38-pad3_ net-_u44-pad3_ d_nor
+* u45  net-_u39-pad3_ net-_u39-pad3_ net-_u45-pad3_ d_nor
+* u46  net-_u44-pad3_ net-_u45-pad3_ net-_u46-pad3_ d_nor
+* u50  net-_u43-pad3_ net-_u43-pad3_ net-_u50-pad3_ d_nor
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port
+a1 net-_u11-pad1_ net-_u11-pad2_ u11
+a2 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u28-pad3_ u28
+a3 [net-_u15-pad2_ net-_u17-pad3_ ] net-_u29-pad3_ u29
+a4 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35
+a5 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u30-pad3_ u30
+a6 [net-_u30-pad3_ net-_u17-pad3_ ] net-_u36-pad3_ u36
+a7 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u31-pad3_ u31
+a8 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u18-pad3_ u18
+a9 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u19-pad3_ u19
+a10 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u33-pad3_ u33
+a11 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u20-pad3_ u20
+a12 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u21-pad3_ u21
+a13 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u34-pad3_ u34
+a14 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u22-pad3_ u22
+a15 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u23-pad3_ u23
+a16 net-_u10-pad1_ net-_u10-pad2_ u10
+a17 net-_u2-pad11_ net-_u13-pad1_ u7
+a18 net-_u10-pad2_ net-_u16-pad2_ u16
+a19 net-_u13-pad1_ net-_u13-pad2_ u13
+a20 [net-_u13-pad1_ net-_u17-pad3_ ] net-_u24-pad3_ u24
+a21 [net-_u14-pad1_ net-_u17-pad3_ ] net-_u25-pad3_ u25
+a22 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u26-pad3_ u26
+a23 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u27-pad3_ u27
+a24 net-_u12-pad1_ net-_u12-pad2_ u12
+a25 net-_u2-pad12_ net-_u14-pad1_ u8
+a26 net-_u14-pad1_ net-_u14-pad2_ u14
+a27 net-_u2-pad13_ net-_u15-pad1_ u9
+a28 net-_u15-pad1_ net-_u15-pad2_ u15
+a29 net-_u2-pad14_ net-_u23-pad1_ u6
+a30 net-_u2-pad15_ net-_u17-pad1_ u4
+a31 net-_u2-pad16_ net-_u17-pad2_ u5
+a32 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a33 [net-_u17-pad2_ net-_u17-pad2_ ] net-_u32-pad3_ u32
+a34 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u37-pad3_ u37
+a35 [net-_u1-pad10_ ] [net-_u11-pad1_ ] u3
+a36 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ ] [net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2
+a37 [net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ ] [net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ ] u53
+a38 [net-_u42-pad1_ net-_u35-pad3_ ] net-_u42-pad3_ u42
+a39 [net-_u42-pad3_ net-_u36-pad3_ ] net-_u49-pad3_ u49
+a40 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u43-pad3_ u43
+a41 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u52-pad3_ u52
+a42 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40
+a43 [net-_u40-pad3_ net-_u40-pad3_ ] net-_u47-pad3_ u47
+a44 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u41-pad3_ u41
+a45 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48
+a46 [net-_u47-pad3_ net-_u48-pad3_ ] net-_u51-pad3_ u51
+a47 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u38-pad3_ u38
+a48 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u39-pad3_ u39
+a49 [net-_u38-pad3_ net-_u38-pad3_ ] net-_u44-pad3_ u44
+a50 [net-_u39-pad3_ net-_u39-pad3_ ] net-_u45-pad3_ u45
+a51 [net-_u44-pad3_ net-_u45-pad3_ ] net-_u46-pad3_ u46
+a52 [net-_u43-pad3_ net-_u43-pad3_ ] net-_u50-pad3_ u50
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_8, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
+.model u53 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u42 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u49 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u52 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u41 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u48 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u51 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.pro b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sch b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sch
new file mode 100644
index 00000000..d1d0e0ff
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sch
@@ -0,0 +1,1363 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN54147-cache
+EELAYER 25 0
+EELAYER END
+$Descr User 27559 23622
+encoding utf-8
+Sheet 1 1
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+Date ""
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+Connection ~ 13750 14650
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+F 0 "U3" H 8500 4800 60  0000 C CNN
+F 1 "adc_bridge_1" H 8500 4950 60  0000 C CNN
+F 2 "" H 8500 4800 60  0000 C CNN
+F 3 "" H 8500 4800 60  0000 C CNN
+	1    8500 4800
+	1    0    0    -1  
+$EndComp
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+F 2 "" H 7100 9600 60  0000 C CNN
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+	1    7100 9600
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+$EndComp
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+F 2 "" H 5000 12950 50  0001 C CNN
+F 3 "" H 5000 12950 50  0001 C CNN
+	1    5000 12950
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+$EndComp
+$Comp
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+F 2 "" H 20150 10200 60  0000 C CNN
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+Wire Wire Line
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+Wire Wire Line
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+F 1 "d_nor" H 17350 5700 60  0000 C CNN
+F 2 "" H 17300 5600 60  0000 C CNN
+F 3 "" H 17300 5600 60  0000 C CNN
+	1    17300 5600
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U49
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+F 0 "U49" H 18350 5650 60  0000 C CNN
+F 1 "d_nor" H 18400 5750 60  0000 C CNN
+F 2 "" H 18350 5650 60  0000 C CNN
+F 3 "" H 18350 5650 60  0000 C CNN
+	1    18350 5650
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U43
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+F 0 "U43" H 17300 6400 60  0000 C CNN
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+F 2 "" H 17300 6400 60  0000 C CNN
+F 3 "" H 17300 6400 60  0000 C CNN
+	1    17300 6400
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U52
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+F 0 "U52" H 19500 5900 60  0000 C CNN
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+F 2 "" H 19500 5900 60  0000 C CNN
+F 3 "" H 19500 5900 60  0000 C CNN
+	1    19500 5900
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+$EndComp
+$Comp
+L d_nor U40
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+F 1 "d_nor" H 17300 9150 60  0000 C CNN
+F 2 "" H 17250 9050 60  0000 C CNN
+F 3 "" H 17250 9050 60  0000 C CNN
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+$EndComp
+$Comp
+L d_nor U47
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+P 18300 9050
+F 0 "U47" H 18300 9050 60  0000 C CNN
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+F 2 "" H 18300 9050 60  0000 C CNN
+F 3 "" H 18300 9050 60  0000 C CNN
+	1    18300 9050
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+$EndComp
+$Comp
+L d_nor U41
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+P 17250 9850
+F 0 "U41" H 17250 9850 60  0000 C CNN
+F 1 "d_nor" H 17300 9950 60  0000 C CNN
+F 2 "" H 17250 9850 60  0000 C CNN
+F 3 "" H 17250 9850 60  0000 C CNN
+	1    17250 9850
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+$EndComp
+$Comp
+L d_nor U48
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+P 18300 9850
+F 0 "U48" H 18300 9850 60  0000 C CNN
+F 1 "d_nor" H 18350 9950 60  0000 C CNN
+F 2 "" H 18300 9850 60  0000 C CNN
+F 3 "" H 18300 9850 60  0000 C CNN
+	1    18300 9850
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+$EndComp
+$Comp
+L d_nor U51
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+F 0 "U51" H 18850 9400 60  0000 C CNN
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+F 2 "" H 18850 9400 60  0000 C CNN
+F 3 "" H 18850 9400 60  0000 C CNN
+	1    18850 9400
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+$EndComp
+$Comp
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+F 2 "" H 16200 12700 60  0000 C CNN
+F 3 "" H 16200 12700 60  0000 C CNN
+	1    16200 12700
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+$EndComp
+$Comp
+L d_nor U39
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+F 2 "" H 16200 13500 60  0000 C CNN
+F 3 "" H 16200 13500 60  0000 C CNN
+	1    16200 13500
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+$EndComp
+$Comp
+L d_nor U44
+U 1 1 6676CB99
+P 17350 12700
+F 0 "U44" H 17350 12700 60  0000 C CNN
+F 1 "d_nor" H 17400 12800 60  0000 C CNN
+F 2 "" H 17350 12700 60  0000 C CNN
+F 3 "" H 17350 12700 60  0000 C CNN
+	1    17350 12700
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+$EndComp
+$Comp
+L d_nor U45
+U 1 1 6676CB9A
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+F 0 "U45" H 17350 13550 60  0000 C CNN
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+F 2 "" H 17350 13550 60  0000 C CNN
+F 3 "" H 17350 13550 60  0000 C CNN
+	1    17350 13550
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U46
+U 1 1 6676CB9B
+P 18000 13100
+F 0 "U46" H 18000 13100 60  0000 C CNN
+F 1 "d_nor" H 18050 13200 60  0000 C CNN
+F 2 "" H 18000 13100 60  0000 C CNN
+F 3 "" H 18000 13100 60  0000 C CNN
+	1    18000 13100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U50
+U 1 1 6676CB9C
+P 18350 6400
+F 0 "U50" H 18350 6400 60  0000 C CNN
+F 1 "d_nor" H 18400 6500 60  0000 C CNN
+F 2 "" H 18350 6400 60  0000 C CNN
+F 3 "" H 18350 6400 60  0000 C CNN
+	1    18350 6400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	17850 6300 17850 6400
+Wire Wire Line
+	17850 6400 17900 6400
+Wire Wire Line
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+Connection ~ 17850 6350
+Wire Wire Line
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+$Comp
+L PORT U1
+U 2 1 6676CB9D
+P 5700 9900
+F 0 "U1" H 5750 10000 30  0000 C CNN
+F 1 "PORT" H 5700 9900 30  0000 C CNN
+F 2 "" H 5700 9900 60  0000 C CNN
+F 3 "" H 5700 9900 60  0000 C CNN
+	2    5700 9900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
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+P 5500 10050
+F 0 "U1" H 5550 10150 30  0000 C CNN
+F 1 "PORT" H 5500 10050 30  0000 C CNN
+F 2 "" H 5500 10050 60  0000 C CNN
+F 3 "" H 5500 10050 60  0000 C CNN
+	3    5500 10050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6676CB9F
+P 5700 10200
+F 0 "U1" H 5750 10300 30  0000 C CNN
+F 1 "PORT" H 5700 10200 30  0000 C CNN
+F 2 "" H 5700 10200 60  0000 C CNN
+F 3 "" H 5700 10200 60  0000 C CNN
+	4    5700 10200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6676CBA0
+P 5550 9750
+F 0 "U1" H 5600 9850 30  0000 C CNN
+F 1 "PORT" H 5550 9750 30  0000 C CNN
+F 2 "" H 5550 9750 60  0000 C CNN
+F 3 "" H 5550 9750 60  0000 C CNN
+	1    5550 9750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+$Comp
+L PORT U1
+U 5 1 6676CBA1
+P 5700 10400
+F 0 "U1" H 5750 10500 30  0000 C CNN
+F 1 "PORT" H 5700 10400 30  0000 C CNN
+F 2 "" H 5700 10400 60  0000 C CNN
+F 3 "" H 5700 10400 60  0000 C CNN
+	5    5700 10400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+L PORT U1
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+F 1 "PORT" H 21250 10200 30  0000 C CNN
+F 2 "" H 21250 10200 60  0000 C CNN
+F 3 "" H 21250 10200 60  0000 C CNN
+	6    21250 10200
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
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+$Comp
+L PORT U1
+U 7 1 6676CBA3
+P 21250 10000
+F 0 "U1" H 21300 10100 30  0000 C CNN
+F 1 "PORT" H 21250 10000 30  0000 C CNN
+F 2 "" H 21250 10000 60  0000 C CNN
+F 3 "" H 21250 10000 60  0000 C CNN
+	7    21250 10000
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
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+$Comp
+L PORT U1
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+F 0 "U1" H 21300 9900 30  0000 C CNN
+F 1 "PORT" H 21250 9800 30  0000 C CNN
+F 2 "" H 21250 9800 60  0000 C CNN
+F 3 "" H 21250 9800 60  0000 C CNN
+	8    21250 9800
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+$Comp
+L PORT U1
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+P 5700 10600
+F 0 "U1" H 5750 10700 30  0000 C CNN
+F 1 "PORT" H 5700 10600 30  0000 C CNN
+F 2 "" H 5700 10600 60  0000 C CNN
+F 3 "" H 5700 10600 60  0000 C CNN
+	9    5700 10600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	6400 10250 6400 10600
+Wire Wire Line
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+$Comp
+L PORT U1
+U 10 1 6676CBA6
+P 7350 4750
+F 0 "U1" H 7400 4850 30  0000 C CNN
+F 1 "PORT" H 7350 4750 30  0000 C CNN
+F 2 "" H 7350 4750 60  0000 C CNN
+F 3 "" H 7350 4750 60  0000 C CNN
+	10   7350 4750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+$Comp
+L PORT U1
+U 11 1 6676CBA7
+P 5700 9350
+F 0 "U1" H 5750 9450 30  0000 C CNN
+F 1 "PORT" H 5700 9350 30  0000 C CNN
+F 2 "" H 5700 9350 60  0000 C CNN
+F 3 "" H 5700 9350 60  0000 C CNN
+	11   5700 9350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6676CBA8
+P 5700 9550
+F 0 "U1" H 5750 9650 30  0000 C CNN
+F 1 "PORT" H 5700 9550 30  0000 C CNN
+F 2 "" H 5700 9550 60  0000 C CNN
+F 3 "" H 5700 9550 60  0000 C CNN
+	12   5700 9550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	5950 9550 6300 9550
+Wire Wire Line
+	6300 9550 6300 9650
+Wire Wire Line
+	6300 9650 6500 9650
+$Comp
+L PORT U1
+U 13 1 6676CBA9
+P 21250 10450
+F 0 "U1" H 21300 10550 30  0000 C CNN
+F 1 "PORT" H 21250 10450 30  0000 C CNN
+F 2 "" H 21250 10450 60  0000 C CNN
+F 3 "" H 21250 10450 60  0000 C CNN
+	13   21250 10450
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	20900 10300 20900 10450
+Wire Wire Line
+	20900 10450 21000 10450
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sub b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sub
new file mode 100644
index 00000000..f16660b7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sub
@@ -0,0 +1,216 @@
+* Subcircuit SN54147_IC
+.subckt SN54147_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ 
+* d:\fossee\esim\library\subcircuitlibrary\sn54147_ic\sn54147_ic.cir
+.include 5_and.sub
+* u11  net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u28  net-_u12-pad2_ net-_u13-pad2_ net-_u28-pad3_ d_and
+* u29  net-_u15-pad2_ net-_u17-pad3_ net-_u29-pad3_ d_and
+* u35  net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_and
+* u30  net-_u14-pad1_ net-_u15-pad2_ net-_u30-pad3_ d_and
+* u36  net-_u30-pad3_ net-_u17-pad3_ net-_u36-pad3_ d_and
+* u31  net-_u23-pad1_ net-_u17-pad3_ net-_u31-pad3_ d_and
+* u18  net-_u10-pad2_ net-_u13-pad2_ net-_u18-pad3_ d_and
+* u19  net-_u14-pad2_ net-_u17-pad3_ net-_u19-pad3_ d_and
+* u33  net-_u18-pad3_ net-_u19-pad3_ net-_u33-pad3_ d_and
+* u20  net-_u12-pad2_ net-_u13-pad2_ net-_u20-pad3_ d_and
+* u21  net-_u14-pad2_ net-_u17-pad3_ net-_u21-pad3_ d_and
+* u34  net-_u20-pad3_ net-_u21-pad3_ net-_u34-pad3_ d_and
+* u22  net-_u15-pad1_ net-_u17-pad3_ net-_u22-pad3_ d_and
+* u23  net-_u23-pad1_ net-_u17-pad3_ net-_u23-pad3_ d_and
+* u10  net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u7  net-_u2-pad11_ net-_u13-pad1_ d_inverter
+* u16  net-_u10-pad2_ net-_u16-pad2_ d_inverter
+* u13  net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u24  net-_u13-pad1_ net-_u17-pad3_ net-_u24-pad3_ d_and
+* u25  net-_u14-pad1_ net-_u17-pad3_ net-_u25-pad3_ d_and
+* u26  net-_u15-pad1_ net-_u17-pad3_ net-_u26-pad3_ d_and
+* u27  net-_u23-pad1_ net-_u17-pad3_ net-_u27-pad3_ d_and
+* u12  net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u8  net-_u2-pad12_ net-_u14-pad1_ d_inverter
+* u14  net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u9  net-_u2-pad13_ net-_u15-pad1_ d_inverter
+* u15  net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u6  net-_u2-pad14_ net-_u23-pad1_ d_inverter
+* u4  net-_u2-pad15_ net-_u17-pad1_ d_inverter
+* u5  net-_u2-pad16_ net-_u17-pad2_ d_inverter
+* u17  net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nor
+x1 net-_u11-pad2_ net-_u16-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u17-pad3_ net-_u42-pad1_ 5_and
+* u32  net-_u17-pad2_ net-_u17-pad2_ net-_u32-pad3_ d_and
+* u37  net-_u17-pad1_ net-_u17-pad2_ net-_u37-pad3_ d_nor
+* u3  net-_u1-pad10_ net-_u11-pad1_ adc_bridge_1
+* u2  net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8
+* u53  net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ dac_bridge_4
+* u42  net-_u42-pad1_ net-_u35-pad3_ net-_u42-pad3_ d_nor
+* u49  net-_u42-pad3_ net-_u36-pad3_ net-_u49-pad3_ d_nor
+* u43  net-_u31-pad3_ net-_u32-pad3_ net-_u43-pad3_ d_nor
+* u52  net-_u49-pad3_ net-_u50-pad3_ net-_u52-pad3_ d_nor
+* u40  net-_u33-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor
+* u47  net-_u40-pad3_ net-_u40-pad3_ net-_u47-pad3_ d_nor
+* u41  net-_u22-pad3_ net-_u23-pad3_ net-_u41-pad3_ d_nor
+* u48  net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nor
+* u51  net-_u47-pad3_ net-_u48-pad3_ net-_u51-pad3_ d_nor
+* u38  net-_u24-pad3_ net-_u25-pad3_ net-_u38-pad3_ d_nor
+* u39  net-_u26-pad3_ net-_u27-pad3_ net-_u39-pad3_ d_nor
+* u44  net-_u38-pad3_ net-_u38-pad3_ net-_u44-pad3_ d_nor
+* u45  net-_u39-pad3_ net-_u39-pad3_ net-_u45-pad3_ d_nor
+* u46  net-_u44-pad3_ net-_u45-pad3_ net-_u46-pad3_ d_nor
+* u50  net-_u43-pad3_ net-_u43-pad3_ net-_u50-pad3_ d_nor
+a1 net-_u11-pad1_ net-_u11-pad2_ u11
+a2 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u28-pad3_ u28
+a3 [net-_u15-pad2_ net-_u17-pad3_ ] net-_u29-pad3_ u29
+a4 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35
+a5 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u30-pad3_ u30
+a6 [net-_u30-pad3_ net-_u17-pad3_ ] net-_u36-pad3_ u36
+a7 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u31-pad3_ u31
+a8 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u18-pad3_ u18
+a9 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u19-pad3_ u19
+a10 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u33-pad3_ u33
+a11 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u20-pad3_ u20
+a12 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u21-pad3_ u21
+a13 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u34-pad3_ u34
+a14 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u22-pad3_ u22
+a15 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u23-pad3_ u23
+a16 net-_u10-pad1_ net-_u10-pad2_ u10
+a17 net-_u2-pad11_ net-_u13-pad1_ u7
+a18 net-_u10-pad2_ net-_u16-pad2_ u16
+a19 net-_u13-pad1_ net-_u13-pad2_ u13
+a20 [net-_u13-pad1_ net-_u17-pad3_ ] net-_u24-pad3_ u24
+a21 [net-_u14-pad1_ net-_u17-pad3_ ] net-_u25-pad3_ u25
+a22 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u26-pad3_ u26
+a23 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u27-pad3_ u27
+a24 net-_u12-pad1_ net-_u12-pad2_ u12
+a25 net-_u2-pad12_ net-_u14-pad1_ u8
+a26 net-_u14-pad1_ net-_u14-pad2_ u14
+a27 net-_u2-pad13_ net-_u15-pad1_ u9
+a28 net-_u15-pad1_ net-_u15-pad2_ u15
+a29 net-_u2-pad14_ net-_u23-pad1_ u6
+a30 net-_u2-pad15_ net-_u17-pad1_ u4
+a31 net-_u2-pad16_ net-_u17-pad2_ u5
+a32 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a33 [net-_u17-pad2_ net-_u17-pad2_ ] net-_u32-pad3_ u32
+a34 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u37-pad3_ u37
+a35 [net-_u1-pad10_ ] [net-_u11-pad1_ ] u3
+a36 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ ] [net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2
+a37 [net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ ] [net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ ] u53
+a38 [net-_u42-pad1_ net-_u35-pad3_ ] net-_u42-pad3_ u42
+a39 [net-_u42-pad3_ net-_u36-pad3_ ] net-_u49-pad3_ u49
+a40 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u43-pad3_ u43
+a41 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u52-pad3_ u52
+a42 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40
+a43 [net-_u40-pad3_ net-_u40-pad3_ ] net-_u47-pad3_ u47
+a44 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u41-pad3_ u41
+a45 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48
+a46 [net-_u47-pad3_ net-_u48-pad3_ ] net-_u51-pad3_ u51
+a47 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u38-pad3_ u38
+a48 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u39-pad3_ u39
+a49 [net-_u38-pad3_ net-_u38-pad3_ ] net-_u44-pad3_ u44
+a50 [net-_u39-pad3_ net-_u39-pad3_ ] net-_u45-pad3_ u45
+a51 [net-_u44-pad3_ net-_u45-pad3_ ] net-_u46-pad3_ u46
+a52 [net-_u43-pad3_ net-_u43-pad3_ ] net-_u50-pad3_ u50
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             adc_bridge_8, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
+.model u53 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u42 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u49 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u52 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u41 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u48 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u51 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN54147_IC
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC_Previous_Values.xml b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC_Previous_Values.xml
new file mode 100644
index 00000000..ecb2c383
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u11 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u11><u28 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u29><u35 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u35><u30 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u30><u36 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u36><u31 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u31><u18 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u19><u33 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u33><u20 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u21><u34 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u34><u22 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u23><u10 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u10><u7 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u7><u16 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u16><u13 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u13><u24 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u26><u27 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u27><u12 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u12><u8 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u8><u14 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u14><u9 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u9><u15 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u15><u6 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u6><u4 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u5><u17 name="type">d_nor<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u17><u32 name="type">d_and<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u32><u37 name="type">d_nor<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u37><u3 name="type">adc_bridge<field103 name="Enter value for in_low (default=1.0)" /><field104 name="Enter value for in_high (default=2.0)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /><field106 name="Enter Fall Delay (default=1.0e-9)" /></u3><u2 name="type">adc_bridge<field107 name="Enter value for in_low (default=1.0)" /><field108 name="Enter value for in_high (default=2.0)" /><field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /></u2><u53 name="type">dac_bridge<field111 name="Enter value for out_low (default=0.0)" /><field112 name="Enter value for out_high (default=5.0)" /><field113 name="Enter value for out_undef (default=0.5)" /><field114 name="Enter value for input load (default=1.0e-12)" /><field115 name="Enter the Rise Time (default=1.0e-9)" /><field116 name="Enter the Fall Time (default=1.0e-9)" /></u53><u42 name="type">d_nor<field117 name="Enter Rise Delay (default=1.0e-9)" /><field118 name="Enter Fall Delay (default=1.0e-9)" /><field119 name="Enter Input Load (default=1.0e-12)" /></u42><u49 name="type">d_nor<field120 name="Enter Rise Delay (default=1.0e-9)" /><field121 name="Enter Fall Delay (default=1.0e-9)" /><field122 name="Enter Input Load (default=1.0e-12)" /></u49><u43 name="type">d_nor<field123 name="Enter Rise Delay (default=1.0e-9)" /><field124 name="Enter Fall Delay (default=1.0e-9)" /><field125 name="Enter Input Load (default=1.0e-12)" /></u43><u52 name="type">d_nor<field126 name="Enter Rise Delay (default=1.0e-9)" /><field127 name="Enter Fall Delay (default=1.0e-9)" /><field128 name="Enter Input Load (default=1.0e-12)" /></u52><u40 name="type">d_nor<field129 name="Enter Rise Delay (default=1.0e-9)" /><field130 name="Enter Fall Delay (default=1.0e-9)" /><field131 name="Enter Input Load (default=1.0e-12)" /></u40><u47 name="type">d_nor<field132 name="Enter Rise Delay (default=1.0e-9)" /><field133 name="Enter Fall Delay (default=1.0e-9)" /><field134 name="Enter Input Load (default=1.0e-12)" /></u47><u41 name="type">d_nor<field135 name="Enter Rise Delay (default=1.0e-9)" /><field136 name="Enter Fall Delay (default=1.0e-9)" /><field137 name="Enter Input Load (default=1.0e-12)" /></u41><u48 name="type">d_nor<field138 name="Enter Rise Delay (default=1.0e-9)" /><field139 name="Enter Fall Delay (default=1.0e-9)" /><field140 name="Enter Input Load (default=1.0e-12)" /></u48><u51 name="type">d_nor<field141 name="Enter Rise Delay (default=1.0e-9)" /><field142 name="Enter Fall Delay (default=1.0e-9)" /><field143 name="Enter Input Load (default=1.0e-12)" /></u51><u38 name="type">d_nor<field144 name="Enter Rise Delay (default=1.0e-9)" /><field145 name="Enter Fall Delay (default=1.0e-9)" /><field146 name="Enter Input Load (default=1.0e-12)" /></u38><u39 name="type">d_nor<field147 name="Enter Rise Delay (default=1.0e-9)" /><field148 name="Enter Fall Delay (default=1.0e-9)" /><field149 name="Enter Input Load (default=1.0e-12)" /></u39><u44 name="type">d_nor<field150 name="Enter Rise Delay (default=1.0e-9)" /><field151 name="Enter Fall Delay (default=1.0e-9)" /><field152 name="Enter Input Load (default=1.0e-12)" /></u44><u45 name="type">d_nor<field153 name="Enter Rise Delay (default=1.0e-9)" /><field154 name="Enter Fall Delay (default=1.0e-9)" /><field155 name="Enter Input Load (default=1.0e-12)" /></u45><u46 name="type">d_nor<field156 name="Enter Rise Delay (default=1.0e-9)" /><field157 name="Enter Fall Delay (default=1.0e-9)" /><field158 name="Enter Input Load (default=1.0e-12)" /></u46><u50 name="type">d_nor<field159 name="Enter Rise Delay (default=1.0e-9)" /><field160 name="Enter Fall Delay (default=1.0e-9)" /><field161 name="Enter Input Load (default=1.0e-12)" /></u50></model><devicemodel /><subcircuit><x1><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54147_sub/analysis b/library/SubcircuitLibrary/SN54147_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54147_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file