diff options
Diffstat (limited to 'digital ciruits/and gate')
| -rw-r--r-- | digital ciruits/and gate/and gate-cache.lib | 68 | ||||
| -rw-r--r-- | digital ciruits/and gate/and gate.bak | 208 | ||||
| -rw-r--r-- | digital ciruits/and gate/and gate.cir | 10 | ||||
| -rw-r--r-- | digital ciruits/and gate/and gate.kicad_pcb | 1 | ||||
| -rw-r--r-- | digital ciruits/and gate/and gate.pro | 33 | ||||
| -rw-r--r-- | digital ciruits/and gate/and gate.sch | 212 | ||||
| -rw-r--r-- | digital ciruits/and gate/sym-lib-table | 4 |
7 files changed, 536 insertions, 0 deletions
diff --git a/digital ciruits/and gate/and gate-cache.lib b/digital ciruits/and gate/and gate-cache.lib new file mode 100644 index 0000000..28aadfe --- /dev/null +++ b/digital ciruits/and gate/and gate-cache.lib @@ -0,0 +1,68 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND +# +DEF sim_logic:CMOS_NAND X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/digital ciruits/and gate/and gate.bak b/digital ciruits/and gate/and gate.bak new file mode 100644 index 0000000..7a004bd --- /dev/null +++ b/digital ciruits/and gate/and gate.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B28B068 +P 4150 3850 +F 0 "X1" H 4350 3578 50 0000 C CNN +F 1 "CMOS_NAND" H 4350 3487 50 0000 C CNN +F 2 "" H 4150 3850 50 0001 C CNN +F 3 "" H 4150 3850 50 0001 C CNN +F 4 "X" H 4150 3850 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4150 3850 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4150 3850 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 4150 3850 50 0001 C CNN "Spice_Lib_File" + 1 4150 3850 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X2 +U 1 1 5B28B0D0 +P 5900 3850 +F 0 "X2" H 6100 3578 50 0000 C CNN +F 1 "CMOS_NAND" H 6100 3487 50 0000 C CNN +F 2 "" H 5900 3850 50 0001 C CNN +F 3 "" H 5900 3850 50 0001 C CNN + 1 5900 3850 + 1 0 0 -1 +$EndComp +Text GLabel 2850 3750 0 50 Input ~ 0 +1 +Wire Wire Line + 2850 3750 3950 3750 +Text GLabel 2850 3950 0 50 Input ~ 0 +2 +Wire Wire Line + 2850 3950 3950 3950 +Text GLabel 7250 3150 0 50 Output ~ 0 +3 +$Comp +L Device:R R1 +U 1 1 5B28B182 +P 7650 3850 +F 0 "R1" V 7443 3850 50 0000 C CNN +F 1 "10meg" V 7534 3850 50 0000 C CNN +F 2 "" V 7580 3850 50 0001 C CNN +F 3 "~" H 7650 3850 50 0001 C CNN + 1 7650 3850 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B28B214 +P 8150 4050 +F 0 "#PWR04" H 8150 3800 50 0001 C CNN +F 1 "GND" H 8155 3877 50 0000 C CNN +F 2 "" H 8150 4050 50 0001 C CNN +F 3 "" H 8150 4050 50 0001 C CNN + 1 8150 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8150 4050 8150 3850 +Wire Wire Line + 8150 3850 7800 3850 +Wire Wire Line + 7500 3850 7350 3850 +Wire Wire Line + 7250 3150 7350 3150 +Wire Wire Line + 7350 3150 7350 3850 +Connection ~ 7350 3850 +Wire Wire Line + 7350 3850 6500 3850 +Wire Wire Line + 4750 3850 4750 3750 +Wire Wire Line + 4750 3750 5700 3750 +Wire Wire Line + 4750 3850 4750 3950 +Wire Wire Line + 4750 3950 5700 3950 +Connection ~ 4750 3850 +Text GLabel 3850 2900 0 50 Input ~ 0 +4 +Wire Wire Line + 3850 2900 4350 2900 +Wire Wire Line + 6100 2900 6100 3450 +Wire Wire Line + 4350 3450 4350 2900 +Connection ~ 4350 2900 +Wire Wire Line + 4350 2900 6100 2900 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B28B632 +P 1800 3400 +F 0 "V1" H 2028 3446 50 0000 L CNN +F 1 "VSOURCE" H 2028 3355 50 0000 L CNN +F 2 "" H 1800 3400 50 0001 C CNN +F 3 "" H 1800 3400 50 0001 C CNN +F 4 "V" H 1800 3400 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1800 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1800 3400 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1800 3400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR01 +U 1 1 5B28B678 +P 1800 3950 +F 0 "#PWR01" H 1800 3700 50 0001 C CNN +F 1 "GND" H 1805 3777 50 0000 C CNN +F 2 "" H 1800 3950 50 0001 C CNN +F 3 "" H 1800 3950 50 0001 C CNN + 1 1800 3950 + 1 0 0 -1 +$EndComp +Text GLabel 1700 2750 0 50 Input ~ 0 +1 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B28B69D +P 2050 5600 +F 0 "V2" H 2278 5646 50 0000 L CNN +F 1 "VSOURCE" H 2278 5555 50 0000 L CNN +F 2 "" H 2050 5600 50 0001 C CNN +F 3 "" H 2050 5600 50 0001 C CNN +F 4 "V" H 2050 5600 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 50m 0 0 50m 100m)" H 2050 5600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2050 5600 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2050 5600 + 1 0 0 -1 +$EndComp +Text GLabel 1900 4950 0 50 Input ~ 0 +2 +$Comp +L power:GND #PWR02 +U 1 1 5B28B717 +P 2050 6100 +F 0 "#PWR02" H 2050 5850 50 0001 C CNN +F 1 "GND" H 2055 5927 50 0000 C CNN +F 2 "" H 2050 6100 50 0001 C CNN +F 3 "" H 2050 6100 50 0001 C CNN + 1 2050 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 6100 2050 5900 +Wire Wire Line + 2050 5300 2050 4950 +Wire Wire Line + 2050 4950 1900 4950 +Wire Wire Line + 1800 3100 1800 2750 +Wire Wire Line + 1800 2750 1700 2750 +Wire Wire Line + 1800 3950 1800 3700 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B28BEA7 +P 7600 5550 +F 0 "V3" H 7828 5596 50 0000 L CNN +F 1 "VSOURCE" H 7828 5505 50 0000 L CNN +F 2 "" H 7600 5550 50 0001 C CNN +F 3 "" H 7600 5550 50 0001 C CNN +F 4 "V" H 7600 5550 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 7600 5550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7600 5550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7600 5550 + 1 0 0 -1 +$EndComp +Text GLabel 7050 4800 0 50 Input ~ 0 +4 +Wire Wire Line + 7050 4800 7600 4800 +Wire Wire Line + 7600 4800 7600 5250 +$Comp +L power:GND #PWR03 +U 1 1 5B28C1DA +P 7600 6000 +F 0 "#PWR03" H 7600 5750 50 0001 C CNN +F 1 "GND" H 7605 5827 50 0000 C CNN +F 2 "" H 7600 6000 50 0001 C CNN +F 3 "" H 7600 6000 50 0001 C CNN + 1 7600 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7600 6000 7600 5850 +Text Notes 8750 5600 0 50 ~ 0 +.tran 1m 400m +$EndSCHEMATC diff --git a/digital ciruits/and gate/and gate.cir b/digital ciruits/and gate/and gate.cir new file mode 100644 index 0000000..c69b756 --- /dev/null +++ b/digital ciruits/and gate/and gate.cir @@ -0,0 +1,10 @@ +.title KiCad schematic +.include "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" +X1 1 2 Net-_X1-PadOut_ 4 NAND +X2 Net-_X1-PadOut_ Net-_X1-PadOut_ 3 4 NAND +R1 GND 3 10meg +V1 1 GND dc 0 pulse(0 3.3 0 0 0 100m 200m) +V2 2 GND dc 0 pulse(0 3.3 50m 0 0 50m 100m) +V3 4 GND dc 3.3 +.tran 1m 400m +.end diff --git a/digital ciruits/and gate/and gate.kicad_pcb b/digital ciruits/and gate/and gate.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/digital ciruits/and gate/and gate.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/digital ciruits/and gate/and gate.pro b/digital ciruits/and gate/and gate.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/digital ciruits/and gate/and gate.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/digital ciruits/and gate/and gate.sch b/digital ciruits/and gate/and gate.sch new file mode 100644 index 0000000..912ac63 --- /dev/null +++ b/digital ciruits/and gate/and gate.sch @@ -0,0 +1,212 @@ +EESchema Schematic File Version 4 +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L sim_logic:CMOS_NAND X1 +U 1 1 5B28B068 +P 4150 3850 +F 0 "X1" H 4350 3578 50 0000 C CNN +F 1 "CMOS_NAND" H 4350 3487 50 0000 C CNN +F 2 "" H 4150 3850 50 0001 C CNN +F 3 "" H 4150 3850 50 0001 C CNN +F 4 "X" H 4150 3850 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 4150 3850 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4150 3850 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 4150 3850 50 0001 C CNN "Spice_Lib_File" + 1 4150 3850 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X2 +U 1 1 5B28B0D0 +P 5900 3850 +F 0 "X2" H 6100 3578 50 0000 C CNN +F 1 "CMOS_NAND" H 6100 3487 50 0000 C CNN +F 2 "" H 5900 3850 50 0001 C CNN +F 3 "" H 5900 3850 50 0001 C CNN +F 4 "X" H 5900 3850 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5900 3850 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5900 3850 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5900 3850 50 0001 C CNN "Spice_Lib_File" + 1 5900 3850 + 1 0 0 -1 +$EndComp +Text GLabel 2850 3750 0 50 Input ~ 0 +1 +Wire Wire Line + 2850 3750 3950 3750 +Text GLabel 2850 3950 0 50 Input ~ 0 +2 +Wire Wire Line + 2850 3950 3950 3950 +Text GLabel 7250 3150 0 50 Output ~ 0 +3 +$Comp +L Device:R R1 +U 1 1 5B28B182 +P 7650 3850 +F 0 "R1" V 7443 3850 50 0000 C CNN +F 1 "10meg" V 7534 3850 50 0000 C CNN +F 2 "" V 7580 3850 50 0001 C CNN +F 3 "~" H 7650 3850 50 0001 C CNN + 1 7650 3850 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR04 +U 1 1 5B28B214 +P 8150 4050 +F 0 "#PWR04" H 8150 3800 50 0001 C CNN +F 1 "GND" H 8155 3877 50 0000 C CNN +F 2 "" H 8150 4050 50 0001 C CNN +F 3 "" H 8150 4050 50 0001 C CNN + 1 8150 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8150 4050 8150 3850 +Wire Wire Line + 8150 3850 7800 3850 +Wire Wire Line + 7500 3850 7350 3850 +Wire Wire Line + 7250 3150 7350 3150 +Wire Wire Line + 7350 3150 7350 3850 +Connection ~ 7350 3850 +Wire Wire Line + 7350 3850 6500 3850 +Wire Wire Line + 4750 3850 4750 3750 +Wire Wire Line + 4750 3750 5700 3750 +Wire Wire Line + 4750 3850 4750 3950 +Wire Wire Line + 4750 3950 5700 3950 +Connection ~ 4750 3850 +Text GLabel 3850 2900 0 50 Input ~ 0 +4 +Wire Wire Line + 3850 2900 4350 2900 +Wire Wire Line + 6100 2900 6100 3450 +Wire Wire Line + 4350 3450 4350 2900 +Connection ~ 4350 2900 +Wire Wire Line + 4350 2900 6100 2900 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B28B632 +P 1800 3400 +F 0 "V1" H 2028 3446 50 0000 L CNN +F 1 "VSOURCE" H 2028 3355 50 0000 L CNN +F 2 "" H 1800 3400 50 0001 C CNN +F 3 "" H 1800 3400 50 0001 C CNN +F 4 "V" H 1800 3400 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 0 0 0 100m 200m)" H 1800 3400 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1800 3400 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1800 3400 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR01 +U 1 1 5B28B678 +P 1800 3950 +F 0 "#PWR01" H 1800 3700 50 0001 C CNN +F 1 "GND" H 1805 3777 50 0000 C CNN +F 2 "" H 1800 3950 50 0001 C CNN +F 3 "" H 1800 3950 50 0001 C CNN + 1 1800 3950 + 1 0 0 -1 +$EndComp +Text GLabel 1700 2750 0 50 Input ~ 0 +1 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B28B69D +P 2050 5600 +F 0 "V2" H 2278 5646 50 0000 L CNN +F 1 "VSOURCE" H 2278 5555 50 0000 L CNN +F 2 "" H 2050 5600 50 0001 C CNN +F 3 "" H 2050 5600 50 0001 C CNN +F 4 "V" H 2050 5600 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pulse(0 3.3 50m 0 0 50m 100m)" H 2050 5600 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2050 5600 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2050 5600 + 1 0 0 -1 +$EndComp +Text GLabel 1900 4950 0 50 Input ~ 0 +2 +$Comp +L power:GND #PWR02 +U 1 1 5B28B717 +P 2050 6100 +F 0 "#PWR02" H 2050 5850 50 0001 C CNN +F 1 "GND" H 2055 5927 50 0000 C CNN +F 2 "" H 2050 6100 50 0001 C CNN +F 3 "" H 2050 6100 50 0001 C CNN + 1 2050 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 6100 2050 5900 +Wire Wire Line + 2050 5300 2050 4950 +Wire Wire Line + 2050 4950 1900 4950 +Wire Wire Line + 1800 3100 1800 2750 +Wire Wire Line + 1800 2750 1700 2750 +Wire Wire Line + 1800 3950 1800 3700 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B28BEA7 +P 7600 5550 +F 0 "V3" H 7828 5596 50 0000 L CNN +F 1 "VSOURCE" H 7828 5505 50 0000 L CNN +F 2 "" H 7600 5550 50 0001 C CNN +F 3 "" H 7600 5550 50 0001 C CNN +F 4 "V" H 7600 5550 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 7600 5550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7600 5550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 7600 5550 + 1 0 0 -1 +$EndComp +Text GLabel 7050 4800 0 50 Input ~ 0 +4 +Wire Wire Line + 7050 4800 7600 4800 +Wire Wire Line + 7600 4800 7600 5250 +$Comp +L power:GND #PWR03 +U 1 1 5B28C1DA +P 7600 6000 +F 0 "#PWR03" H 7600 5750 50 0001 C CNN +F 1 "GND" H 7605 5827 50 0000 C CNN +F 2 "" H 7600 6000 50 0001 C CNN +F 3 "" H 7600 6000 50 0001 C CNN + 1 7600 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7600 6000 7600 5850 +Text Notes 8750 5600 0 50 ~ 0 +.tran 1m 400m +$EndSCHEMATC diff --git a/digital ciruits/and gate/sym-lib-table b/digital ciruits/and gate/sym-lib-table new file mode 100644 index 0000000..81cad09 --- /dev/null +++ b/digital ciruits/and gate/sym-lib-table @@ -0,0 +1,4 @@ +(sym_lib_table + (lib (name spice_models)(type Legacy)(uri /home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib)(options "")(descr "")) + (lib (name sim_logic)(type Legacy)(uri /home/akshay/Downloads/kicad-simulation-examples-master/libs/sim_logic.lib)(options "")(descr "")) +) |