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authorAkshay NH2018-06-28 19:22:03 +0530
committerAkshay NH2018-06-28 19:22:03 +0530
commitd1edc2c0c9b8d823892b94482e01451e82c3eec1 (patch)
tree9fb54dfd93a975be8b2a8cb29b21eb5639ac29ef /digital ciruits/nor_sub/nor_sub.sch
downloadeSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.tar.gz
eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.tar.bz2
eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.zip
adding kicad analog and digital circuits
Diffstat (limited to 'digital ciruits/nor_sub/nor_sub.sch')
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diff --git a/digital ciruits/nor_sub/nor_sub.sch b/digital ciruits/nor_sub/nor_sub.sch
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+EESchema Schematic File Version 4
+LIBS:nor_sub-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L pspice:VSOURCE V1
+U 1 1 5B294AD5
+P 3300 3750
+F 0 "V1" H 3528 3796 50 0000 L CNN
+F 1 "VSOURCE" H 3528 3705 50 0000 L CNN
+F 2 "" H 3300 3750 50 0001 C CNN
+F 3 "" H 3300 3750 50 0001 C CNN
+F 4 "V" H 3300 3750 50 0001 C CNN "Spice_Primitive"
+F 5 "pulse(0 3.3 0 0 0 50m 100m)" H 3300 3750 50 0001 C CNN "Spice_Model"
+F 6 "Y" H 3300 3750 50 0001 C CNN "Spice_Netlist_Enabled"
+ 1 3300 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L pspice:VSOURCE V3
+U 1 1 5B294B5F
+P 7750 4350
+F 0 "V3" H 7978 4396 50 0000 L CNN
+F 1 "VSOURCE" H 7978 4305 50 0000 L CNN
+F 2 "" H 7750 4350 50 0001 C CNN
+F 3 "" H 7750 4350 50 0001 C CNN
+F 4 "V" H 7750 4350 50 0001 C CNN "Spice_Primitive"
+F 5 "dc 3.3" H 7750 4350 50 0001 C CNN "Spice_Model"
+F 6 "Y" H 7750 4350 50 0001 C CNN "Spice_Netlist_Enabled"
+ 1 7750 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L pspice:VSOURCE V2
+U 1 1 5B294BE6
+P 4050 4250
+F 0 "V2" H 4278 4296 50 0000 L CNN
+F 1 "VSOURCE" H 4278 4205 50 0000 L CNN
+F 2 "" H 4050 4250 50 0001 C CNN
+F 3 "" H 4050 4250 50 0001 C CNN
+F 4 "V" H 4050 4250 50 0001 C CNN "Spice_Primitive"
+F 5 "pulse(0 3.3 50m 0 0 50m 100m)" H 4050 4250 50 0001 C CNN "Spice_Model"
+F 6 "Y" H 4050 4250 50 0001 C CNN "Spice_Netlist_Enabled"
+ 1 4050 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5B294C95
+P 6600 3650
+F 0 "R1" V 6393 3650 50 0000 C CNN
+F 1 "10meg" V 6484 3650 50 0000 C CNN
+F 2 "" V 6530 3650 50 0001 C CNN
+F 3 "~" H 6600 3650 50 0001 C CNN
+ 1 6600 3650
+ 0 1 1 0
+$EndComp
+$Comp
+L power:GND #PWR0101
+U 1 1 5B294D70
+P 7750 4900
+F 0 "#PWR0101" H 7750 4650 50 0001 C CNN
+F 1 "GND" H 7755 4727 50 0000 C CNN
+F 2 "" H 7750 4900 50 0001 C CNN
+F 3 "" H 7750 4900 50 0001 C CNN
+ 1 7750 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #PWR0102
+U 1 1 5B294D8C
+P 4050 4750
+F 0 "#PWR0102" H 4050 4500 50 0001 C CNN
+F 1 "GND" H 4055 4577 50 0000 C CNN
+F 2 "" H 4050 4750 50 0001 C CNN
+F 3 "" H 4050 4750 50 0001 C CNN
+ 1 4050 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:GND #PWR0103
+U 1 1 5B294DA1
+P 3300 4250
+F 0 "#PWR0103" H 3300 4000 50 0001 C CNN
+F 1 "GND" H 3305 4077 50 0000 C CNN
+F 2 "" H 3300 4250 50 0001 C CNN
+F 3 "" H 3300 4250 50 0001 C CNN
+ 1 3300 4250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3300 3350 4100 3350
+Wire Wire Line
+ 3300 3350 3300 3450
+Wire Wire Line
+ 4050 3950 4050 3650
+Wire Wire Line
+ 4050 3650 4400 3650
+Wire Wire Line
+ 4050 4550 4050 4750
+Wire Wire Line
+ 3300 4050 3300 4250
+$Comp
+L power:GND #PWR0104
+U 1 1 5B294E99
+P 7000 3800
+F 0 "#PWR0104" H 7000 3550 50 0001 C CNN
+F 1 "GND" H 7005 3627 50 0000 C CNN
+F 2 "" H 7000 3800 50 0001 C CNN
+F 3 "" H 7000 3800 50 0001 C CNN
+ 1 7000 3800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6750 3650 7000 3650
+Wire Wire Line
+ 7000 3650 7000 3800
+Wire Wire Line
+ 7750 4650 7750 4900
+Text GLabel 6350 3450 0 50 Output ~ 0
+Out
+Wire Wire Line
+ 6350 3450 6350 3650
+Connection ~ 6350 3650
+Wire Wire Line
+ 6350 3650 6450 3650
+Text GLabel 4000 3000 0 50 Output ~ 0
+a
+Text GLabel 4350 3500 0 50 Output ~ 0
+b
+Wire Wire Line
+ 4350 3500 4400 3500
+Wire Wire Line
+ 4400 3500 4400 3650
+Connection ~ 4400 3650
+Wire Wire Line
+ 4000 3000 4100 3000
+Wire Wire Line
+ 4100 3000 4100 3350
+Connection ~ 4100 3350
+$Comp
+L power:VDD #PWR0105
+U 1 1 5B295DE6
+P 7750 3900
+F 0 "#PWR0105" H 7750 3750 50 0001 C CNN
+F 1 "VDD" H 7767 4073 50 0000 C CNN
+F 2 "" H 7750 3900 50 0001 C CNN
+F 3 "" H 7750 3900 50 0001 C CNN
+ 1 7750 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L power:VDD #PWR0106
+U 1 1 5B295E02
+P 6500 3300
+F 0 "#PWR0106" H 6500 3150 50 0001 C CNN
+F 1 "VDD" H 6517 3473 50 0000 C CNN
+F 2 "" H 6500 3300 50 0001 C CNN
+F 3 "" H 6500 3300 50 0001 C CNN
+ 1 6500 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6500 3350 6500 3300
+Wire Wire Line
+ 7750 3900 7750 4050
+Wire Wire Line
+ 4100 3350 5250 3350
+Wire Wire Line
+ 5250 3650 5250 3500
+Wire Wire Line
+ 5950 3350 6500 3350
+Wire Wire Line
+ 5950 3500 5950 3650
+Wire Wire Line
+ 5950 3650 6350 3650
+Wire Wire Line
+ 4400 3650 5250 3650
+Text Notes 6900 5450 0 50 ~ 0
+.tran .25m 30m
+$Comp
+L sim_logic:NOR X1
+U 1 1 5B332768
+P 5700 3350
+F 0 "X1" H 5600 3591 39 0000 C CNN
+F 1 "NOR" H 5600 3516 39 0000 C CNN
+F 2 "" H 5700 3350 50 0001 C CNN
+F 3 "" H 5700 3350 50 0001 C CNN
+F 4 "X" H 5700 3350 50 0001 C CNN "Spice_Primitive"
+F 5 "NOR" H 5700 3350 50 0001 C CNN "Spice_Model"
+F 6 "Y" H 5700 3350 50 0001 C CNN "Spice_Netlist_Enabled"
+F 7 "/home/akshay/Desktop/digital ciruits/libs/spice_models.lib" H 5700 3350 50 0001 C CNN "Spice_Lib_File"
+ 1 5700 3350
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC