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author | Akshay NH | 2018-06-28 19:22:03 +0530 |
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committer | Akshay NH | 2018-06-28 19:22:03 +0530 |
commit | d1edc2c0c9b8d823892b94482e01451e82c3eec1 (patch) | |
tree | 9fb54dfd93a975be8b2a8cb29b21eb5639ac29ef /digital ciruits/masterslave_jkff/masterslave_jkff.bak | |
download | eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.tar.gz eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.tar.bz2 eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.zip |
adding kicad analog and digital circuits
Diffstat (limited to 'digital ciruits/masterslave_jkff/masterslave_jkff.bak')
-rw-r--r-- | digital ciruits/masterslave_jkff/masterslave_jkff.bak | 564 |
1 files changed, 564 insertions, 0 deletions
diff --git a/digital ciruits/masterslave_jkff/masterslave_jkff.bak b/digital ciruits/masterslave_jkff/masterslave_jkff.bak new file mode 100644 index 0000000..f462218 --- /dev/null +++ b/digital ciruits/masterslave_jkff/masterslave_jkff.bak @@ -0,0 +1,564 @@ +EESchema Schematic File Version 4 +LIBS:masterslave_jkff-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L sim_logic:CMOS_NAND X3 +U 1 1 5B29F141 +P 5450 3250 +F 0 "X3" H 5650 2978 50 0000 C CNN +F 1 "CMOS_NAND" H 5650 2887 50 0000 C CNN +F 2 "" H 5450 3250 50 0001 C CNN +F 3 "" H 5450 3250 50 0001 C CNN +F 4 "X" H 5450 3250 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5450 3250 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5450 3250 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5450 3250 50 0001 C CNN "Spice_Lib_File" + 1 5450 3250 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND3 X1 +U 1 1 5B29F238 +P 3600 3300 +F 0 "X1" H 3800 3028 50 0000 C CNN +F 1 "CMOS_NAND3" H 3800 2937 50 0000 C CNN +F 2 "" H 3600 3300 50 0001 C CNN +F 3 "" H 3600 3300 50 0001 C CNN +F 4 "X" H 3600 3300 50 0001 C CNN "Spice_Primitive" +F 5 "NAND3" H 3600 3300 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3600 3300 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 3600 3300 50 0001 C CNN "Spice_Lib_File" + 1 3600 3300 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND3 X2 +U 1 1 5B29F2F2 +P 3650 4550 +F 0 "X2" H 3850 4278 50 0000 C CNN +F 1 "CMOS_NAND3" H 3850 4187 50 0000 C CNN +F 2 "" H 3650 4550 50 0001 C CNN +F 3 "" H 3650 4550 50 0001 C CNN +F 4 "X" H 3650 4550 50 0001 C CNN "Spice_Primitive" +F 5 "NAND3" H 3650 4550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3650 4550 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 3650 4550 50 0001 C CNN "Spice_Lib_File" + 1 3650 4550 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X4 +U 1 1 5B29F3E9 +P 5500 4500 +F 0 "X4" H 5700 4228 50 0000 C CNN +F 1 "CMOS_NAND" H 5700 4137 50 0000 C CNN +F 2 "" H 5500 4500 50 0001 C CNN +F 3 "" H 5500 4500 50 0001 C CNN +F 4 "X" H 5500 4500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 5500 4500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5500 4500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5500 4500 50 0001 C CNN "Spice_Lib_File" + 1 5500 4500 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X6 +U 1 1 5B29F421 +P 7050 3200 +F 0 "X6" H 7250 2928 50 0000 C CNN +F 1 "CMOS_NAND" H 7250 2837 50 0000 C CNN +F 2 "" H 7050 3200 50 0001 C CNN +F 3 "" H 7050 3200 50 0001 C CNN +F 4 "X" H 7050 3200 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 7050 3200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7050 3200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 7050 3200 50 0001 C CNN "Spice_Lib_File" + 1 7050 3200 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X7 +U 1 1 5B29F51D +P 7150 4500 +F 0 "X7" H 7350 4228 50 0000 C CNN +F 1 "CMOS_NAND" H 7350 4137 50 0000 C CNN +F 2 "" H 7150 4500 50 0001 C CNN +F 3 "" H 7150 4500 50 0001 C CNN +F 4 "X" H 7150 4500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 7150 4500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 7150 4500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 7150 4500 50 0001 C CNN "Spice_Lib_File" + 1 7150 4500 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X9 +U 1 1 5B29F56B +P 8650 3200 +F 0 "X9" H 8850 2928 50 0000 C CNN +F 1 "CMOS_NAND" H 8850 2837 50 0000 C CNN +F 2 "" H 8650 3200 50 0001 C CNN +F 3 "" H 8650 3200 50 0001 C CNN +F 4 "X" H 8650 3200 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 8650 3200 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8650 3200 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 8650 3200 50 0001 C CNN "Spice_Lib_File" + 1 8650 3200 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NAND X8 +U 1 1 5B29F5E4 +P 8600 4500 +F 0 "X8" H 8800 4228 50 0000 C CNN +F 1 "CMOS_NAND" H 8800 4137 50 0000 C CNN +F 2 "" H 8600 4500 50 0001 C CNN +F 3 "" H 8600 4500 50 0001 C CNN +F 4 "X" H 8600 4500 50 0001 C CNN "Spice_Primitive" +F 5 "NAND" H 8600 4500 50 0001 C CNN "Spice_Model" +F 6 "Y" H 8600 4500 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 8600 4500 50 0001 C CNN "Spice_Lib_File" + 1 8600 4500 + 1 0 0 -1 +$EndComp +$Comp +L sim_logic:CMOS_NOT X5 +U 1 1 5B29F6B5 +P 5550 5800 +F 0 "X5" H 5750 5528 50 0000 C CNN +F 1 "CMOS_NOT" H 5750 5437 50 0000 C CNN +F 2 "" H 5550 5800 50 0001 C CNN +F 3 "" H 5550 5800 50 0001 C CNN +F 4 "X" H 5550 5800 50 0001 C CNN "Spice_Primitive" +F 5 "NOT" H 5550 5800 50 0001 C CNN "Spice_Model" +F 6 "Y" H 5550 5800 50 0001 C CNN "Spice_Netlist_Enabled" +F 7 "/home/akshay/Downloads/kicad-simulation-examples-master/libs/spice_models.lib" H 5550 5800 50 0001 C CNN "Spice_Lib_File" + 1 5550 5800 + 1 0 0 -1 +$EndComp +Text GLabel 1250 4000 0 50 Input ~ 0 +2 +Text GLabel 2100 3450 0 50 Input ~ 0 +1 +Text GLabel 2050 4450 0 50 Input ~ 0 +3 +Wire Wire Line + 2100 4000 2500 4000 +Wire Wire Line + 3000 4000 3000 3400 +Wire Wire Line + 3000 3400 3400 3400 +Wire Wire Line + 3000 4000 3000 4450 +Wire Wire Line + 3000 4450 3450 4450 +Connection ~ 3000 4000 +Wire Wire Line + 2100 3450 2500 3450 +Wire Wire Line + 2500 3450 2500 3300 +Wire Wire Line + 2500 3300 3400 3300 +Wire Wire Line + 2050 4450 2050 4550 +Wire Wire Line + 2050 4550 3450 4550 +Wire Wire Line + 4200 3300 4200 3150 +Wire Wire Line + 4200 3150 5250 3150 +Wire Wire Line + 4250 4550 4250 4600 +Wire Wire Line + 4250 4600 5300 4600 +Wire Wire Line + 6100 4500 6100 4600 +Wire Wire Line + 6100 4600 6300 4600 +Wire Wire Line + 6050 3250 6050 3100 +Wire Wire Line + 6050 3100 6150 3100 +Wire Wire Line + 2500 4000 2500 5800 +Wire Wire Line + 2500 5800 5350 5800 +Connection ~ 2500 4000 +Wire Wire Line + 2500 4000 3000 4000 +Wire Wire Line + 6150 5800 6500 5800 +Wire Wire Line + 6500 5800 6500 4400 +Wire Wire Line + 6500 3300 6850 3300 +Wire Wire Line + 6950 4400 6500 4400 +Connection ~ 6500 4400 +Wire Wire Line + 6500 4400 6500 3300 +Wire Wire Line + 7750 4500 7750 4600 +Wire Wire Line + 7750 4600 8400 4600 +Wire Wire Line + 7650 3200 7650 3100 +Wire Wire Line + 7650 3100 8450 3100 +Wire Wire Line + 8450 3300 8150 3300 +Wire Wire Line + 8150 3300 8150 3700 +Wire Wire Line + 8150 3700 9600 3700 +Wire Wire Line + 9600 3700 9600 4500 +Wire Wire Line + 9600 4500 9200 4500 +Wire Wire Line + 8400 4400 8200 4400 +Wire Wire Line + 8200 4400 8200 3800 +Wire Wire Line + 8200 3800 9450 3800 +Wire Wire Line + 9450 3800 9450 3200 +Wire Wire Line + 9450 3200 9250 3200 +Wire Wire Line + 5250 3350 4800 3350 +Wire Wire Line + 4800 3350 4800 3800 +Wire Wire Line + 4800 3800 6300 3800 +Wire Wire Line + 6300 3800 6300 4600 +Connection ~ 6300 4600 +Wire Wire Line + 6300 4600 6950 4600 +Wire Wire Line + 5300 4400 5100 4400 +Wire Wire Line + 5100 4400 5100 3900 +Wire Wire Line + 5100 3900 6200 3900 +Wire Wire Line + 6200 3900 6200 3100 +Connection ~ 6200 3100 +Wire Wire Line + 6200 3100 6850 3100 +$Comp +L Device:R R1 +U 1 1 5B2A209E +P 10300 3200 +F 0 "R1" V 10093 3200 50 0000 C CNN +F 1 "10meg" V 10184 3200 50 0000 C CNN +F 2 "" V 10230 3200 50 0001 C CNN +F 3 "~" H 10300 3200 50 0001 C CNN + 1 10300 3200 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR06 +U 1 1 5B2A2ACE +P 10750 3200 +F 0 "#PWR06" H 10750 2950 50 0001 C CNN +F 1 "GND" H 10755 3027 50 0000 C CNN +F 2 "" H 10750 3200 50 0001 C CNN +F 3 "" H 10750 3200 50 0001 C CNN + 1 10750 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10750 3200 10450 3200 +Connection ~ 9450 3200 +$Comp +L Device:R R2 +U 1 1 5B2A3E5E +P 10300 4500 +F 0 "R2" V 10093 4500 50 0000 C CNN +F 1 "10meg" V 10184 4500 50 0000 C CNN +F 2 "" V 10230 4500 50 0001 C CNN +F 3 "~" H 10300 4500 50 0001 C CNN + 1 10300 4500 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR05 +U 1 1 5B2A3E9F +P 10600 4500 +F 0 "#PWR05" H 10600 4250 50 0001 C CNN +F 1 "GND" H 10605 4327 50 0000 C CNN +F 2 "" H 10600 4500 50 0001 C CNN +F 3 "" H 10600 4500 50 0001 C CNN + 1 10600 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10600 4500 10450 4500 +Wire Wire Line + 10150 4500 10100 4500 +Wire Wire Line + 3400 3200 2600 3200 +Wire Wire Line + 2600 3200 2600 2100 +Wire Wire Line + 3450 4650 3450 5150 +Wire Wire Line + 3450 5150 9750 5150 +Wire Wire Line + 9750 5150 9750 3200 +Wire Wire Line + 9750 3200 9450 3200 +Text GLabel 9950 4050 0 50 Output ~ 0 +6 +Wire Wire Line + 9950 4050 10100 4050 +Wire Wire Line + 10100 4050 10100 4500 +$Comp +L pspice:VSOURCE V2 +U 1 1 5B2AA56F +P 1300 2000 +F 0 "V2" H 1528 2046 50 0000 L CNN +F 1 "VSOURCE" H 1528 1955 50 0000 L CNN +F 2 "" H 1300 2000 50 0001 C CNN +F 3 "" H 1300 2000 50 0001 C CNN +F 4 "V" H 1300 2000 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 1300 2000 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1300 2000 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1300 2000 + 1 0 0 -1 +$EndComp +Text GLabel 1150 1450 0 50 Input ~ 0 +1 +$Comp +L power:GND #PWR02 +U 1 1 5B2AA5E3 +P 1300 2650 +F 0 "#PWR02" H 1300 2400 50 0001 C CNN +F 1 "GND" H 1305 2477 50 0000 C CNN +F 2 "" H 1300 2650 50 0001 C CNN +F 3 "" H 1300 2650 50 0001 C CNN + 1 1300 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 2300 1300 2650 +Wire Wire Line + 1300 1700 1300 1450 +Wire Wire Line + 1300 1450 1150 1450 +$Comp +L pspice:VSOURCE V1 +U 1 1 5B2ACCD6 +P 1150 5150 +F 0 "V1" H 1378 5196 50 0000 L CNN +F 1 "VSOURCE" H 1378 5105 50 0000 L CNN +F 2 "" H 1150 5150 50 0001 C CNN +F 3 "" H 1150 5150 50 0001 C CNN +F 4 "V" H 1150 5150 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 1150 5150 50 0001 C CNN "Spice_Model" +F 6 "Y" H 1150 5150 50 0001 C CNN "Spice_Netlist_Enabled" + 1 1150 5150 + 1 0 0 -1 +$EndComp +Text GLabel 950 4450 0 50 Input ~ 0 +3 +Wire Wire Line + 950 4450 1150 4450 +Wire Wire Line + 1150 4450 1150 4850 +$Comp +L power:GND #PWR01 +U 1 1 5B2AE376 +P 1100 5850 +F 0 "#PWR01" H 1100 5600 50 0001 C CNN +F 1 "GND" H 1105 5677 50 0000 C CNN +F 2 "" H 1100 5850 50 0001 C CNN +F 3 "" H 1100 5850 50 0001 C CNN + 1 1100 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1100 5850 1100 5450 +Wire Wire Line + 1100 5450 1150 5450 +Text GLabel 3550 2550 0 50 Input ~ 0 +4 +Wire Wire Line + 3800 2900 3800 2550 +Wire Wire Line + 3800 2550 3550 2550 +Text GLabel 5400 2500 0 50 Input ~ 0 +4 +Wire Wire Line + 5400 2500 5650 2500 +Wire Wire Line + 5650 2500 5650 2850 +Text GLabel 6950 2450 0 50 Input ~ 0 +4 +Wire Wire Line + 7250 2800 7250 2450 +Wire Wire Line + 7250 2450 6950 2450 +Text GLabel 8550 2450 0 50 Input ~ 0 +4 +Wire Wire Line + 8850 2800 8850 2450 +Wire Wire Line + 8850 2450 8550 2450 +Text GLabel 8550 3950 0 50 Input ~ 0 +4 +Wire Wire Line + 8800 4100 8800 3950 +Wire Wire Line + 8800 3950 8550 3950 +Text GLabel 7150 3900 0 50 Input ~ 0 +4 +Wire Wire Line + 7350 4100 7350 3900 +Wire Wire Line + 7350 3900 7150 3900 +Text GLabel 5400 4000 0 50 Input ~ 0 +4 +Wire Wire Line + 5700 4100 5700 4000 +Wire Wire Line + 5700 4000 5400 4000 +Text GLabel 3650 4000 0 50 Input ~ 0 +4 +Wire Wire Line + 3850 4150 3850 4000 +Wire Wire Line + 3850 4000 3650 4000 +Text GLabel 5100 5300 0 50 Input ~ 0 +4 +Wire Wire Line + 5750 5500 5750 5300 +Wire Wire Line + 5750 5300 5100 5300 +$Comp +L pspice:VSOURCE V3 +U 1 1 5B2C1078 +P 2300 6550 +F 0 "V3" H 2528 6596 50 0000 L CNN +F 1 "VSOURCE" H 2528 6505 50 0000 L CNN +F 2 "" H 2300 6550 50 0001 C CNN +F 3 "" H 2300 6550 50 0001 C CNN +F 4 "V" H 2300 6550 50 0001 C CNN "Spice_Primitive" +F 5 "dc 0 pwl(0 0 5m 0 5.005m 3.3 10m 3.3 10.005m 0 15m 0 15.005m 3.3 20m 3.3 20.005m 0 25m 0 25.005m 3.3 30m 3.3 30.005m 0 35m 0 35.005m 3.3 40m 3.3 40.005m 0 45m 0 45.005m 3.3 50m 3.3)" H 2300 6550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 2300 6550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 2300 6550 + 1 0 0 -1 +$EndComp +Text GLabel 2100 5850 0 50 Input ~ 0 +2 +$Comp +L power:GND #PWR03 +U 1 1 5B2C1180 +P 2300 7050 +F 0 "#PWR03" H 2300 6800 50 0001 C CNN +F 1 "GND" H 2305 6877 50 0000 C CNN +F 2 "" H 2300 7050 50 0001 C CNN +F 3 "" H 2300 7050 50 0001 C CNN + 1 2300 7050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2300 7050 2300 6850 +Wire Wire Line + 2300 6250 2300 5850 +Wire Wire Line + 2300 5850 2100 5850 +$Comp +L pspice:VSOURCE V4 +U 1 1 5B2C5F12 +P 3900 6950 +F 0 "V4" H 4128 6996 50 0000 L CNN +F 1 "VSOURCE" H 4128 6905 50 0000 L CNN +F 2 "" H 3900 6950 50 0001 C CNN +F 3 "" H 3900 6950 50 0001 C CNN +F 4 "V" H 3900 6950 50 0001 C CNN "Spice_Primitive" +F 5 "dc 3.3" H 3900 6950 50 0001 C CNN "Spice_Model" +F 6 "Y" H 3900 6950 50 0001 C CNN "Spice_Netlist_Enabled" + 1 3900 6950 + 1 0 0 -1 +$EndComp +Text GLabel 3850 6250 0 50 Input ~ 0 +4 +$Comp +L power:GND #PWR04 +U 1 1 5B2C5FB4 +P 3900 7350 +F 0 "#PWR04" H 3900 7100 50 0001 C CNN +F 1 "GND" H 3905 7177 50 0000 C CNN +F 2 "" H 3900 7350 50 0001 C CNN +F 3 "" H 3900 7350 50 0001 C CNN + 1 3900 7350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3900 7350 3900 7250 +Wire Wire Line + 3900 6650 3900 6250 +Wire Wire Line + 3900 6250 3850 6250 +Text Notes 7650 6150 0 50 ~ 0 +.tran .25m 50m +Text GLabel 6150 2600 0 50 Output ~ 0 +q12 +Wire Wire Line + 6150 2600 6300 2600 +Wire Wire Line + 6300 2600 6300 2850 +Wire Wire Line + 6300 2850 6150 2850 +Wire Wire Line + 6150 2850 6150 3100 +Connection ~ 6150 3100 +Wire Wire Line + 6150 3100 6200 3100 +Wire Wire Line + 1250 3700 1250 4000 +Wire Wire Line + 2100 3700 2100 4000 +Connection ~ 10100 4500 +Connection ~ 9600 4500 +Connection ~ 9750 3200 +Text GLabel 9800 2700 0 50 Output ~ 0 +5 +Wire Wire Line + 10100 3200 10150 3200 +Wire Wire Line + 9750 3200 10100 3200 +Connection ~ 10100 3200 +Wire Wire Line + 10100 2700 10100 3200 +Wire Wire Line + 9800 2700 10100 2700 +Wire Wire Line + 2600 2100 10050 2100 +Wire Wire Line + 10100 4500 10050 4500 +Wire Wire Line + 10050 4500 9600 4500 +Connection ~ 10050 4500 +Wire Wire Line + 10050 2100 10050 4500 +Wire Wire Line + 1250 3700 2100 3700 +$EndSCHEMATC |