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author | Akshay NH | 2018-06-28 19:22:03 +0530 |
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committer | Akshay NH | 2018-06-28 19:22:03 +0530 |
commit | d1edc2c0c9b8d823892b94482e01451e82c3eec1 (patch) | |
tree | 9fb54dfd93a975be8b2a8cb29b21eb5639ac29ef /digital ciruits/cmos_nand_dflip/cmos_nand_dflip-cache.lib | |
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adding kicad analog and digital circuits
Diffstat (limited to 'digital ciruits/cmos_nand_dflip/cmos_nand_dflip-cache.lib')
-rw-r--r-- | digital ciruits/cmos_nand_dflip/cmos_nand_dflip-cache.lib | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/digital ciruits/cmos_nand_dflip/cmos_nand_dflip-cache.lib b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip-cache.lib new file mode 100644 index 0000000..a3cd44b --- /dev/null +++ b/digital ciruits/cmos_nand_dflip/cmos_nand_dflip-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:VDD +# +DEF power:VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power:VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:0 +# +DEF pspice:0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 50 H I C CNN +F1 "pspice:0" 0 -70 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND +# +DEF sim_logic:CMOS_NAND X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# sim_logic:CMOS_NAND3 +# +DEF sim_logic:CMOS_NAND3 X 0 20 Y Y 1 F N +F0 "X" 0 -400 50 H V C CNN +F1 "sim_logic:CMOS_NAND3" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +A 200 0 200 -899 899 0 1 0 N 200 -200 200 200 +P 4 0 1 0 200 200 0 200 0 -200 200 -200 N +X A A -200 100 200 R 50 50 1 1 I +X B B -200 0 200 R 50 50 1 1 I +X C C -200 -100 200 R 50 50 1 1 I +X Out Out 600 0 200 L 50 50 1 1 O I +X VDD VDD 200 400 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library |