adding kicad analog and digital circuits

14 files changed, 1009 insertions, 0 deletions

diff --git a/digital ciruits/cmos_nand/cmos_nand-cache.lib b/digital ciruits/cmos_nand/cmos_nand-cache.lib
new file mode 100644
index 0000000..6dd4c50
--- /dev/null
+++ b/digital ciruits/cmos_nand/cmos_nand-cache.lib
@@ -0,0 +1,90 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# power:VDD
+#
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+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power:VDD" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VDD 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pspice:0
+#
+DEF pspice:0 #GND 0 0 Y Y 1 F P
+F0 "#GND" 0 -100 50 H I C CNN
+F1 "pspice:0" 0 -70 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
+X 0 1 0 0 0 R 40 40 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pspice:MNMOS
+#
+DEF pspice:MNMOS M 0 0 Y Y 1 F N
+F0 "M" 300 50 50 H V L CNN
+F1 "pspice:MNMOS" 300 -50 50 H V L CNN
+F2 "" -25 0 50 H I C CNN
+F3 "" -25 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -50 -100 -50 100 N
+P 2 0 1 0 -25 -100 100 -100 N
+P 2 0 1 0 100 100 -25 100 N
+P 2 0 1 0 200 0 -25 0 N
+P 4 0 1 0 -25 0 50 25 50 -25 -25 0 F
+P 2 1 1 0 -25 -100 -25 100 N
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 150 R 50 50 1 1 I
+X S 3 100 -200 100 U 50 50 1 1 P
+X B 4 200 -200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pspice:MPMOS
+#
+DEF pspice:MPMOS M 0 0 Y Y 1 F N
+F0 "M" 300 50 50 H V L CNN
+F1 "pspice:MPMOS" 300 -50 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -50 100 -50 -100 N
+P 2 0 1 0 -25 -100 100 -100 N
+P 2 0 1 0 100 100 -25 100 N
+P 2 0 1 0 200 0 -25 0 N
+P 4 0 1 0 200 0 125 25 125 -25 200 0 F
+P 2 1 1 0 -25 -100 -25 100 N
+X D 1 100 -200 100 U 50 50 1 1 P
+X G 2 -200 0 150 R 50 50 1 1 I
+X S 3 100 200 100 D 50 50 1 1 P
+X B 4 200 200 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pspice:VSOURCE
+#
+DEF pspice:VSOURCE V 0 40 Y Y 1 F N
+F0 "V" -250 300 50 H V C CNN
+F1 "pspice:VSOURCE" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 0 200 0 1 0 N
+T 0 -320 -10 50 0 0 1 V Normal 0 C C
+P 2 0 1 0 -250 -250 -250 150 F
+P 3 0 1 0 -300 150 -250 250 -200 150 F
+X E1 1 0 300 100 D 50 50 1 1 I
+X E2 2 0 -300 100 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/digital ciruits/cmos_nand/cmos_nand.bak b/digital ciruits/cmos_nand/cmos_nand.bak
new file mode 100644
index 0000000..23bc2a2
--- /dev/null
+++ b/digital ciruits/cmos_nand/cmos_nand.bak
@@ -0,0 +1,283 @@
+EESchema Schematic File Version 4
+LIBS:cmos_nand-cache
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+EELAYER END
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+F 3 "" H 10200 3100 50  0001 C CNN
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+Wire Notes Line
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+Wire Wire Line
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+Wire Wire Line
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+Text Notes 4950 6000 0    50   ~ 0
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+Wire Wire Line
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+Text Notes 9900 4850 0    50   ~ 0
+Supply voltage
+Text Notes 1000 1600 0    50   ~ 0
+Notes:\n\n1. the dotted section implements a 2-input NAND gate using PMOS/NMOS\n2. Run the simulation and plot V(A), V(B) and V(out)
+$Comp
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diff --git a/digital ciruits/cmos_nand/cmos_nand.cir b/digital ciruits/cmos_nand/cmos_nand.cir
new file mode 100644
index 0000000..b426375
--- /dev/null
+++ b/digital ciruits/cmos_nand/cmos_nand.cir
@@ -0,0 +1,16 @@
+.title KiCad schematic
+V1 A 0 dc 0 pulse(0 3.3 0 0 0 100m 200m)
+V2 VDD 0 3.3
+M1 Out A VDD VDD MPMOS
+M2 Out A 1 1 MNMOS
+M4 Out B VDD VDD MPMOS
+M3 1 B 0 0 MNMOS
+V3 B 0 dc 0 pulse(0 3.3 0 0 0 50m 100m)
+.tran 1m 400m
+.model mnmos nmos level=8 version=3.3.0
+.model mpmos pmos level=8 version=3.3.0
+.control
+run
+plot v(a)+5 v(b)+10 v(out)
+.endc
+.end
diff --git a/digital ciruits/cmos_nand/cmos_nand.pro b/digital ciruits/cmos_nand/cmos_nand.pro
new file mode 100644
index 0000000..152769c
--- /dev/null
+++ b/digital ciruits/cmos_nand/cmos_nand.pro
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
diff --git a/digital ciruits/cmos_nand/cmos_nand.sch b/digital ciruits/cmos_nand/cmos_nand.sch
new file mode 100644
index 0000000..d8cdc4c
--- /dev/null
+++ b/digital ciruits/cmos_nand/cmos_nand.sch
@@ -0,0 +1,287 @@
+EESchema Schematic File Version 4
+LIBS:cmos_nand-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
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+Wire Wire Line
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+	1400 2250 1500 2250
+$Comp
+L pspice:0 #GND02
+U 1 1 5B24F37F
+P 1400 5750
+F 0 "#GND02" H 1400 5650 50  0001 C CNN
+F 1 "0" H 1400 5837 50  0000 C CNN
+F 2 "" H 1400 5750 50  0001 C CNN
+F 3 "" H 1400 5750 50  0001 C CNN
+	1    1400 5750
+	1    0    0    -1  
+$EndComp
+$Comp
+L pspice:VSOURCE V3
+U 1 1 5B24F388
+P 1400 5000
+F 0 "V3" H 1828 5046 50  0000 L CNN
+F 1 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1828 4955 50  0000 L CNN
+F 2 "" H 1400 5000 50  0001 C CNN
+F 3 "" H 1400 5000 50  0001 C CNN
+F 4 "V" H 1400 5000 50  0001 C CNN "Spice_Primitive"
+F 5 "dc 0 pulse(0 3.3 0 0 0 50m 100m)" H 1400 5000 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 1400 5000 50  0001 C CNN "Spice_Netlist_Enabled"
+	1    1400 5000
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1400 4200 1500 4200
+Text Notes 1150 6050 0    50   ~ 0
+Test input signals
+Text Notes 4950 6550 0    50   ~ 0
+.control\nrun\nplot v(a)+5 v(b)+10 v(out)\n.endc
+Text GLabel 5000 4100 0    50   BiDi ~ 0
+1
+Wire Wire Line
+	1400 2250 1400 2750
+Wire Wire Line
+	1400 3350 1400 3800
+Wire Wire Line
+	1400 4200 1400 4700
+Wire Wire Line
+	1400 5300 1400 5750
+Wire Wire Line
+	10200 3500 10200 3100
+Wire Wire Line
+	10200 4100 10200 4500
+$EndSCHEMATC
diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/AKS.bck b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.bck
new file mode 100644
index 0000000..5f3ed79
--- /dev/null
+++ b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.bck
@@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/AKS.dcm b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.dcm
new file mode 100644
index 0000000..5f3ed79
--- /dev/null
+++ b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.dcm
@@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0
+#
+#End Doc Library
diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/AKS.lib b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.lib
new file mode 100644
index 0000000..58a69aa
--- /dev/null
+++ b/digital ciruits/cmos_nand/d_flip flop_sub/AKS.lib
@@ -0,0 +1,21 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# dflipflop
+#
+DEF dflipflop X 0 40 Y Y 1 F N
+F0 "X" 0 -250 50 H V C CNN
+F1 "dflipflop" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -250 150 250 -200 0 1 0 N
+X CLK B -350 100 100 R 50 50 1 1 I
+X D B -350 -150 100 R 50 50 1 1 I
+X nq Out 350 -150 100 L 50 50 1 1 O
+X q Out 350 100 100 L 50 50 1 1 O
+X VDD VDD 0 250 100 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.kicad_pcb b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.kicad_pcb
new file mode 100644
index 0000000..02c8ecb
--- /dev/null
+++ b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.kicad_pcb
@@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.pro b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.pro
new file mode 100644
index 0000000..152769c
--- /dev/null
+++ b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.pro
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.sch b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.sch
new file mode 100644
index 0000000..fff8c68
--- /dev/null
+++ b/digital ciruits/cmos_nand/d_flip flop_sub/d_flip flop_sub.sch
@@ -0,0 +1,4 @@
+EESchema Schematic File Version 2
+EELAYER 25 0
+EELAYER END
+$EndSCHEMATC
diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/pspice.dcm b/digital ciruits/cmos_nand/d_flip flop_sub/pspice.dcm
new file mode 100644
index 0000000..0c3c718
--- /dev/null
+++ b/digital ciruits/cmos_nand/d_flip flop_sub/pspice.dcm
@@ -0,0 +1,18 @@
+EESchema-DOCLIB  Version 2.0
+#
+$CMP MNMOS
+D N-channel MOSFET
+K mosfet nmos
+$ENDCMP
+#
+$CMP MPMOS
+D P-channel MOSFET
+K mosfet pmos
+$ENDCMP
+#
+$CMP R
+D Resistance
+K R DEV
+$ENDCMP
+#
+#End Doc Library
diff --git a/digital ciruits/cmos_nand/d_flip flop_sub/pspice.lib b/digital ciruits/cmos_nand/d_flip flop_sub/pspice.lib
new file mode 100644
index 0000000..e95d245
--- /dev/null
+++ b/digital ciruits/cmos_nand/d_flip flop_sub/pspice.lib
@@ -0,0 +1,213 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# 0
+#
+DEF 0 #GND 0 0 Y Y 1 F P
+F0 "#GND" 0 -100 50 H I C CNN
+F1 "0" 0 -70 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
+X 0 1 0 0 0 R 40 40 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# CAP
+#
+DEF CAP C 0 10 Y Y 1 F N
+F0 "C" 100 150 50 V V C CNN
+F1 "CAP" 100 -150 50 V V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS C
+DRAW
+P 2 0 1 0 -150 -50 150 -50 N
+P 2 0 1 0 -150 50 150 50 N
+X ~ 1 0 250 200 D 40 40 1 1 P
+X ~ 2 0 -250 200 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# DIODE
+#
+DEF DIODE D 0 40 Y N 1 F N
+F0 "D" 0 150 50 H V C CNN
+F1 "DIODE" 0 -175 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 75 100 75 -100 N
+P 3 0 1 0 -75 100 -75 -100 75 0 F
+X K 1 -200 0 150 R 50 50 1 1 I
+X A 2 200 0 150 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# INDUCTOR
+#
+DEF INDUCTOR L 0 0 N Y 1 F N
+F0 "L" 0 100 50 H V C CNN
+F1 "INDUCTOR" 0 -50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -150 0 50 1 1799 0 1 0 N -100 0 -200 0
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 1 1799 0 1 0 N 100 0 0 0
+A 150 0 50 1 1799 0 1 0 N 200 0 100 0
+X 1 1 -250 0 50 R 30 30 1 1 I
+X 2 2 250 0 50 L 30 30 1 1 I
+ENDDRAW
+ENDDEF
+#
+# ISOURCE
+#
+DEF ISOURCE I 0 40 Y Y 1 F N
+F0 "I" -300 350 50 H V C CNN
+F1 "ISOURCE" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 -100 200 0 1 0 N
+C 0 100 202 0 1 0 N
+T 0 -270 -10 50 0 0 1 I Normal 0 C C
+P 2 0 1 0 -300 -200 -300 200 F
+P 3 0 1 0 -350 200 -300 300 -250 200 F
+X E1 1 0 400 100 D 50 50 1 1 I
+X E2 2 0 -400 100 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# MNMOS
+#
+DEF MNMOS M 0 0 Y Y 1 F N
+F0 "M" 300 50 50 H V L CNN
+F1 "MNMOS" 300 -50 50 H V L CNN
+F2 "" -25 0 50 H I C CNN
+F3 "" -25 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -50 -100 -50 100 N
+P 2 0 1 0 -25 -100 100 -100 N
+P 2 0 1 0 100 100 -25 100 N
+P 2 0 1 0 200 0 -25 0 N
+P 4 0 1 0 -25 0 50 25 50 -25 -25 0 F
+P 2 1 1 0 -25 -100 -25 100 N
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 150 R 50 50 1 1 I
+X S 3 100 -200 100 U 50 50 1 1 P
+X B 4 200 -200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# MPMOS
+#
+DEF MPMOS M 0 0 Y Y 1 F N
+F0 "M" 300 50 50 H V L CNN
+F1 "MPMOS" 300 -50 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -50 100 -50 -100 N
+P 2 0 1 0 -25 -100 100 -100 N
+P 2 0 1 0 100 100 -25 100 N
+P 2 0 1 0 200 0 -25 0 N
+P 4 0 1 0 200 0 125 25 125 -25 200 0 F
+P 2 1 1 0 -25 -100 -25 100 N
+X D 1 100 -200 100 U 50 50 1 1 P
+X G 2 -200 0 150 R 50 50 1 1 I
+X S 3 100 200 100 D 50 50 1 1 P
+X B 4 200 200 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# QNPN
+#
+DEF QNPN Q 0 0 Y Y 1 F N
+F0 "Q" -100 300 50 H V C CNN
+F1 "QNPN" -100 200 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 0 0 0 150 -150 N
+P 4 0 0 0 150 -150 150 -50 50 -150 150 -150 F
+P 2 0 1 0 0 -150 0 150 N
+P 2 0 1 0 0 0 150 150 N
+P 4 0 1 0 -100 -150 0 -150 0 -150 0 -150 N
+X C 1 150 350 200 D 40 40 1 1 P
+X B 2 -300 0 300 R 40 40 1 1 I
+X E 3 150 -350 200 U 40 40 1 1 P
+X Substrat 4 -100 -350 200 U 50 20 1 1 I
+ENDDRAW
+ENDDEF
+#
+# QPNP
+#
+DEF QPNP Q 0 0 Y Y 1 F N
+F0 "Q" -100 300 50 H V C CNN
+F1 "QPNP" -100 200 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 0 -150 0 150 N
+P 2 0 1 0 0 0 150 -150 N
+P 2 0 1 0 0 0 150 150 N
+P 3 0 1 0 -100 -150 0 -150 0 -150 N
+P 4 0 1 0 120 -180 180 -120 85 -85 120 -180 F
+X C 1 150 350 200 D 40 40 1 1 C
+X B 2 -300 0 300 R 40 40 1 1 I
+X E 3 150 -350 200 U 40 40 1 1 E
+X Substrat 4 -100 -350 200 U 50 20 1 1 I
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -40 150 40 -150 0 1 0 N
+X ~ 1 0 250 100 D 50 50 1 1 P
+X ~ 2 0 -250 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VSOURCE
+#
+DEF VSOURCE V 0 40 Y Y 1 F N
+F0 "V" -250 300 50 H V C CNN
+F1 "VSOURCE" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 0 200 0 1 0 N
+T 0 -320 -10 50 0 0 1 V Normal 0 C C
+P 2 0 1 0 -250 -250 -250 150 F
+P 3 0 1 0 -300 150 -250 250 -200 150 F
+X E1 1 0 300 100 D 50 50 1 1 I
+X E2 2 0 -300 100 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# dflip
+#
+DEF dflip X 0 40 Y Y 1 F N
+F0 "X" 0 -150 50 H V C CNN
+F1 "dflip" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -150 100 150 -100 0 1 0 N
+X CLK B -250 50 100 R 50 50 1 1 I
+X D B -250 -50 100 R 50 50 1 1 I
+X nq Out 250 -50 100 L 50 50 1 1 O
+X q Out 250 50 100 L 50 50 1 1 O
+X VDD VDD 0 200 100 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/digital ciruits/cmos_nand/sym-lib-table b/digital ciruits/cmos_nand/sym-lib-table
new file mode 100644
index 0000000..a9aa174
--- /dev/null
+++ b/digital ciruits/cmos_nand/sym-lib-table
@@ -0,0 +1,4 @@
+(sym_lib_table
+  (lib (name basic_gates)(type Legacy)(uri /home/akshay/kicad_examples/and_sub/basic_gates.lib)(options "")(descr ""))
+  (lib (name sim_logic)(type Legacy)(uri "/home/akshay/Desktop/digital ciruits/libs/sim_logic.lib")(options "")(descr ""))
+)