adding kicad analog and digital circuits

6 files changed, 328 insertions, 0 deletions

diff --git a/analog circuits/clipper circuit/clipper circuit-cache.lib b/analog circuits/clipper circuit/clipper circuit-cache.lib
new file mode 100644
index 0000000..eb61469
--- /dev/null
+++ b/analog circuits/clipper circuit/clipper circuit-cache.lib
@@ -0,0 +1,73 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Device:D_ALT
+#
+DEF Device:D_ALT D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "Device:D_ALT" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ TO-???*
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+P 2 0 1 8 -50 50 -50 -50 N
+P 2 0 1 0 50 0 -50 0 N
+P 4 0 1 8 50 50 50 -50 -50 0 50 50 F
+X K 1 -150 0 100 R 50 50 1 1 P
+X A 2 150 0 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device:R
+#
+DEF Device:R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "Device:R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# power:GND
+#
+DEF power:GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power:GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pspice:VSOURCE
+#
+DEF pspice:VSOURCE V 0 40 Y Y 1 F N
+F0 "V" -250 300 50 H V C CNN
+F1 "pspice:VSOURCE" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 0 200 0 1 0 N
+T 0 -320 -10 50 0 0 1 V Normal 0 C C
+P 2 0 1 0 -250 -250 -250 150 F
+P 3 0 1 0 -300 150 -250 250 -200 150 F
+X E1 1 0 300 100 D 50 50 1 1 I
+X E2 2 0 -300 100 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/analog circuits/clipper circuit/clipper circuit.bak b/analog circuits/clipper circuit/clipper circuit.bak
new file mode 100644
index 0000000..30fb589
--- /dev/null
+++ b/analog circuits/clipper circuit/clipper circuit.bak
@@ -0,0 +1,104 @@
+EESchema Schematic File Version 4
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L pspice:VSOURCE V1
+U 1 1 5B0DADA3
+P 3750 4350
+F 0 "V1" H 3978 4396 50  0000 L CNN
+F 1 "VSOURCE" H 3978 4305 50  0000 L CNN
+F 2 "" H 3750 4350 50  0001 C CNN
+F 3 "" H 3750 4350 50  0001 C CNN
+F 4 "V" H 3750 4350 50  0001 C CNN "Spice_Primitive"
+F 5 "sin(0 5)" H 3750 4350 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 3750 4350 50  0001 C CNN "Spice_Netlist_Enabled"
+	1    3750 4350
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:D_ALT D1
+U 1 1 5B0DAE19
+P 5150 4000
+F 0 "D1" H 5150 4216 50  0000 C CNN
+F 1 "D_ALT" H 5150 4125 50  0000 C CNN
+F 2 "" H 5150 4000 50  0001 C CNN
+F 3 "~" H 5150 4000 50  0001 C CNN
+	1    5150 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5B0DAE60
+P 5950 4300
+F 0 "R1" H 6020 4346 50  0000 L CNN
+F 1 "1k" H 6020 4255 50  0000 L CNN
+F 2 "" V 5880 4300 50  0001 C CNN
+F 3 "~" H 5950 4300 50  0001 C CNN
+	1    5950 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3750 4050 3750 4000
+Wire Wire Line
+	3750 4000 4150 4000
+Wire Wire Line
+	5300 4000 5850 4000
+Wire Wire Line
+	5950 4000 5950 4150
+Wire Wire Line
+	5950 4450 5950 4800
+Wire Wire Line
+	5950 4800 4850 4800
+Wire Wire Line
+	3750 4800 3750 4650
+$Comp
+L power:GND #PWR01
+U 1 1 5B0DAEDB
+P 4850 5100
+F 0 "#PWR01" H 4850 4850 50  0001 C CNN
+F 1 "GND" H 4855 4927 50  0000 C CNN
+F 2 "" H 4850 5100 50  0001 C CNN
+F 3 "" H 4850 5100 50  0001 C CNN
+	1    4850 5100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4850 5100 4850 4800
+Connection ~ 4850 4800
+Wire Wire Line
+	4850 4800 3750 4800
+Text GLabel 3600 3800 0    50   Input ~ 0
+ip
+Wire Wire Line
+	3600 3800 4150 3800
+Wire Wire Line
+	4150 3800 4150 4000
+Connection ~ 4150 4000
+Wire Wire Line
+	4150 4000 5000 4000
+Text GLabel 6600 3850 0    50   Output ~ 0
+out
+Wire Wire Line
+	6600 3850 6850 3850
+Wire Wire Line
+	6850 3850 6850 3650
+Wire Wire Line
+	6850 3650 5850 3650
+Wire Wire Line
+	5850 3650 5850 4000
+Connection ~ 5850 4000
+Wire Wire Line
+	5850 4000 5950 4000
+$EndSCHEMATC
diff --git a/analog circuits/clipper circuit/clipper circuit.cir b/analog circuits/clipper circuit/clipper circuit.cir
new file mode 100644
index 0000000..68338d1
--- /dev/null
+++ b/analog circuits/clipper circuit/clipper circuit.cir
@@ -0,0 +1,6 @@
+.title KiCad schematic
+V1 ip GND sin(0 5)
+D1 out ip D_ALT
+R1 out GND 1k
+.tran .25m 30m
+.end
diff --git a/analog circuits/clipper circuit/clipper circuit.kicad_pcb b/analog circuits/clipper circuit/clipper circuit.kicad_pcb
new file mode 100644
index 0000000..02c8ecb
--- /dev/null
+++ b/analog circuits/clipper circuit/clipper circuit.kicad_pcb
@@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )
diff --git a/analog circuits/clipper circuit/clipper circuit.pro b/analog circuits/clipper circuit/clipper circuit.pro
new file mode 100644
index 0000000..152769c
--- /dev/null
+++ b/analog circuits/clipper circuit/clipper circuit.pro
@@ -0,0 +1,33 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
diff --git a/analog circuits/clipper circuit/clipper circuit.sch b/analog circuits/clipper circuit/clipper circuit.sch
new file mode 100644
index 0000000..c06a66e
--- /dev/null
+++ b/analog circuits/clipper circuit/clipper circuit.sch
@@ -0,0 +1,111 @@
+EESchema Schematic File Version 4
+LIBS:clipper circuit-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L pspice:VSOURCE V1
+U 1 1 5B0DADA3
+P 3750 4350
+F 0 "V1" H 3978 4396 50  0000 L CNN
+F 1 "VSOURCE" H 3978 4305 50  0000 L CNN
+F 2 "" H 3750 4350 50  0001 C CNN
+F 3 "" H 3750 4350 50  0001 C CNN
+F 4 "V" H 3750 4350 50  0001 C CNN "Spice_Primitive"
+F 5 "sin(0 5)" H 3750 4350 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 3750 4350 50  0001 C CNN "Spice_Netlist_Enabled"
+	1    3750 4350
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:D_ALT D1
+U 1 1 5B0DAE19
+P 5150 4000
+F 0 "D1" H 5150 4216 50  0000 C CNN
+F 1 "D_ALT" H 5150 4125 50  0000 C CNN
+F 2 "" H 5150 4000 50  0001 C CNN
+F 3 "~" H 5150 4000 50  0001 C CNN
+F 4 "D" H 5150 4000 50  0001 C CNN "Spice_Primitive"
+F 5 "D_ALT" H 5150 4000 50  0001 C CNN "Spice_Model"
+F 6 "Y" H 5150 4000 50  0001 C CNN "Spice_Netlist_Enabled"
+F 7 "2 1" H 5150 4000 50  0001 C CNN "Spice_Node_Sequence"
+	1    5150 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5B0DAE60
+P 5950 4300
+F 0 "R1" H 6020 4346 50  0000 L CNN
+F 1 "1k" H 6020 4255 50  0000 L CNN
+F 2 "" V 5880 4300 50  0001 C CNN
+F 3 "~" H 5950 4300 50  0001 C CNN
+	1    5950 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3750 4050 3750 4000
+Wire Wire Line
+	3750 4000 4150 4000
+Wire Wire Line
+	5300 4000 5850 4000
+Wire Wire Line
+	5950 4000 5950 4150
+Wire Wire Line
+	5950 4450 5950 4800
+Wire Wire Line
+	5950 4800 4850 4800
+Wire Wire Line
+	3750 4800 3750 4650
+$Comp
+L power:GND #PWR01
+U 1 1 5B0DAEDB
+P 4850 5100
+F 0 "#PWR01" H 4850 4850 50  0001 C CNN
+F 1 "GND" H 4855 4927 50  0000 C CNN
+F 2 "" H 4850 5100 50  0001 C CNN
+F 3 "" H 4850 5100 50  0001 C CNN
+	1    4850 5100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4850 5100 4850 4800
+Connection ~ 4850 4800
+Wire Wire Line
+	4850 4800 3750 4800
+Text GLabel 3600 3800 0    50   Input ~ 0
+ip
+Wire Wire Line
+	3600 3800 4150 3800
+Wire Wire Line
+	4150 3800 4150 4000
+Connection ~ 4150 4000
+Wire Wire Line
+	4150 4000 5000 4000
+Text GLabel 6600 3850 0    50   Output ~ 0
+out
+Wire Wire Line
+	6600 3850 6850 3850
+Wire Wire Line
+	6850 3850 6850 3650
+Wire Wire Line
+	6850 3650 5850 3650
+Wire Wire Line
+	5850 3650 5850 4000
+Connection ~ 5850 4000
+Wire Wire Line
+	5850 4000 5950 4000
+Text Notes 7700 5250 0    50   ~ 0
+.tran .25m 30m
+$EndSCHEMATC