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| author | Akshay NH | 2018-06-28 19:22:03 +0530 |
|---|---|---|
| committer | Akshay NH | 2018-06-28 19:22:03 +0530 |
| commit | d1edc2c0c9b8d823892b94482e01451e82c3eec1 (patch) | |
| tree | 9fb54dfd93a975be8b2a8cb29b21eb5639ac29ef /analog circuits/RLC-parallel | |
| download | eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.tar.gz eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.tar.bz2 eSIm-Kicad-Simulations-d1edc2c0c9b8d823892b94482e01451e82c3eec1.zip | |
adding kicad analog and digital circuits
Diffstat (limited to 'analog circuits/RLC-parallel')
| -rw-r--r-- | analog circuits/RLC-parallel/RLC-parallel-cache.lib | 105 | ||||
| -rw-r--r-- | analog circuits/RLC-parallel/RLC-parallel.bak | 120 | ||||
| -rw-r--r-- | analog circuits/RLC-parallel/RLC-parallel.cir | 7 | ||||
| -rw-r--r-- | analog circuits/RLC-parallel/RLC-parallel.kicad_pcb | 1 | ||||
| -rw-r--r-- | analog circuits/RLC-parallel/RLC-parallel.pro | 33 | ||||
| -rw-r--r-- | analog circuits/RLC-parallel/RLC-parallel.sch | 136 |
6 files changed, 402 insertions, 0 deletions
diff --git a/analog circuits/RLC-parallel/RLC-parallel-cache.lib b/analog circuits/RLC-parallel/RLC-parallel-cache.lib new file mode 100644 index 0000000..603b5a7 --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel-cache.lib @@ -0,0 +1,105 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device:C +# +DEF Device:C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device:C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:L +# +DEF Device:L L 0 40 N N 1 F N +F0 "L" -50 0 50 V V C CNN +F1 "Device:L" 75 0 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Choke_* + *Coil* + Inductor_* + L_* +$ENDFPLIST +DRAW +A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50 +A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0 +A 0 25 25 -899 899 0 1 0 N 0 0 0 50 +A 0 75 25 -899 899 0 1 0 N 0 50 0 100 +X 1 1 0 150 50 D 50 50 1 1 P +X 2 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device:R +# +DEF Device:R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device:R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# power:GND +# +DEF power:GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power:GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power:PWR_FLAG +# +DEF power:PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "power:PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +X pwr 1 0 0 0 U 50 50 0 0 w +ENDDRAW +ENDDEF +# +# pspice:VSOURCE +# +DEF pspice:VSOURCE V 0 40 Y Y 1 F N +F0 "V" -250 300 50 H V C CNN +F1 "pspice:VSOURCE" 0 0 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 0 200 0 1 0 N +T 0 -320 -10 50 0 0 1 V Normal 0 C C +P 2 0 1 0 -250 -250 -250 150 F +P 3 0 1 0 -300 150 -250 250 -200 150 F +X E1 1 0 300 100 D 50 50 1 1 I +X E2 2 0 -300 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/analog circuits/RLC-parallel/RLC-parallel.bak b/analog circuits/RLC-parallel/RLC-parallel.bak new file mode 100644 index 0000000..30d8b63 --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel.bak @@ -0,0 +1,120 @@ +EESchema Schematic File Version 4
+LIBS:esim-11-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L pspice:VSOURCE V1
+U 1 1 5B090E79
+P 4200 3550
+F 0 "V1" H 4428 3596 50 0000 L CNN
+F 1 "VSOURCE" H 4428 3505 50 0000 L CNN
+F 2 "" H 4200 3550 50 0001 C CNN
+F 3 "" H 4200 3550 50 0001 C CNN
+F 4 "V" H 4200 3550 50 0001 C CNN "Spice_Primitive"
+F 5 "ac 5 0" H 4200 3550 50 0001 C CNN "Spice_Model"
+F 6 "Y" H 4200 3550 50 0001 C CNN "Spice_Netlist_Enabled"
+ 1 4200 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5B090F12
+P 6300 3000
+F 0 "R1" H 6370 3046 50 0000 L CNN
+F 1 "1k" H 6370 2955 50 0000 L CNN
+F 2 "" V 6230 3000 50 0001 C CNN
+F 3 "~" H 6300 3000 50 0001 C CNN
+ 1 6300 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L Device:L L1
+U 1 1 5B090F9F
+P 6300 3850
+F 0 "L1" H 6353 3896 50 0000 L CNN
+F 1 "100m" H 6353 3805 50 0000 L CNN
+F 2 "" H 6300 3850 50 0001 C CNN
+F 3 "~" H 6300 3850 50 0001 C CNN
+ 1 6300 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L Device:C C1
+U 1 1 5B091068
+P 7100 3350
+F 0 "C1" H 7215 3396 50 0000 L CNN
+F 1 "0.1u" H 7215 3305 50 0000 L CNN
+F 2 "" H 7138 3200 50 0001 C CNN
+F 3 "~" H 7100 3350 50 0001 C CNN
+ 1 7100 3350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4200 3250 4200 2600
+Wire Wire Line
+ 4200 2600 6300 2600
+Wire Wire Line
+ 6300 2600 6300 2850
+Wire Wire Line
+ 6300 3150 6300 3700
+Wire Wire Line
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+Wire Wire Line
+ 7100 2600 6300 2600
+Connection ~ 6300 2600
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 6300 4200 6300 4000
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 6300 4200
+$Comp
+L power:GND #PWR0101
+U 1 1 5B09125A
+P 5650 4450
+F 0 "#PWR0101" H 5650 4200 50 0001 C CNN
+F 1 "GND" H 5655 4277 50 0000 C CNN
+F 2 "" H 5650 4450 50 0001 C CNN
+F 3 "" H 5650 4450 50 0001 C CNN
+ 1 5650 4450
+ 1 0 0 -1
+$EndComp
+Connection ~ 5650 4200
+Wire Wire Line
+ 5650 4200 6300 4200
+$Comp
+L power:PWR_FLAG #FLG0101
+U 1 1 5B09135C
+P 5100 4400
+F 0 "#FLG0101" H 5100 4475 50 0001 C CNN
+F 1 "PWR_FLAG" H 5100 4574 50 0000 C CNN
+F 2 "" H 5100 4400 50 0001 C CNN
+F 3 "~" H 5100 4400 50 0001 C CNN
+ 1 5100 4400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5100 4400 5650 4400
+Wire Wire Line
+ 5650 4200 5650 4400
+Connection ~ 5650 4400
+Wire Wire Line
+ 5650 4400 5650 4450
+$EndSCHEMATC
diff --git a/analog circuits/RLC-parallel/RLC-parallel.cir b/analog circuits/RLC-parallel/RLC-parallel.cir new file mode 100644 index 0000000..ff1b87d --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel.cir @@ -0,0 +1,7 @@ +.title KiCad schematic +V1 ip GND ac 5 0 +R1 ip Net-_L1-Pad1_ 1k +L1 Net-_L1-Pad1_ GND 100m +C1 ip GND 0.1u +.ac dec 10 1 1meg +.end diff --git a/analog circuits/RLC-parallel/RLC-parallel.kicad_pcb b/analog circuits/RLC-parallel/RLC-parallel.kicad_pcb new file mode 100644 index 0000000..02c8ecb --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel.kicad_pcb @@ -0,0 +1 @@ +(kicad_pcb (version 4) (host kicad "dummy file") ) diff --git a/analog circuits/RLC-parallel/RLC-parallel.pro b/analog circuits/RLC-parallel/RLC-parallel.pro new file mode 100644 index 0000000..152769c --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel.pro @@ -0,0 +1,33 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] diff --git a/analog circuits/RLC-parallel/RLC-parallel.sch b/analog circuits/RLC-parallel/RLC-parallel.sch new file mode 100644 index 0000000..e12bb77 --- /dev/null +++ b/analog circuits/RLC-parallel/RLC-parallel.sch @@ -0,0 +1,136 @@ +EESchema Schematic File Version 4 +LIBS:RLC-parallel-cache +EELAYER 26 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L pspice:VSOURCE V1 +U 1 1 5B090E79 +P 4200 3550 +F 0 "V1" H 4428 3596 50 0000 L CNN +F 1 "VSOURCE" H 4428 3505 50 0000 L CNN +F 2 "" H 4200 3550 50 0001 C CNN +F 3 "" H 4200 3550 50 0001 C CNN +F 4 "V" H 4200 3550 50 0001 C CNN "Spice_Primitive" +F 5 "ac 5 0" H 4200 3550 50 0001 C CNN "Spice_Model" +F 6 "Y" H 4200 3550 50 0001 C CNN "Spice_Netlist_Enabled" + 1 4200 3550 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R1 +U 1 1 5B090F12 +P 6300 3000 +F 0 "R1" H 6370 3046 50 0000 L CNN +F 1 "1k" H 6370 2955 50 0000 L CNN +F 2 "" V 6230 3000 50 0001 C CNN +F 3 "~" H 6300 3000 50 0001 C CNN + 1 6300 3000 + 1 0 0 -1 +$EndComp +$Comp +L Device:L L1 +U 1 1 5B090F9F +P 6300 3850 +F 0 "L1" H 6353 3896 50 0000 L CNN +F 1 "100m" H 6353 3805 50 0000 L CNN +F 2 "" H 6300 3850 50 0001 C CNN +F 3 "~" H 6300 3850 50 0001 C CNN + 1 6300 3850 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C1 +U 1 1 5B091068 +P 7100 3350 +F 0 "C1" H 7215 3396 50 0000 L CNN +F 1 "0.1u" H 7215 3305 50 0000 L CNN +F 2 "" H 7138 3200 50 0001 C CNN +F 3 "~" H 7100 3350 50 0001 C CNN + 1 7100 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4200 3250 4200 2600 +Wire Wire Line + 4200 2600 6300 2600 +Wire Wire Line + 6300 2600 6300 2850 +Wire Wire Line + 6300 3150 6300 3700 +Wire Wire Line + 7100 3200 7100 2600 +Wire Wire Line + 7100 2600 6300 2600 +Connection ~ 6300 2600 +Wire Wire Line + 4200 3850 4200 4200 +Wire Wire Line + 4200 4200 5650 4200 +Wire Wire Line + 6300 4200 6300 4000 +Wire Wire Line + 7100 3500 7100 4200 +Wire Wire Line + 7100 4200 6300 4200 +Connection ~ 6300 4200 +$Comp +L power:GND #PWR0101 +U 1 1 5B09125A +P 5650 4450 +F 0 "#PWR0101" H 5650 4200 50 0001 C CNN +F 1 "GND" H 5655 4277 50 0000 C CNN +F 2 "" H 5650 4450 50 0001 C CNN +F 3 "" H 5650 4450 50 0001 C CNN + 1 5650 4450 + 1 0 0 -1 +$EndComp +Connection ~ 5650 4200 +Wire Wire Line + 5650 4200 6300 4200 +$Comp +L power:PWR_FLAG #FLG0101 +U 1 1 5B09135C +P 5100 4400 +F 0 "#FLG0101" H 5100 4475 50 0001 C CNN +F 1 "PWR_FLAG" H 5100 4574 50 0000 C CNN +F 2 "" H 5100 4400 50 0001 C CNN +F 3 "~" H 5100 4400 50 0001 C CNN + 1 5100 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4400 5650 4400 +Wire Wire Line + 5650 4200 5650 4400 +Connection ~ 5650 4400 +Wire Wire Line + 5650 4400 5650 4450 +Text GLabel 4100 2300 0 50 Input ~ 0 +ip +Wire Wire Line + 4100 2300 4200 2300 +Wire Wire Line + 4200 2300 4200 2600 +Connection ~ 4200 2600 +Text GLabel 6750 2150 0 50 Output ~ 0 +out +Wire Wire Line + 6750 2150 7100 2150 +Wire Wire Line + 7100 2150 7100 2600 +Connection ~ 7100 2600 +Text Notes 8700 5000 0 50 ~ 0 +.ac dec 10 1 1meg +$EndSCHEMATC |