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| author | Prashant S | 2020-04-14 10:25:32 +0530 |
|---|---|---|
| committer | GitHub | 2020-04-14 10:25:32 +0530 |
| commit | 06b09e7d29d252fb2f5a056eeb8bd1264ff6a333 (patch) | |
| tree | 2b1df110e24ff0174830d7f825f43ff1c134d1af /Linear_Integrated_Circuits_by_D_R_Choudhury | |
| parent | abb52650288b08a680335531742a7126ad0fb846 (diff) | |
| parent | 476705d693c7122d34f9b049fa79b935405c9b49 (diff) | |
| download | all-scilab-tbc-books-ipynb-master.tar.gz all-scilab-tbc-books-ipynb-master.tar.bz2 all-scilab-tbc-books-ipynb-master.zip | |
Initial commit
Diffstat (limited to 'Linear_Integrated_Circuits_by_D_R_Choudhury')
8 files changed, 256 insertions, 0 deletions
diff --git a/Linear_Integrated_Circuits_by_D_R_Choudhury/10-D_to_A_and_A_to_D_Converters.ipynb b/Linear_Integrated_Circuits_by_D_R_Choudhury/10-D_to_A_and_A_to_D_Converters.ipynb new file mode 100644 index 0000000..70e8234 --- /dev/null +++ b/Linear_Integrated_Circuits_by_D_R_Choudhury/10-D_to_A_and_A_to_D_Converters.ipynb @@ -0,0 +1,32 @@ +{ +"cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Chapter 10: D to A and A to D Converters" + ] + }, +], +"metadata": { + "kernelspec": { + "display_name": "Scilab", + "language": "scilab", + "name": "scilab" + }, + "language_info": { + "file_extension": ".sce", + "help_links": [ + { + "text": "MetaKernel Magics", + "url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md" + } + ], + "mimetype": "text/x-octave", + "name": "scilab", + "version": "0.7.1" + } + }, + "nbformat": 4, + "nbformat_minor": 0 +} diff --git a/Linear_Integrated_Circuits_by_D_R_Choudhury/2-Operational_Amplifier.ipynb b/Linear_Integrated_Circuits_by_D_R_Choudhury/2-Operational_Amplifier.ipynb new file mode 100644 index 0000000..f7e9ef3 --- /dev/null +++ b/Linear_Integrated_Circuits_by_D_R_Choudhury/2-Operational_Amplifier.ipynb @@ -0,0 +1,32 @@ +{ +"cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Chapter 2: Operational Amplifier" + ] + }, +], +"metadata": { + "kernelspec": { + "display_name": "Scilab", + "language": "scilab", + "name": "scilab" + }, + "language_info": { + "file_extension": ".sce", + "help_links": [ + { + "text": "MetaKernel Magics", + "url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md" + } + ], + "mimetype": "text/x-octave", + "name": "scilab", + "version": "0.7.1" + } + }, + "nbformat": 4, + "nbformat_minor": 0 +} diff --git a/Linear_Integrated_Circuits_by_D_R_Choudhury/3-Operational_Amplifier_Characteristics.ipynb b/Linear_Integrated_Circuits_by_D_R_Choudhury/3-Operational_Amplifier_Characteristics.ipynb new file mode 100644 index 0000000..dc4b76e --- /dev/null +++ b/Linear_Integrated_Circuits_by_D_R_Choudhury/3-Operational_Amplifier_Characteristics.ipynb @@ -0,0 +1,32 @@ +{ +"cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Chapter 3: Operational Amplifier Characteristics" + ] + }, +], +"metadata": { + "kernelspec": { + "display_name": "Scilab", + "language": "scilab", + "name": "scilab" + }, + "language_info": { + "file_extension": ".sce", + "help_links": [ + { + "text": "MetaKernel Magics", + "url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md" + } + ], + "mimetype": "text/x-octave", + "name": "scilab", + "version": "0.7.1" + } + }, + "nbformat": 4, + "nbformat_minor": 0 +} diff --git a/Linear_Integrated_Circuits_by_D_R_Choudhury/4-Operational_Amplifier_Circuits.ipynb b/Linear_Integrated_Circuits_by_D_R_Choudhury/4-Operational_Amplifier_Circuits.ipynb new file mode 100644 index 0000000..a235118 --- /dev/null +++ b/Linear_Integrated_Circuits_by_D_R_Choudhury/4-Operational_Amplifier_Circuits.ipynb @@ -0,0 +1,32 @@ +{ +"cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Chapter 4: Operational Amplifier Circuits" + ] + }, +], +"metadata": { + "kernelspec": { + "display_name": "Scilab", + "language": "scilab", + "name": "scilab" + }, + "language_info": { + "file_extension": ".sce", + "help_links": [ + { + "text": "MetaKernel Magics", + "url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md" + } + ], + "mimetype": "text/x-octave", + "name": "scilab", + "version": "0.7.1" + } + }, + "nbformat": 4, + "nbformat_minor": 0 +} diff --git a/Linear_Integrated_Circuits_by_D_R_Choudhury/5-Comparators_and_Waveform_Generators.ipynb b/Linear_Integrated_Circuits_by_D_R_Choudhury/5-Comparators_and_Waveform_Generators.ipynb new file mode 100644 index 0000000..9e93d39 --- /dev/null +++ b/Linear_Integrated_Circuits_by_D_R_Choudhury/5-Comparators_and_Waveform_Generators.ipynb @@ -0,0 +1,32 @@ +{ +"cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Chapter 5: Comparators and Waveform Generators" + ] + }, +], +"metadata": { + "kernelspec": { + "display_name": "Scilab", + "language": "scilab", + "name": "scilab" + }, + "language_info": { + "file_extension": ".sce", + "help_links": [ + { + "text": "MetaKernel Magics", + "url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md" + } + ], + "mimetype": "text/x-octave", + "name": "scilab", + "version": "0.7.1" + } + }, + "nbformat": 4, + "nbformat_minor": 0 +} diff --git a/Linear_Integrated_Circuits_by_D_R_Choudhury/6-Voltage_Regulator.ipynb b/Linear_Integrated_Circuits_by_D_R_Choudhury/6-Voltage_Regulator.ipynb new file mode 100644 index 0000000..e785a23 --- /dev/null +++ b/Linear_Integrated_Circuits_by_D_R_Choudhury/6-Voltage_Regulator.ipynb @@ -0,0 +1,32 @@ +{ +"cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Chapter 6: Voltage Regulator" + ] + }, +], +"metadata": { + "kernelspec": { + "display_name": "Scilab", + "language": "scilab", + "name": "scilab" + }, + "language_info": { + "file_extension": ".sce", + "help_links": [ + { + "text": "MetaKernel Magics", + "url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md" + } + ], + "mimetype": "text/x-octave", + "name": "scilab", + "version": "0.7.1" + } + }, + "nbformat": 4, + "nbformat_minor": 0 +} diff --git a/Linear_Integrated_Circuits_by_D_R_Choudhury/7-Active_Filters.ipynb b/Linear_Integrated_Circuits_by_D_R_Choudhury/7-Active_Filters.ipynb new file mode 100644 index 0000000..cb18fa6 --- /dev/null +++ b/Linear_Integrated_Circuits_by_D_R_Choudhury/7-Active_Filters.ipynb @@ -0,0 +1,32 @@ +{ +"cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Chapter 7: Active Filters" + ] + }, +], +"metadata": { + "kernelspec": { + "display_name": "Scilab", + "language": "scilab", + "name": "scilab" + }, + "language_info": { + "file_extension": ".sce", + "help_links": [ + { + "text": "MetaKernel Magics", + "url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md" + } + ], + "mimetype": "text/x-octave", + "name": "scilab", + "version": "0.7.1" + } + }, + "nbformat": 4, + "nbformat_minor": 0 +} diff --git a/Linear_Integrated_Circuits_by_D_R_Choudhury/8-555_Timer.ipynb b/Linear_Integrated_Circuits_by_D_R_Choudhury/8-555_Timer.ipynb new file mode 100644 index 0000000..eab1457 --- /dev/null +++ b/Linear_Integrated_Circuits_by_D_R_Choudhury/8-555_Timer.ipynb @@ -0,0 +1,32 @@ +{ +"cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Chapter 8: 555 Timer" + ] + }, +], +"metadata": { + "kernelspec": { + "display_name": "Scilab", + "language": "scilab", + "name": "scilab" + }, + "language_info": { + "file_extension": ".sce", + "help_links": [ + { + "text": "MetaKernel Magics", + "url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md" + } + ], + "mimetype": "text/x-octave", + "name": "scilab", + "version": "0.7.1" + } + }, + "nbformat": 4, + "nbformat_minor": 0 +} |