summaryrefslogtreecommitdiff
path: root/2.3-1/src/c/hardware/avr/uart/u8AVRUARTSetups.c
blob: 085ac6e38e0455f18465ffbed8a9f66bd12308af (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
/* Copyright (C) 2016 - IIT Bombay - FOSSEE

 This file must be used under the terms of the CeCILL.
 This source file is licensed as described in the file COPYING, which
 you should have received as part of this distribution.  The terms
 are also available at
 http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt
 Author: Ashish Kamble
 Organization: FOSSEE, IIT Bombay
 Email: toolbox@scilab.in
*/ 
//Function to Setup Serial communication for ATmega16.


#include "AVRPeripheralUART.h"

uint8 u8AVRUARTSetups(uint8 mode, uint32 baudrate, uint8 stopbits, uint8 parity)
{
//Enable UART and USART
 UCSRC |= (1<<URSEL);
 UCSRB |= (1<<TXEN)|(1<<RXEN);

 switch (mode) //According to mode set bits UMSEL and U2X
{
 case 0: //Normal mode
        UCSRC &= ~(1<<UMSEL);  //Clear bit 6 UMSEL and  U2X=0
	UCSRA &= ~(1<<U2X);
	UCSRC &= ~(1<<UCPOL);  // Clock polarity bit
	break;

 case 1: //Double speed mode
	UCSRC &= ~(1<<UMSEL); //Clear bit 6 UMSEL and U2X=1
	UCSRA |= (1<<U2X);
	UCSRC &= ~(1<<UCPOL);  //Clock polarity bit
	break;
		
 case 2: //Synchronous mode
	UCSRC |= (1<<UMSEL);  //Set bit 6 UMSEL and set clock polarity
	UCSRC |= (1<<UCPOL);
	break;
}

//Set stop bits
if(stopbits == 0)
{   
 UCSRC &= ~(1<<USBS);      // 1 stopbit
}
else UCSRC |= (1<<USBS);   //2 stopbits

//Set parity bit settings
switch(parity)
{
 case 0: // Parity disabled
	UCSRC &= ~(1<<UPM1);	//UPM1:0=0
	UCSRC &= ~(1<<UPM0);
	break;

 case 1: // Even parity
	UCSRC |= (1<<UPM1);    //UPM1:0 = 2
	UCSRC &= ~(1<<UPM0);
	break;

 case 2: // Odd parity
	UCSRC |= (1<<UPM1);    //UPM1:1 = 3
	UCSRC |= (1<<UPM0);
	break;
}

//Set baudrate
UCSRC &= ~(1<<URSEL);
switch(baudrate)
{
 case 2400:
	   UBRRL = 0xA0;
           UBRRH = 0x01;
           break;

 case 4800:
	   UBRRL = 0xCF;
	   UBRRH = 0x00;
           break;

 case 9600:
	   UBRRL = 0x67;
	   UBRRH = 0x00;
           break;

 case 14400:
	    UBRRL = 0x44;
	    UBRRH = 0x00;
	    break;

 case 19200:
	    UBRRL = 0x33;
	    UBRRH = 0x00;
	    break;

 case 28800:
	    UBRRL = 0x22;
	    UBRRH = 0x00;
	    break;

 case 38400:
	    UBRRL = 0x19;
            UBRRH = 0x00;
	    break;

 case 57600:
	    UBRRL = 0x10;
            UBRRH = 0x00;
	    break;    	
 
 case 768000:
	     UBRRL = 0x0C;
             UBRRH = 0x00;
	     break;    	

 case 115200:
 	     UBRRL = 0x08;
             UBRRH = 0x00;
	     break;
    	
 case 230400:
	     UBRRL = 0x03;
	     UBRRH = 0x00;
	     break;
    	
 case 250000:
	     UBRRL = 0x03;
	     UBRRH = 0x00;
	     break;

 case 1000000:
	      UBRRL = 0x00;
	      UBRRH = 0x00;
	      break; 
}

//Set data format
UCSRC|= (1<<URSEL)|(1<<UCSZ0)|(1<<UCSZ1);  

 return 0;
}