8 files changed, 328 insertions, 0 deletions
diff --git a/506/CH16/EX16.1/Example16_1.sce b/506/CH16/EX16.1/Example16_1.sce
new file mode 100755
index 000000000..3ed01bcd2
--- /dev/null
+++ b/506/CH16/EX16.1/Example16_1.sce
@@ -0,0 +1,30 @@
+clear;
+clc;
+
+//Caption:Fourth Order Butterworth Filter
+//Given Data
+fo=1;//Cutoff Frequency in Hz
+//For n = 4
+k1=0.765;
+k2=1.848;
+
+Av1 = 3-k1;
+Av2 = 3-k2;
+disp('For a fourth order Buttworth filter we cacade 2 second order Buttworth filter with parameters R1 R2 R1d R2d R C');
+//we arbitrarily choose
+R1=10;//in K
+disp('K',R1,'R1=');
+//Av1=(R1+R1d)/R1
+R1d=(Av1*R1)-R1;
+disp(R1d,'R1d = ');
+
+R2 = 10;//in K
+disp('K',R2,'R2=');
+R2d=(Av2*R2)-R2;
+disp(R2d,'R2d = ');
+
+//To satisfy fo = 1/(2*%pi*r*c) = 1kHz
+R=1;//in K
+C = 1/(2*%pi*R*fo);
+disp('K',R,'R=');
+disp('microF',C,'C = ');
diff --git a/506/CH16/EX16.2/Example16_2.sce b/506/CH16/EX16.2/Example16_2.sce
new file mode 100755
index 000000000..59030a4ec
--- /dev/null
+++ b/506/CH16/EX16.2/Example16_2.sce
@@ -0,0 +1,26 @@
+clear;
+clc;
+//Caption : Design a second order bandpass filter
+//Given Value
+Ao=50;//Gain
+fo=160;//center frequency
+B=16;//Bandwidth in Hz
+C1=0.1;//in microF
+C2=0.1;//in microF
+
+//Required Formulae
+
+Q=fo/B;
+R1=(1000*Q)/(Ao*2*%pi*fo*C1);
+R3=(1000*Q)/((2*%pi*fo)*(C1*C2/(C1+C2)));
+//As C is in microFarad to compensate for it 1000 is multiplied
+//Let r = R'
+r=(10^6)/((2*%pi*fo)^2*R3*C1*C2);
+R2=(R1*r)/(R1-r);
+
+disp('K',R1,'R1=');
+disp('K',R3,'R3=');
+disp('K',r,'r=');
+disp('K',R2,'R2=');
+
+//end
+\ No newline at end of file
diff --git a/506/CH16/EX16.3/Example16_3.sce b/506/CH16/EX16.3/Example16_3.sce
new file mode 100755
index 000000000..c6f1c8ba3
--- /dev/null
+++ b/506/CH16/EX16.3/Example16_3.sce
@@ -0,0 +1,47 @@
+clear;
+clc;
+
+//Caption:Design a video amplifier using MC1550
+//Given Data
+Avo=-25;
+Vagc=20;//in V
+Vcc=6;//in V
+hfe=50;
+rbb=50;//in ohm
+Cs=5;//in pF
+Cl=5;//in pF
+Ie1=1;//in mA
+ft=900;//in MHz
+Vt=26;//in V
+n=2;//eeta
+//re2 = infinity
+
+//Since Vagc=0 , transistor Q2 is in cut off region and collector current of Q1 flows through Q3....So
+Ie2=0;
+Ie3=1;//in mA
+re3 = (n*Vt)/Ie3;//in ohm
+disp('ohm',re3,'re3=');
+gm = (Ie1)/Vt;//in ohm^-1
+disp('ohm^-1',gm,'gm=');
+rbe=hfe/gm;
+disp('ohm',rbe,'rbe=');
+Ce=gm/(2*%pi*ft*10^-6);
+disp('pF',Ce,'Ce=');
+a3=1;//we make an assumption that alpha is one
+s=0;
+//Av0 = -((a3*gm)/(re3*rbb))*(1/(((1/rbb)+(1/rbe)+(s*Ce))*((1/re3)+(s*Cs))*((1/Rl)+(s*(Cs+Cl)))))
+//From here we can find Rl
+k = -((a3*gm)/(re3*rbb))*(1/(((1/rbb)+(1/rbe)+(s*Ce))*((1/re3)+(s*Cs))));
+Rl=Avo/k;
+disp('ohm',Rl,'Rl=');
+
+//C is in picoFarad so to compensate the whole equation some constants are multiplied
+f1 = 1/(2*%pi*Rl*(Cs+Cl)*10^-6);
+disp('MHz',f1,'f1=');
+f2 = 1/(2*%pi*Ce*10^-6*((rbe*rbb)/(rbe+rbb)));
+disp('MHz',f2,'f2=');
+f3 = 1/(2*%pi*Cs*re3*10^-6);
+disp('MHz',f3,'f3=');
+
+
+//end
+\ No newline at end of file
diff --git a/506/CH16/EX16.4.a/Example16_4a.sce b/506/CH16/EX16.4.a/Example16_4a.sce
new file mode 100755
index 000000000..da7a02d99
--- /dev/null
+++ b/506/CH16/EX16.4.a/Example16_4a.sce
@@ -0,0 +1,43 @@
+clear;
+clc;
+
+//Caption:Logic Level Output of an ECL gate
+//Given Data
+Vbb = 1.15;//in V
+Vee=5.20;//in V
+Vbe5=0.7;//in V
+R=1.18;//in K
+r=300;//in ohm
+Vbecutin=0.5;//in V
+
+//If all inputs are low then we assume that Q1,Q2 and Q3 are cutoff and Q4 is conducting
+Ve=-Vbb-Vbe5;//Voltage at Common Emitter in V
+//Current I in 1.18K Resistor
+I = (Ve+Vee)/R;//in mA
+I1=I;
+disp('mA',I,'Current in 300 ohm resistance I=');
+//Output Voltage at Y
+vy = -(r*I/1000)-Vbe5;//I is in mA so 1000 is multiplied
+Vbe = vy-Ve;
+disp('V',Vbe,'Vbe = ');
+if(Vbe<Vbecutin)
+    disp('Input transistors are non conducting as was assumed');
+    disp('If atleast one input is high then it is assumed that curent in 1.18K resistance is switched to R and Q4 is cutoff');
+    disp('Drop in 300 ohm resistance is zero.Since the base aand collector are tied together Q5 now behaves as a diode');
+    disp('Across Q5');
+    v=0.7;//voltage across Q5 in V
+    rQ5 = 1.5;//in K
+    i = (Vee-v)/rQ5;
+    v = 0.75;//from the graph in V
+    disp('mA',i,'i=');
+    disp('V',v,'v=');
+    Ve = -v-Vbe5;
+    Vbe4=-Vbb-Ve;
+    disp('V',Vbe4,'Vbe4=');
+end
+disp('The total output swing between two logic gates');
+vo = -vy-v;
+disp('V',vo,'vo=');
+
+
+//end
+\ No newline at end of file
diff --git a/506/CH16/EX16.4.b/Example16_4b.sce b/506/CH16/EX16.4.b/Example16_4b.sce
new file mode 100755
index 000000000..582f0d24b
--- /dev/null
+++ b/506/CH16/EX16.4.b/Example16_4b.sce
@@ -0,0 +1,36 @@
+clear;
+clc;
+
+//Calculation of noise margin
+//Given Data
+Vbb = 1.15;//in V
+Vee=5.20;//in V
+Vbe5=0.7;//in V
+R=1.18;//in K
+r=300;//in ohm
+Vbecutin=0.5;//in V
+
+//If all inputs are low then we assume that Q1,Q2 and Q3 are cutoff and Q4 is conducting
+Ve=-Vbb-Vbe5;//Voltage at Common Emitter in V
+//Current I in 1.18K Resistor
+I = (Ve+Vee)/R;//in mA
+I1=I;
+//Output Voltage at Y
+vy = -(r*I/1000)-Vbe5;//I is in mA so 1000 is multiplied
+Vbe = vy-Ve;
+if(Vbe<Vbecutin)
+    v=0.7;//voltage across Q5 in V
+    rQ5 = 1.5;//in K
+    i = (Vee-v)/rQ5;
+    v = 0.75;//from the graph in V
+    Ve = -v-Vbe5;
+    Vbe4=-Vbb-Ve;
+end
+vo = -vy-v;
+
+//Calculation of noise margin
+vn = Vbecutin-Vbe4;
+disp('Positive noise spike which will cause the gate to malfunction');
+disp('V',vn,'vn=');
+
+//end
+\ No newline at end of file
diff --git a/506/CH16/EX16.4.c/Example16_4c.sce b/506/CH16/EX16.4.c/Example16_4c.sce
new file mode 100755
index 000000000..1382ac6fb
--- /dev/null
+++ b/506/CH16/EX16.4.c/Example16_4c.sce
@@ -0,0 +1,47 @@
+clear;
+clc;
+
+//Verify that conducting transistor is in active region
+//Given Data
+Vbb = 1.15;//in V
+Vee=5.20;//in V
+Vbe5=0.7;//in V
+R=1.18;//in K
+r=300;//in ohm
+Vbecutin=0.5;//in V
+
+//If all inputs are low then we assume that Q1,Q2 and Q3 are cutoff and Q4 is conducting
+Ve=-Vbb-Vbe5;//Voltage at Common Emitter in V
+//Current I in 1.18K Resistor
+I = (Ve+Vee)/R;//in mA
+I1=I;
+//Output Voltage at Y
+vy = -(r*I/1000)-Vbe5;//I is in mA so 1000 is multiplied
+Vbe = vy-Ve;
+if(Vbe<Vbecutin)
+    v=0.7;//voltage across Q5 in V
+    rQ5 = 1.5;//in K
+    i = (Vee-v)/rQ5;
+    v = 0.75;//from the graph in V
+    Ve = -v-Vbe5;
+    Vbe4=-Vbb-Ve;
+end
+vo = -vy-v;
+
+Vb4 = Vbb;
+Vc4 = -(I*r)/1000;//in V
+Vcb4 = Vc4+Vb4;
+disp('V',Vcb4,'Vcb4 = ');
+if(Vcb4>0)
+    disp('For on npn transistor this represents a reverse bias and Q4 must be in active region');
+end
+Vb1 = v;
+Vc1 = vy+Vbe5;
+Vcb1 = Vc1 + Vb1;
+disp('V',Vc1,'Vc1=');
+disp('V',Vcb1,'Vcb1=');
+if(Vcb1<0)
+    disp('For an npn transistor this represents a forward bias.... therefore Q1 is in saturation region');
+    end
+
+//end
+\ No newline at end of file
diff --git a/506/CH16/EX16.4.d/Example16_4d.sce b/506/CH16/EX16.4.d/Example16_4d.sce
new file mode 100755
index 000000000..589aed8e5
--- /dev/null
+++ b/506/CH16/EX16.4.d/Example16_4d.sce
@@ -0,0 +1,47 @@
+clear;
+clc;
+
+//Calculation of R
+//Given Data
+Vbb = 1.15;//in V
+Vee=5.20;//in V
+Vbe5=0.7;//in V
+R=1.18;//in K
+r=300;//in ohm
+Vbecutin=0.5;//in V
+
+//If all inputs are low then we assume that Q1,Q2 and Q3 are cutoff and Q4 is conducting
+Ve=-Vbb-Vbe5;//Voltage at Common Emitter in V
+//Current I in 1.18K Resistor
+I = (Ve+Vee)/R;//in mA
+I1=I;
+//Output Voltage at Y
+vy = -(r*I/1000)-Vbe5;//I is in mA so 1000 is multiplied
+Vbe = vy-Ve;
+if(Vbe<Vbecutin)
+    v=0.7;//voltage across Q5 in V
+    rQ5 = 1.5;//in K
+    i = (Vee-v)/rQ5;
+    v = 0.75;//from the graph in V
+    Ve = -v-Vbe5;
+    Vbe4=-Vbb-Ve;
+end
+vo = -vy-v;
+
+//Verify that conducting transistor is in active region
+Vb4 = Vbb;
+Vc4 = -(I*r)/1000;//in V
+Vcb4 = Vc4+Vb4;
+Vb1 = v;
+Vc1 = vy+Vbe5;
+Vcb1 = Vc1 + Vb1;
+
+Vbe1 = Vbe5;
+Ve = -(Vb1+Vbe1);
+disp('V',Ve,'Ve=');
+I = (Ve + Vee)/R;
+I2=I;
+R = -Vc1/I;
+disp('ohm',R,'R=');
+
+//end
+\ No newline at end of file
diff --git a/506/CH16/EX16.4.e/Example16_4e.sce b/506/CH16/EX16.4.e/Example16_4e.sce
new file mode 100755
index 000000000..f74e6ace1
--- /dev/null
+++ b/506/CH16/EX16.4.e/Example16_4e.sce
@@ -0,0 +1,52 @@
+clear;
+clc;
+
+//Average power dissipated by the gate
+//Given Data
+Vbb = 1.15;//in V
+Vee=5.20;//in V
+Vbe5=0.7;//in V
+R=1.18;//in K
+r=300;//in ohm
+Vbecutin=0.5;//in V
+
+//If all inputs are low then we assume that Q1,Q2 and Q3 are cutoff and Q4 is conducting
+Ve=-Vbb-Vbe5;//Voltage at Common Emitter in V
+//Current I in 1.18K Resistor
+I = (Ve+Vee)/R;//in mA
+I1=I;
+//Output Voltage at Y
+vy = -(r*I/1000)-Vbe5;//I is in mA so 1000 is multiplied
+Vbe = vy-Ve;
+if(Vbe<Vbecutin)
+    v=0.7;//voltage across Q5 in V
+    rQ5 = 1.5;//in K
+    i = (Vee-v)/rQ5;
+    v = 0.75;//from the graph in V
+    Ve = -v-Vbe5;
+    Vbe4=-Vbb-Ve;
+end
+
+vo = -vy-v;
+
+Vb4 = Vbb;
+Vc4 = -(I*r)/1000;//in V
+Vcb4 = Vc4+Vb4;
+Vb1 = v;
+Vc1 = vy+Vbe5;
+Vcb1 = Vc1 + Vb1;
+
+Vbe1 = Vbe5;
+Ve = -(Vb1+Vbe1);
+I = (Ve + Vee)/R;
+I2=I;
+
+I =(I1+I2)/2;
+disp('mA',I,'I=');
+I2 = (Vee-v)/rQ5;
+I3 = (Vee+vy)/rQ5;
+I = I + I2 + I3;
+P = Vee*I;
+disp('mW',P,'Power dissipated = ');
+
+//end
+\ No newline at end of file