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authorprashantsinalkar2017-10-10 12:27:19 +0530
committerprashantsinalkar2017-10-10 12:27:19 +0530
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+//example 3.4//
+clc
+//clears the screen//
+clear
+//clears all existing variables//
+disp('In case of OR gate. Y=A + A'', this will always result in output as 1.') \ No newline at end of file