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| author | priyanka | 2015-06-24 15:03:17 +0530 |
|---|---|---|
| committer | priyanka | 2015-06-24 15:03:17 +0530 |
| commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
| tree | ab291cffc65280e58ac82470ba63fbcca7805165 /462/CH1/EX1.7.b/ex_1_7_b.sce | |
| download | Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.gz Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.bz2 Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.zip | |
initial commit / add all books
Diffstat (limited to '462/CH1/EX1.7.b/ex_1_7_b.sce')
| -rwxr-xr-x | 462/CH1/EX1.7.b/ex_1_7_b.sce | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/462/CH1/EX1.7.b/ex_1_7_b.sce b/462/CH1/EX1.7.b/ex_1_7_b.sce new file mode 100755 index 000000000..41512b770 --- /dev/null +++ b/462/CH1/EX1.7.b/ex_1_7_b.sce @@ -0,0 +1,7 @@ +//example 1.7(b)//
+clc
+//clears the screen//
+clear
+//clears already existing variables//
+disp('when one of the logic input of 2-input NAND gate is 1, then when A=1, Y=0 and if A=0, Y=1')
+disp('Y=A''')
\ No newline at end of file |