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| author | priyanka | 2015-06-24 15:03:17 +0530 |
|---|---|---|
| committer | priyanka | 2015-06-24 15:03:17 +0530 |
| commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
| tree | ab291cffc65280e58ac82470ba63fbcca7805165 /275/CH4/EX4.4.77/Ch4_4_77.sce | |
| download | Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.gz Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.bz2 Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.zip | |
initial commit / add all books
Diffstat (limited to '275/CH4/EX4.4.77/Ch4_4_77.sce')
| -rwxr-xr-x | 275/CH4/EX4.4.77/Ch4_4_77.sce | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/275/CH4/EX4.4.77/Ch4_4_77.sce b/275/CH4/EX4.4.77/Ch4_4_77.sce new file mode 100755 index 000000000..8ab28c5e0 --- /dev/null +++ b/275/CH4/EX4.4.77/Ch4_4_77.sce @@ -0,0 +1,28 @@ +clc
+disp("Example 4.77")
+printf("\n")
+disp("calculate Vds at these gate_source voltages & circuit voltage gain of JFET")
+printf("Given\n")
+//drain current
+Id=9*10^-3
+//gate to source voltage
+Vgs=(-2)
+//when Vgs is reduced to -1V then Id is 12mA
+Vgs1=-1
+Id1=12*10^-3
+//from circuit (fig 4.49)
+Rd=1.5*10^3
+Vdd=20
+//to find Vds
+//when Vgs=-2
+Vds=Vdd-(Id*Rd)
+//when Vgs=-1
+Vds1=Vdd-(Id1*Rd)
+//change in input voltage Vgs is
+delVi=Vgs1-Vgs
+//change in output voltage is
+delVo=Vds-Vds1
+//Voltage gain
+Av=delVo/delVi
+printf("The value of Vds at gate-source voltages is \n%f volt\n",Vds)
+printf("The circuit voltage gain \n%f\n",Av)
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