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| author | prashantsinalkar | 2017-10-10 12:38:01 +0530 |
|---|---|---|
| committer | prashantsinalkar | 2017-10-10 12:38:01 +0530 |
| commit | f35ea80659b6a49d1bb2ce1d7d002583f3f40947 (patch) | |
| tree | eb72842d800ac1233e9d890e020eac5fd41b0b1b /275/CH3/EX3.3.74/Ch3_3_74.sce | |
| parent | 7f60ea012dd2524dae921a2a35adbf7ef21f2bb6 (diff) | |
| download | Scilab-TBC-Uploads-f35ea80659b6a49d1bb2ce1d7d002583f3f40947.tar.gz Scilab-TBC-Uploads-f35ea80659b6a49d1bb2ce1d7d002583f3f40947.tar.bz2 Scilab-TBC-Uploads-f35ea80659b6a49d1bb2ce1d7d002583f3f40947.zip | |
updated the code
Diffstat (limited to '275/CH3/EX3.3.74/Ch3_3_74.sce')
| -rwxr-xr-x | 275/CH3/EX3.3.74/Ch3_3_74.sce | 74 |
1 files changed, 37 insertions, 37 deletions
diff --git a/275/CH3/EX3.3.74/Ch3_3_74.sce b/275/CH3/EX3.3.74/Ch3_3_74.sce index a34f72ed9..14d3180c5 100755 --- a/275/CH3/EX3.3.74/Ch3_3_74.sce +++ b/275/CH3/EX3.3.74/Ch3_3_74.sce @@ -1,38 +1,38 @@ -clc
-disp("Example 3.74")
-printf("\n")
-disp("Find the Ve, Ic,Vce & Vc. Draw a DC load line for Voltage divider circuit")
-printf("Given\n")
-//given
-Vcc=15
-Vbe=0.7
-hFE=50
-R1=6.8*10^3
-R2=3.3*10^3
-Rc=0.9*10^3
-Re=0.9*10^3
-//thevenin voltage
-Vt=(Vcc*R2)/(R1+R2)
-//thevenin resistance
-Rt=(R1*R2)/(R1+R2)
-//base current
-Ib=(Vt-Vbe)/(Rt+(1+hFE)*Re)
-//collector current
-Icq=hFE*Ib
-//emitter current
-Ie=Ib+Icq
-//emitter voltage
-Ve=Ie*Re
-//collector to emitter voltage
-Vceq=Vcc-(Icq*Rc)-(Ie*Re)
-//collector voltage
-Vc=Vce+Ve
-//to draw DC load line
-Ic1=Vcc/(Rc+Re)
-Vce=[Vcc Vceq 0]
-Ic=[0 Icq Ic1]
-printf("Q(%f,%f)\n",Vceq,Icq)
-plot2d(Vce, Ic)
-xlabel("Vce")
-ylabel("Ic")
+clc +disp("Example 3.74") +printf("\n") +disp("Find the Ve, Ic,Vce & Vc. Draw a DC load line for Voltage divider circuit") +printf("Given\n") +//given +Vcc=15 +Vbe=0.7 +hFE=50 +R1=6.8*10^3 +R2=3.3*10^3 +Rc=0.9*10^3 +Re=0.9*10^3 +//thevenin voltage +Vt=(Vcc*R2)/(R1+R2) +//thevenin resistance +Rt=(R1*R2)/(R1+R2) +//base current +Ib=(Vt-Vbe)/(Rt+(1+hFE)*Re) +//collector current +Icq=hFE*Ib +//emitter current +Ie=Ib+Icq +//emitter voltage +Ve=Ie*Re +//collector to emitter voltage +Vceq=Vcc-(Icq*Rc)-(Ie*Re); +Vce=[Vcc Vceq 0]; +//collector voltage +Vc=Vce+Ve +//to draw DC load line +Ic1=Vcc/(Rc+Re) +Ic=[0 Icq Ic1] +printf("Q(%f,%f)\n",Vceq,Icq) +plot2d(Vce, Ic) +xlabel("Vce") +ylabel("Ic") xtitle("DC load line for base bias circuit")
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