updated the code

4 files changed, 130 insertions, 130 deletions

diff --git a/275/CH3/EX3.3.55/Ch3_3_55.sce b/275/CH3/EX3.3.55/Ch3_3_55.sce
index 351c6d536..a5f63195e 100755
--- a/275/CH3/EX3.3.55/Ch3_3_55.sce
+++ b/275/CH3/EX3.3.55/Ch3_3_55.sce
@@ -1,22 +1,22 @@
-clc

-disp("Example 3.55")

-printf("\n")

-disp("Calculate transistor hFE & new Vce level for hFE=100 of base bias ciruit")

-printf("Given\n")

-//given

-Vcc=24

-Rb=390*10^3

-Rc=3.3*10^3

-Vce=10

-//Find Ic

-Ic=(Vcc-Vce)/Rc  //from circuit

-//find Ib

-Ib=(Vcc-Vbe)/Rb  //from ciruit

-//the value of hFE

-hFE=Ic/Ib

-//to find Vce when hFE=100

-hFE1=100

-Ic1=hFE1*Ib

-Vce1=Vcc-(Ic1*Rc)

-printf("Value of hFE is \n%f\n",hFE)

-printf("New value of Vce is \n%f volt\n",Vce1)

+clc
+disp("Example 3.55")
+printf("\n")
+disp("Calculate transistor hFE & new Vce level for hFE=100 of base bias ciruit")
+printf("Given\n")
+//given
+Vcc=24
+Rb=390*10^3
+Rc=3.3*10^3
+Vce=10
+//Find Ic
+Ic=(Vcc-Vce)/Rc  //from circuit
+//find Ib
+Ib=(Vcc-Vce)/Rb  //from ciruit
+//the value of hFE
+hFE=Ic/Ib
+//to find Vce when hFE=100
+hFE1=100
+Ic1=hFE1*Ib
+Vce1=Vcc-(Ic1*Rc)
+printf("Value of hFE is \n%f\n",hFE)
+printf("New value of Vce is \n%f volt\n",Vce1)
\ No newline at end of file
diff --git a/275/CH3/EX3.3.72/Ch3_3_72.sce b/275/CH3/EX3.3.72/Ch3_3_72.sce
index 9b7b82e98..08b7c9129 100755
--- a/275/CH3/EX3.3.72/Ch3_3_72.sce
+++ b/275/CH3/EX3.3.72/Ch3_3_72.sce
@@ -1,33 +1,33 @@
-clc

-disp("Example 3.72")

-printf("\n")

-disp("Draw a DC load line for Voltage divider circuit")

-printf("Given\n")

-//given

-Vcc=15

-Rc=2.7*10^3

-Re=2.2*10^3

-R1=22*10^3

-R2=12*10^3

-Vbe=0.7

-//base voltage

-Vb=(Vcc*R2)/(R1+R2)

-//emitter voltage

-Ve=Vb-Vbe

-//emitter current

-Ie=Ve/Re

-//collector current

-Icq=Ie

-//collector to emitter voltage

-Vceq=Vcc-(Icq*(Rc+Re))

-//collector voltage

-Vc=Vce+Ve

-//to draw DC load line

-Ic1=Vcc/(Rc+Re)

-Vce=[Vcc Vceq 0]

-Ic=[0 Icq Ic1]

-printf("Q(%f volt,%f ampere)\n",Vceq,Icq)

-plot2d(Vce, Ic)

-xlabel("Vce in volt")

-ylabel("Ic in ampere")

-xtitle("DC load line for base bias circuit")

+clc
+disp("Example 3.72")
+printf("\n")
+disp("Draw a DC load line for Voltage divider circuit")
+printf("Given\n")
+//given
+Vcc=15
+Rc=2.7*10^3
+Re=2.2*10^3
+R1=22*10^3
+R2=12*10^3
+Vbe=0.7
+//base voltage
+Vb=(Vcc*R2)/(R1+R2)
+//emitter voltage
+Ve=Vb-Vbe
+//emitter current
+Ie=Ve/Re
+//collector current
+Icq=Ie
+//collector to emitter voltage
+Vceq=Vcc-(Icq*(Rc+Re));
+Vce=[Vcc Vceq 0];
+//collector voltage
+Vc=Vce+Ve
+//to draw DC load line
+Ic1=Vcc/(Rc+Re)
+Ic=[0 Icq Ic1]
+printf("Q(%f volt,%f ampere)\n",Vceq,Icq)
+plot2d(Vce, Ic)
+xlabel("Vce in volt")
+ylabel("Ic in ampere")
+xtitle("DC load line for base bias circuit")
\ No newline at end of file
diff --git a/275/CH3/EX3.3.73/Ch3_3_73.sce b/275/CH3/EX3.3.73/Ch3_3_73.sce
index 1b299caa6..c2a961817 100755
--- a/275/CH3/EX3.3.73/Ch3_3_73.sce
+++ b/275/CH3/EX3.3.73/Ch3_3_73.sce
@@ -1,38 +1,38 @@
-clc

-disp("Example 3.73")

-printf("\n")

-disp("Find the Ve, Ic,Vce & Vc. Draw a DC load line for Voltage divider circuit")

-printf("Given\n")

-//given

-Vcc=18

-Vbe=0.7

-hFE=50

-R1=33*10^3

-R2=12*10^3

-Rc=1.2*10^3

-Re=10^3

-//thevenin voltage

-Vt=(Vcc*R2)/(R1+R2)

-//thevenin resistance

-Rt=(R1*R2)/(R1+R2)

-//base current

-Ib=(Vt-Vbe)/(Rt+(1+hFE)*Re)

-//collector current

-Icq=hFE*Ib

-//emitter current

-Ie=Ib+Icq

-//emitter voltage

-Ve=Ie*Re

-//collector to emitter voltage

-Vceq=Vcc-(Icq*Rc)-(Ie*Re)

-//collector voltage

-Vc=Vce+Ve

-//to draw DC load line

-Ic1=Vcc/(Rc+Re)

-Vce=[Vcc Vceq 0]

-Ic=[0 Icq Ic1]

-printf("Q(%f volt,%f ampere)\n",Vceq,Icq)

-plot2d(Vce, Ic)

-xlabel("Vce in volt")

-ylabel("Ic in ampere")

-xtitle("DC load line for base bias circuit")

+clc
+disp("Example 3.73")
+printf("\n")
+disp("Find the Ve, Ic,Vce & Vc. Draw a DC load line for Voltage divider circuit")
+printf("Given\n")
+//given
+Vcc=18
+Vbe=0.7
+hFE=50
+R1=33*10^3
+R2=12*10^3
+Rc=1.2*10^3
+Re=10^3
+//thevenin voltage
+Vt=(Vcc*R2)/(R1+R2)
+//thevenin resistance
+Rt=(R1*R2)/(R1+R2)
+//base current
+Ib=(Vt-Vbe)/(Rt+(1+hFE)*Re)
+//collector current
+Icq=hFE*Ib
+//emitter current
+Ie=Ib+Icq
+//emitter voltage
+Ve=Ie*Re
+//collector to emitter voltage
+Vceq=Vcc-(Icq*Rc)-(Ie*Re);
+Vce=[Vcc Vceq 0];
+//collector voltage
+Vc=Vce+Ve
+//to draw DC load line
+Ic1=Vcc/(Rc+Re)
+Ic=[0 Icq Ic1]
+printf("Q(%f volt,%f ampere)\n",Vceq,Icq)
+plot2d(Vce, Ic)
+xlabel("Vce in volt")
+ylabel("Ic in ampere")
+xtitle("DC load line for base bias circuit")
\ No newline at end of file
diff --git a/275/CH3/EX3.3.74/Ch3_3_74.sce b/275/CH3/EX3.3.74/Ch3_3_74.sce
index a34f72ed9..14d3180c5 100755
--- a/275/CH3/EX3.3.74/Ch3_3_74.sce
+++ b/275/CH3/EX3.3.74/Ch3_3_74.sce
@@ -1,38 +1,38 @@
-clc

-disp("Example 3.74")

-printf("\n")

-disp("Find the Ve, Ic,Vce & Vc. Draw a DC load line for Voltage divider circuit")

-printf("Given\n")

-//given

-Vcc=15

-Vbe=0.7

-hFE=50

-R1=6.8*10^3

-R2=3.3*10^3

-Rc=0.9*10^3

-Re=0.9*10^3

-//thevenin voltage

-Vt=(Vcc*R2)/(R1+R2)

-//thevenin resistance

-Rt=(R1*R2)/(R1+R2)

-//base current

-Ib=(Vt-Vbe)/(Rt+(1+hFE)*Re)

-//collector current

-Icq=hFE*Ib

-//emitter current

-Ie=Ib+Icq

-//emitter voltage

-Ve=Ie*Re

-//collector to emitter voltage

-Vceq=Vcc-(Icq*Rc)-(Ie*Re)

-//collector voltage

-Vc=Vce+Ve

-//to draw DC load line

-Ic1=Vcc/(Rc+Re)

-Vce=[Vcc Vceq 0]

-Ic=[0 Icq Ic1]

-printf("Q(%f,%f)\n",Vceq,Icq)

-plot2d(Vce, Ic)

-xlabel("Vce")

-ylabel("Ic")

+clc
+disp("Example 3.74")
+printf("\n")
+disp("Find the Ve, Ic,Vce & Vc. Draw a DC load line for Voltage divider circuit")
+printf("Given\n")
+//given
+Vcc=15
+Vbe=0.7
+hFE=50
+R1=6.8*10^3
+R2=3.3*10^3
+Rc=0.9*10^3
+Re=0.9*10^3
+//thevenin voltage
+Vt=(Vcc*R2)/(R1+R2)
+//thevenin resistance
+Rt=(R1*R2)/(R1+R2)
+//base current
+Ib=(Vt-Vbe)/(Rt+(1+hFE)*Re)
+//collector current
+Icq=hFE*Ib
+//emitter current
+Ie=Ib+Icq
+//emitter voltage
+Ve=Ie*Re
+//collector to emitter voltage
+Vceq=Vcc-(Icq*Rc)-(Ie*Re);
+Vce=[Vcc Vceq 0];
+//collector voltage
+Vc=Vce+Ve
+//to draw DC load line
+Ic1=Vcc/(Rc+Re)
+Ic=[0 Icq Ic1]
+printf("Q(%f,%f)\n",Vceq,Icq)
+plot2d(Vce, Ic)
+xlabel("Vce")
+ylabel("Ic")
 xtitle("DC load line for base bias circuit")
\ No newline at end of file