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| author | priyanka | 2015-06-24 15:03:17 +0530 |
|---|---|---|
| committer | priyanka | 2015-06-24 15:03:17 +0530 |
| commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
| tree | ab291cffc65280e58ac82470ba63fbcca7805165 /196/CH4/EX4.4 | |
| download | Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.gz Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.bz2 Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.zip | |
initial commit / add all books
Diffstat (limited to '196/CH4/EX4.4')
| -rwxr-xr-x | 196/CH4/EX4.4/example_4_4.sce | 20 | ||||
| -rwxr-xr-x | 196/CH4/EX4.4/result_4_4.txt | 9 |
2 files changed, 29 insertions, 0 deletions
diff --git a/196/CH4/EX4.4/example_4_4.sce b/196/CH4/EX4.4/example_4_4.sce new file mode 100755 index 000000000..ef851c973 --- /dev/null +++ b/196/CH4/EX4.4/example_4_4.sce @@ -0,0 +1,20 @@ +//Chapter 4
+//Example 4-4
+//DesignUsingVutAndVlt
+//Page 96
+clear;clc;
+//Given
+Vut = 12 ; Vlt = 8 ; //Upper and Lower Threshold Voltages
+Vsatp = 15 ; Vsatm = -15 ;// Saturation Voltages
+R = 10*10^3 ;//Choosing R
+//Design
+Vh = Vut - Vlt ; // Hysteresis Voltage
+Vctr = (Vut + Vlt)/2;//Center Voltage
+n = (Vsatp - Vsatm)/Vh ; // Resistor Factor
+Vref = Vctr / (1 + (1/n)); //Reference Voltage
+Resistance = n * R;
+printf ( "\n\n Hysteresis Voltage = %.4f V \n\n",Vh )
+printf ( "\n\n Center Voltage = %.4f V \n\n", Vctr )
+printf ( "\n\n Resistor Factor = %.4f \n\n" , n )
+printf ( "\n\n Reference Voltage = %.4f \n\n", Vref)
+printf ( "\n\n Feedback resistor = %.4f \n\n", Resistance)
\ No newline at end of file diff --git a/196/CH4/EX4.4/result_4_4.txt b/196/CH4/EX4.4/result_4_4.txt new file mode 100755 index 000000000..535c6eed7 --- /dev/null +++ b/196/CH4/EX4.4/result_4_4.txt @@ -0,0 +1,9 @@ +Hysteresis Voltage = 4.0000 V
+
+Center Voltage = 10.0000 V
+
+Resistor Factor = 7.5000
+
+Reference Voltage = 8.8235
+
+Feedback resistor = 75000.0000
\ No newline at end of file |