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| author | priyanka | 2015-06-24 15:03:17 +0530 |
|---|---|---|
| committer | priyanka | 2015-06-24 15:03:17 +0530 |
| commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
| tree | ab291cffc65280e58ac82470ba63fbcca7805165 /1133/CH8/EX8.16/Example8_16.sce | |
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Diffstat (limited to '1133/CH8/EX8.16/Example8_16.sce')
| -rwxr-xr-x | 1133/CH8/EX8.16/Example8_16.sce | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/1133/CH8/EX8.16/Example8_16.sce b/1133/CH8/EX8.16/Example8_16.sce new file mode 100755 index 000000000..1cf369a93 --- /dev/null +++ b/1133/CH8/EX8.16/Example8_16.sce @@ -0,0 +1,31 @@ +//Example 8.16
+clc
+disp("The fig 8.36 shows the connections for 74LS191 to get desire operation. We can design the combinational circuit for such counter from the truth table shown below.")
+disp("")
+disp("Q3 Q2 Q1 Q0 Y")
+disp("0 0 0 0 0")
+disp("0 0 0 1 0")
+disp("0 0 1 0 0")
+disp("0 0 1 1 1")
+disp("0 1 0 0 1")
+disp("0 1 0 1 1")
+disp("0 1 1 0 1")
+disp("0 1 1 1 1")
+disp("1 0 0 0 1")
+disp("1 0 0 1 1")
+disp("1 0 1 0 1")
+disp("1 0 1 1 1")
+disp("1 1 0 0 1")
+disp("1 1 0 1 1")
+disp("1 1 1 0 0")
+disp("1 1 1 1 0")
+disp("")
+disp("K=map simplification")
+disp(" Q1''Q0'' Q1''Q0 Q1Q0 Q1Q0''")
+disp("Q3''Q2'' 0 0 1 0")
+disp("Q3''Q2 1 1 1 1")
+disp("Q3Q2 1 1 0 0")
+disp("Q3Q2'' 1 1 1 1")
+disp("")
+disp("Therefore, PL'' = Y = Q3''Q1Q0 + Q3''Q2 + Q3Q1'' + Q3Q2''")
+disp("After switch ON, if the counter output is other than 1101 through 0011, the PL'' goes low and count 1101 is loaded in the counter. The counter is then decremented on the occurrence of clock pulses. When counter reaches 0010, the PL'' again goes low and count 1101 is loaded in the counter")
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