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| author | priyanka | 2015-06-24 15:03:17 +0530 |
|---|---|---|
| committer | priyanka | 2015-06-24 15:03:17 +0530 |
| commit | b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b (patch) | |
| tree | ab291cffc65280e58ac82470ba63fbcca7805165 /1133/CH8 | |
| download | Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.gz Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.tar.bz2 Scilab-TBC-Uploads-b1f5c3f8d6671b4331cef1dcebdf63b7a43a3a2b.zip | |
initial commit / add all books
Diffstat (limited to '1133/CH8')
77 files changed, 596 insertions, 0 deletions
diff --git a/1133/CH8/EX8.1/Example8_1.sce b/1133/CH8/EX8.1/Example8_1.sce new file mode 100755 index 000000000..68c3ce21a --- /dev/null +++ b/1133/CH8/EX8.1/Example8_1.sce @@ -0,0 +1,3 @@ +//Example 8.1
+clc
+disp("After 12 pulses, the count will be (1100)_2, i.e. 12 in decimal.")
diff --git a/1133/CH8/EX8.10/Example8_10.sce b/1133/CH8/EX8.10/Example8_10.sce new file mode 100755 index 000000000..822ad3f74 --- /dev/null +++ b/1133/CH8/EX8.10/Example8_10.sce @@ -0,0 +1,4 @@ +//Example 8.10
+clc
+disp("Since 128 = 16 x 8, a divide-by-16 counter followed by a divide-by-8 counter will become a divide-by-128 counter. IC 7493 is a 4-bit binary counter (i.e. mod-16 or divide-by-16), therefore, two IC packages will be required.")
+disp("The circuit diagram is as shown in fig.8.18.")
diff --git a/1133/CH8/EX8.10/Fig8_18.xcos b/1133/CH8/EX8.10/Fig8_18.xcos new file mode 100755 index 000000000..02cd2873d --- /dev/null +++ b/1133/CH8/EX8.10/Fig8_18.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_18"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-6ebd"/><mxCell id="-29456bc4:13f0f33c35c:-6ebe" parent="-29456bc4:13f0f33c35c:-6ebd"/><BasicBlock angle="90" id="-29456bc4:13f0f33c35c:-6ea0" interfaceFunctionName="FROM" parent="-29456bc4:13f0f33c35c:-6ebe" simulationFunctionName="from" simulationFunctionType="DEFAULT" style="FROM;rotation=90;flip=false;mirror=false"><ScilabString as="exprs" height="1" width="1"><data column="0" line="0" value="CP"/></ScilabString><ScilabDouble as="realParameters" height="0" width="0"/><ScilabDouble as="integerParameters" height="0" width="0"/><Array as="objectsParameters" scilabClass="ScilabList"><ScilabString height="1" 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\ No newline at end of file diff --git a/1133/CH8/EX8.11/Example8_11.sce b/1133/CH8/EX8.11/Example8_11.sce new file mode 100755 index 000000000..f10bcf820 --- /dev/null +++ b/1133/CH8/EX8.11/Example8_11.sce @@ -0,0 +1,4 @@ +//Example 8.11
+clc
+disp("Since 78 = 13 x 6, we have to use 7493 as mod-a3 and 7492 as mod-6 counters. For the mod-13 counter QD, QC and QA outputs of 7493 ans ANDed and used to clear the count when the count reaches 1101. For the mod-6 counter, clock is applied to B input of 7492.")
+disp(" The circuit diagram is as shown in the fig. 8.19")
diff --git a/1133/CH8/EX8.11/Fig8_19.xcos b/1133/CH8/EX8.11/Fig8_19.xcos new file mode 100755 index 000000000..72fb8e148 --- /dev/null +++ b/1133/CH8/EX8.11/Fig8_19.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_19"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-6c86"/><mxCell id="-29456bc4:13f0f33c35c:-6c87" parent="-29456bc4:13f0f33c35c:-6c86"/><SuperBlock angle="90" id="-29456bc4:13f0f33c35c:-6c78" parent="-29456bc4:13f0f33c35c:-6c87" simulationFunctionType="DEFAULT" style="SUPER_f;rotation=90;flip=false;mirror=false"><SuperBlockDiagram as="child" background="-1" title=""><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><Array as="context" scilabClass="String[]"><add value=""/></Array><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-6c76"/><mxCell id="-29456bc4:13f0f33c35c:-6c77" parent="-29456bc4:13f0f33c35c:-6c76"/><ExplicitInBlock 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y="-8.0"/></ExplicitInputPort></ExplicitLink></root></mxGraphModel><mxCell as="defaultParent" id="-29456bc4:13f0f33c35c:-6c87" parent="-29456bc4:13f0f33c35c:-6c86"/></XcosDiagram>
\ No newline at end of file diff --git a/1133/CH8/EX8.12/Example8_12.sce b/1133/CH8/EX8.12/Example8_12.sce new file mode 100755 index 000000000..bc5388826 --- /dev/null +++ b/1133/CH8/EX8.12/Example8_12.sce @@ -0,0 +1,3 @@ +//Example 8.12
+clc
+disp("The fig.8.20 shows divided-by-6 (MOD 6) counter using 7493. As shown in the fig.8.20, the clock is applied to inout B of IC 7493 and the output count sequenceis taken from QD, QC and QB. As soon as count is 110, i.e. QD and QC = 1, the internal NAND gate output goes low and it resets the counter.")
diff --git a/1133/CH8/EX8.12/Fig8_20.xcos b/1133/CH8/EX8.12/Fig8_20.xcos new file mode 100755 index 000000000..b5c55a854 --- /dev/null +++ b/1133/CH8/EX8.12/Fig8_20.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_20"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-6a6a"/><mxCell id="-29456bc4:13f0f33c35c:-6a6b" parent="-29456bc4:13f0f33c35c:-6a6a"/><BasicBlock id="-29456bc4:13f0f33c35c:-6a44" interfaceFunctionName="GOTO" parent="-29456bc4:13f0f33c35c:-6a6b" simulationFunctionName="goto" simulationFunctionType="DEFAULT" style="GOTO;rotation=0;flip=false;mirror=false"><ScilabString as="exprs" height="2" width="1"><data column="0" line="0" value="QD"/><data column="0" line="1" value="1"/></ScilabString><ScilabDouble as="realParameters" height="0" width="0"/><ScilabDouble as="integerParameters" height="1" width="1"><data column="0" line="0" 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\ No newline at end of file diff --git a/1133/CH8/EX8.13/Example8_13.sce b/1133/CH8/EX8.13/Example8_13.sce new file mode 100755 index 000000000..ddbdddad1 --- /dev/null +++ b/1133/CH8/EX8.13/Example8_13.sce @@ -0,0 +1,10 @@ +//Example 8.13
+clc
+disp("For a synchronous counter the total delay that must be allowed between input clock pulses is equal to flip-flop t_pd + AND gate t_pd. Thus T_clock >= 50 + 20 = 70 ns and so the counter has")
+fm=(1/(70*10^-9))*10^-6
+format(5)
+disp(fm," f_max(in MHz) =")
+disp("We know that MOD-16 ripple counter used four flip-flops. With flip-flop t_pd = 50 ns, the f_max for ripple counter can be given as,")
+fma=(1/(4*(50*10^-9)))*10^-6
+format(3)
+disp(fma," f_max(ripple)(in MHz) =")
diff --git a/1133/CH8/EX8.14/Example8_14.sce b/1133/CH8/EX8.14/Example8_14.sce new file mode 100755 index 000000000..69f706af8 --- /dev/null +++ b/1133/CH8/EX8.14/Example8_14.sce @@ -0,0 +1,3 @@ +//Example 8.14
+clc
+disp("IC 74191 is a 4-bit counter. Thus it is MOD-16 counter. However, we require MOD-11 counter. The difference between 16 and 11 is 5. Hence 5 steps must be skipped from the full modulus sequence. This can be achieved by presetting counter to value 5. Each time when counter recycles it starts counting from 5 upto 16 on each full cycle. Therefore, each full cycle of the counter consists of 11 states.")
diff --git a/1133/CH8/EX8.15/Example8_15.sce b/1133/CH8/EX8.15/Example8_15.sce new file mode 100755 index 000000000..facf53120 --- /dev/null +++ b/1133/CH8/EX8.15/Example8_15.sce @@ -0,0 +1,3 @@ +//Example 8.15
+clc
+disp("IC 74191 is a 4-bit counter. Thus it is MOD-16 counter. However, we require MOD-10 counter. The difference between 16 and 10 is 6. Hence 6 steps must be skipped from the full modulus sequence. This can be achieved by presetting counter to value 6. Each time when counter recycles it starts counting from 6 upto 16 on each full cycle. Therefore, each full cycle of the counter consists of 10 states.")
diff --git a/1133/CH8/EX8.15/Example8_15_fig.xcos b/1133/CH8/EX8.15/Example8_15_fig.xcos new file mode 100755 index 000000000..d4d9a04e4 --- /dev/null +++ b/1133/CH8/EX8.15/Example8_15_fig.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Example8_15_fig"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-655c"/><mxCell id="-29456bc4:13f0f33c35c:-655d" parent="-29456bc4:13f0f33c35c:-655c"/><SuperBlock angle="90" id="-29456bc4:13f0f33c35c:-655a" parent="-29456bc4:13f0f33c35c:-655d" simulationFunctionType="DEFAULT" style="SUPER_f;rotation=90;flip=false;mirror=false"><SuperBlockDiagram as="child" background="-1" title=""><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><Array as="context" scilabClass="String[]"><add value=""/></Array><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-6558"/><mxCell id="-29456bc4:13f0f33c35c:-6559" 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height="1" width="1"><data column="0" line="0" value="74191"/></ScilabString><mxGeometry as="geometry" height="20.0" width="40.0" x="270.0" y="160.0"/></TextBlock></root></mxGraphModel><mxCell as="defaultParent" id="-29456bc4:13f0f33c35c:-655d" parent="-29456bc4:13f0f33c35c:-655c"/></XcosDiagram>
\ No newline at end of file diff --git a/1133/CH8/EX8.16/Example8_16.sce b/1133/CH8/EX8.16/Example8_16.sce new file mode 100755 index 000000000..1cf369a93 --- /dev/null +++ b/1133/CH8/EX8.16/Example8_16.sce @@ -0,0 +1,31 @@ +//Example 8.16
+clc
+disp("The fig 8.36 shows the connections for 74LS191 to get desire operation. We can design the combinational circuit for such counter from the truth table shown below.")
+disp("")
+disp("Q3 Q2 Q1 Q0 Y")
+disp("0 0 0 0 0")
+disp("0 0 0 1 0")
+disp("0 0 1 0 0")
+disp("0 0 1 1 1")
+disp("0 1 0 0 1")
+disp("0 1 0 1 1")
+disp("0 1 1 0 1")
+disp("0 1 1 1 1")
+disp("1 0 0 0 1")
+disp("1 0 0 1 1")
+disp("1 0 1 0 1")
+disp("1 0 1 1 1")
+disp("1 1 0 0 1")
+disp("1 1 0 1 1")
+disp("1 1 1 0 0")
+disp("1 1 1 1 0")
+disp("")
+disp("K=map simplification")
+disp(" Q1''Q0'' Q1''Q0 Q1Q0 Q1Q0''")
+disp("Q3''Q2'' 0 0 1 0")
+disp("Q3''Q2 1 1 1 1")
+disp("Q3Q2 1 1 0 0")
+disp("Q3Q2'' 1 1 1 1")
+disp("")
+disp("Therefore, PL'' = Y = Q3''Q1Q0 + Q3''Q2 + Q3Q1'' + Q3Q2''")
+disp("After switch ON, if the counter output is other than 1101 through 0011, the PL'' goes low and count 1101 is loaded in the counter. The counter is then decremented on the occurrence of clock pulses. When counter reaches 0010, the PL'' again goes low and count 1101 is loaded in the counter")
diff --git a/1133/CH8/EX8.16/Fig8_36.xcos b/1133/CH8/EX8.16/Fig8_36.xcos new file mode 100755 index 000000000..bacb2c3da --- /dev/null +++ b/1133/CH8/EX8.16/Fig8_36.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_36"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-64d6"/><mxCell id="-29456bc4:13f0f33c35c:-64d7" parent="-29456bc4:13f0f33c35c:-64d6"/><BasicBlock angle="90" id="-29456bc4:13f0f33c35c:-64a6" interfaceFunctionName="FROM" parent="-29456bc4:13f0f33c35c:-64d7" simulationFunctionName="from" simulationFunctionType="DEFAULT" style="FROM;rotation=90;flip=false;mirror=false"><ScilabString as="exprs" height="1" width="1"><data column="0" line="0" value="1"/></ScilabString><ScilabDouble as="realParameters" height="0" width="0"/><ScilabDouble as="integerParameters" height="0" width="0"/><Array as="objectsParameters" scilabClass="ScilabList"><ScilabString height="1" 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\ No newline at end of file diff --git a/1133/CH8/EX8.17/Example8_17.sce b/1133/CH8/EX8.17/Example8_17.sce new file mode 100755 index 000000000..41c69de69 --- /dev/null +++ b/1133/CH8/EX8.17/Example8_17.sce @@ -0,0 +1,3 @@ +//Example 8.17
+clc
+disp("The IC 74191 is a 4-bit binary counter, therefore f_out = f_CLK / 16 in up and down counter mode. If f_CLK = 500 Hz and f_out = 50 Hz we need mod 10 (500/50) counter. The fig. 8.39 shows the mod-10 counter using IC 74191")
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\ No newline at end of file diff --git a/1133/CH8/EX8.18/Example8_18.sce b/1133/CH8/EX8.18/Example8_18.sce new file mode 100755 index 000000000..2b19c5099 --- /dev/null +++ b/1133/CH8/EX8.18/Example8_18.sce @@ -0,0 +1,31 @@ +//Example 8.18
+clc
+disp("The fig shows the connections for 74LS191 to get desire operation. We can design the combinational circuit for such counter from the truth table shown below.")
+disp("")
+disp("Q3 Q2 Q1 Q0 Y")
+disp("0 0 0 0 0")
+disp("0 0 0 1 0")
+disp("0 0 1 0 0")
+disp("0 0 1 1 1")
+disp("0 1 0 0 1")
+disp("0 1 0 1 1")
+disp("0 1 1 0 1")
+disp("0 1 1 1 1")
+disp("1 0 0 0 1")
+disp("1 0 0 1 1")
+disp("1 0 1 0 1")
+disp("1 0 1 1 1")
+disp("1 1 0 0 1")
+disp("1 1 0 1 1")
+disp("1 1 1 0 1")
+disp("1 1 1 1 0")
+disp("")
+disp("K=map simplification")
+disp(" Q1''Q0'' Q1''Q0 Q1Q0 Q1Q0''")
+disp("Q3''Q2'' 0 0 1 0")
+disp("Q3''Q2 1 1 1 1")
+disp("Q3Q2 1 1 0 1")
+disp("Q3Q2'' 1 1 1 1")
+disp("")
+disp("Therefore, PL'' = Y = Q3''Q1Q0 + Q3''Q2 + Q3Q1'' + Q3Q2'' + Q2Q1Q0''")
+disp("After switch ON, if the counter output is other than 1110 through 0011, the PL'' goes low and count 1110 is loaded in the counter. The counter is then decremented on the occurrence of clock pulses. When counter reaches 0010, the PL'' again goes low and count 1110 is loaded in the counter")
diff --git a/1133/CH8/EX8.18/Example8_18_afig.xcos b/1133/CH8/EX8.18/Example8_18_afig.xcos new file mode 100755 index 000000000..9e3c33901 --- /dev/null +++ b/1133/CH8/EX8.18/Example8_18_afig.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Example8_18_afig"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-5ea6"/><mxCell id="-29456bc4:13f0f33c35c:-5ea7" parent="-29456bc4:13f0f33c35c:-5ea6"/><BasicBlock angle="90" id="-29456bc4:13f0f33c35c:-5ea4" interfaceFunctionName="FROM" parent="-29456bc4:13f0f33c35c:-5ea7" simulationFunctionName="from" simulationFunctionType="DEFAULT" style="FROM;rotation=90;flip=false;mirror=false"><ScilabString as="exprs" height="1" width="1"><data column="0" line="0" value="1"/></ScilabString><ScilabDouble as="realParameters" height="0" width="0"/><ScilabDouble as="integerParameters" height="0" width="0"/><Array as="objectsParameters" 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\ No newline at end of file diff --git a/1133/CH8/EX8.19/Example8_19.sce b/1133/CH8/EX8.19/Example8_19.sce new file mode 100755 index 000000000..6b06f7089 --- /dev/null +++ b/1133/CH8/EX8.19/Example8_19.sce @@ -0,0 +1,3 @@ +//Example 8.19
+clc
+disp("IC 74191 is a 4-bit binary counter. Thus it divides the input frequency by 16. However, we can design MOD-N counter using IC 74191. For MOD-N counter the output frequency will be f_out = f_in / N. Thus by changing N we can change the output frequency. The fig.8.40 shows the programmable frequncy divider using IC 74191.")
diff --git a/1133/CH8/EX8.19/Fig8_40.xcos b/1133/CH8/EX8.19/Fig8_40.xcos new file mode 100755 index 000000000..600f45f74 --- /dev/null +++ b/1133/CH8/EX8.19/Fig8_40.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_40"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-5ac9"/><mxCell id="-29456bc4:13f0f33c35c:-5aca" parent="-29456bc4:13f0f33c35c:-5ac9"/><TextBlock id="-29456bc4:13f0f33c35c:-5a39" parent="-29456bc4:13f0f33c35c:-5aca" simulationFunctionType="DEFAULT" style="TEXT_f;fontStyle=1;flip=false;mirror=false" value="Count = (16 - N)"><ScilabString as="exprs" height="1" width="3"><data column="0" line="0" value="Count = (16 - N)"/><data column="1" line="0" value="2"/><data column="2" line="0" value="1"/></ScilabString><ScilabString as="realParameters" height="1" width="1"><data column="0" line="0" value="Count = (16 - N)"/></ScilabString><mxGeometry as="geometry" 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ordering="2" parent="-29456bc4:13f0f33c35c:-588b" style="ExplicitInputPort;align=center;verticalAlign=top;spacing=10.0;rotation=90;flip=false;mirror=false"><mxGeometry as="geometry" height="8.0" width="8.0" x="46.0" y="-8.0"/></ExplicitInputPort></ExplicitLink></root></mxGraphModel><mxCell as="defaultParent" id="-29456bc4:13f0f33c35c:-5aca" parent="-29456bc4:13f0f33c35c:-5ac9"/></XcosDiagram>
\ No newline at end of file diff --git a/1133/CH8/EX8.2/Example8_2.sce b/1133/CH8/EX8.2/Example8_2.sce new file mode 100755 index 000000000..9cd739cc2 --- /dev/null +++ b/1133/CH8/EX8.2/Example8_2.sce @@ -0,0 +1,7 @@ +//Example 8.2
+clc
+a=dec2bin(144)
+disp(a,"decimal (144) =")
+disp("Since counter is a 5-bit counter, it resets after 2^5 = 32 clock pulses.")
+disp("Dividing 144 by 32 we get quotient 2 and remainder 6")
+disp("Therefore, counter resets four times and then it counts remaining 16 clock pulses. Thus, the count will be binary (110000), i.e., 16 in decimal")
diff --git a/1133/CH8/EX8.20/Example8_20.sce b/1133/CH8/EX8.20/Example8_20.sce new file mode 100755 index 000000000..208b70bb9 --- /dev/null +++ b/1133/CH8/EX8.20/Example8_20.sce @@ -0,0 +1,33 @@ +//Example 8.20
+clc
+disp("Fig. 8.41 shows Dividing-by-2 for up counting")
+disp("Divide-by-2 is a mod-2 counter. Since, after preset above counter goes through 2 states 1110 and 1111, it is a mod-2 counter. Thus, above circuit is a divide-by-2 counter for up counting mode.")
+disp("")
+disp("Divide-by-5 for down counting mode:")
+disp("")
+disp("Q3 Q2 Q1 Q0 Y")
+disp("0 0 0 0 0")
+disp("0 0 0 1 0")
+disp("0 0 1 0 0")
+disp("0 0 1 1 0")
+disp("0 1 0 0 0")
+disp("0 1 0 1 0")
+disp("0 1 1 0 0")
+disp("0 1 1 1 0")
+disp("1 0 0 0 0")
+disp("1 0 0 1 0")
+disp("1 0 1 0 0")
+disp("1 0 1 1 1")
+disp("1 1 0 0 1")
+disp("1 1 0 1 1")
+disp("1 1 1 0 1")
+disp("1 1 1 1 1")
+disp("")
+disp("K=map simplification")
+disp(" Q1''Q0'' Q1''Q0 Q1Q0 Q1Q0''")
+disp("Q3''Q2'' 0 0 0 0")
+disp("Q3''Q2 0 0 0 0")
+disp("Q3Q2 1 1 1 1")
+disp("Q3Q2'' 0 0 1 0")
+disp("")
+disp("Therefore, Y = Q3Q2 + Q3Q1Q0")
diff --git a/1133/CH8/EX8.20/Fig8_41.xcos b/1133/CH8/EX8.20/Fig8_41.xcos new file mode 100755 index 000000000..047548f6a --- /dev/null +++ b/1133/CH8/EX8.20/Fig8_41.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_41"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-5689"/><mxCell id="-29456bc4:13f0f33c35c:-568a" parent="-29456bc4:13f0f33c35c:-5689"/><GroundBlock dependsOnU="1" id="-29456bc4:13f0f33c35c:-5684" interfaceFunctionName="Ground" parent="-29456bc4:13f0f33c35c:-568a" simulationFunctionName="Ground" simulationFunctionType="DEFAULT" style="Ground;flip=false;mirror=false"><ScilabString as="exprs" height="1" width="1"><data column="0" line="0" value=""/></ScilabString><ScilabDouble as="realParameters" height="0" width="0"/><ScilabDouble as="integerParameters" height="0" width="0"/><Array as="objectsParameters" scilabClass="ScilabList"/><ScilabDouble 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\ No newline at end of file diff --git a/1133/CH8/EX8.21/Example8_21.sce b/1133/CH8/EX8.21/Example8_21.sce new file mode 100755 index 000000000..6821c59be --- /dev/null +++ b/1133/CH8/EX8.21/Example8_21.sce @@ -0,0 +1,3 @@ +//Example 8.21
+clc
+disp("IC 74191 is a 4-bit counter. Thus it is MOD-16 counter. However, we require MOD-9 counter. The difference between 16 and 9 is 7. Hence 7 steps must be skipped from the full modulus sequence. This can be achieved by presetting counter to value 7. Each time when counter recycles it starts counting from 7 upto 16 on each full cycle. Therefore, each full cycle of the counter consists of 9 states.")
diff --git a/1133/CH8/EX8.21/Example8_21_fig.xcos b/1133/CH8/EX8.21/Example8_21_fig.xcos new file mode 100755 index 000000000..75f9ea99f --- /dev/null +++ b/1133/CH8/EX8.21/Example8_21_fig.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Example8_21_fig"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-5423"/><mxCell id="-29456bc4:13f0f33c35c:-5424" parent="-29456bc4:13f0f33c35c:-5423"/><SuperBlock angle="90" id="-29456bc4:13f0f33c35c:-5421" parent="-29456bc4:13f0f33c35c:-5424" simulationFunctionType="DEFAULT" style="SUPER_f;rotation=90;flip=false;mirror=false"><SuperBlockDiagram as="child" background="-1" title="Untitled - 10:45:18 PM"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><Array as="context" scilabClass="String[]"><add value=""/></Array><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-541f"/><mxCell id="-29456bc4:13f0f33c35c:-5420" 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height="1" width="1"><data column="0" line="0" value="74191"/></ScilabString><mxGeometry as="geometry" height="20.0" width="40.0" x="270.0" y="160.0"/></TextBlock></root></mxGraphModel><mxCell as="defaultParent" id="-29456bc4:13f0f33c35c:-5424" parent="-29456bc4:13f0f33c35c:-5423"/></XcosDiagram>
\ No newline at end of file diff --git a/1133/CH8/EX8.22/Example8_22.sce b/1133/CH8/EX8.22/Example8_22.sce new file mode 100755 index 000000000..38dcaf1c8 --- /dev/null +++ b/1133/CH8/EX8.22/Example8_22.sce @@ -0,0 +1,9 @@ +//Example 8.22
+clc
+disp("Clock frequency = 256 kHz")
+disp("Output frequency = 2 kHz")
+format(4)
+mn=256/2
+disp(mn,"Therefore, Mod number = n =")
+disp("Therefore, Counter is MOD-128 counter")
+disp("Mod-128 counter can count the numbers from 0 to 127.")
diff --git a/1133/CH8/EX8.23/Example8_23.sce b/1133/CH8/EX8.23/Example8_23.sce new file mode 100755 index 000000000..aa2f09cd7 --- /dev/null +++ b/1133/CH8/EX8.23/Example8_23.sce @@ -0,0 +1,10 @@ +//Example 8.23
+clc
+disp("Internal structure of 7490 ripple counter IC is as shown in fig. 8.50")
+disp("")
+disp("We know that, one IC can work as mod-10 (BCD) counter. Therefore, we need two ICs. The counter will go through states 0-19 and should be reset on state 20. i.e.")
+disp(" QD QC QB QA QD QC QB QA")
+disp(" 0 0 1 0 0 0 0 0")
+disp(" 7490(2) 7490(1)")
+disp("")
+disp("The diagram of divide-by-20 counter using IC 7490 is as shown in fig.8.51")
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\ No newline at end of file diff --git a/1133/CH8/EX8.24/Example8_24.sce b/1133/CH8/EX8.24/Example8_24.sce new file mode 100755 index 000000000..5d8f96597 --- /dev/null +++ b/1133/CH8/EX8.24/Example8_24.sce @@ -0,0 +1,3 @@ +//Example 8.24
+clc
+disp("IC 7490 is a decade counter. When two such ICs are cascaded, it becomes a divide-by-100 counter. To get a divide-by-96 counter, the counter is reset as soon as it becomes 1001 0110. The diagram is shown in fig.8.52.")
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y="16.0"/></ExplicitInputPort></ExplicitLink></root></mxGraphModel><mxCell as="defaultParent" id="-29456bc4:13f0f33c35c:-4d33" parent="-29456bc4:13f0f33c35c:-4d32"/></XcosDiagram>
\ No newline at end of file diff --git a/1133/CH8/EX8.25/Example8_25.sce b/1133/CH8/EX8.25/Example8_25.sce new file mode 100755 index 000000000..54a7e9603 --- /dev/null +++ b/1133/CH8/EX8.25/Example8_25.sce @@ -0,0 +1,3 @@ +//Example 8.25.
+clc
+disp("IC 7490 is a decade counter. Whentwo such ICs are cascaded, it becomes a divide-by-100 counter. To get a divide-by-93 counter, the counter is reset as soon as ot becomes 1001 0011. The diagram is as shown in fig.8.53")
diff --git a/1133/CH8/EX8.25/Fig8_53.xcos b/1133/CH8/EX8.25/Fig8_53.xcos new file mode 100755 index 000000000..d83cc0862 --- /dev/null +++ b/1133/CH8/EX8.25/Fig8_53.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_53"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-40b7372e:13f1efed6d3:-7e3a"/><mxCell id="-40b7372e:13f1efed6d3:-7e3b" parent="-40b7372e:13f1efed6d3:-7e3a"/><BasicBlock angle="90" id="-40b7372e:13f1efed6d3:-7e38" interfaceFunctionName="FROM" parent="-40b7372e:13f1efed6d3:-7e3b" simulationFunctionName="from" simulationFunctionType="DEFAULT" style="FROM;rotation=90;flip=false;mirror=false"><ScilabString as="exprs" height="1" width="1"><data column="0" line="0" value="CP"/></ScilabString><ScilabDouble as="realParameters" height="0" width="0"/><ScilabDouble as="integerParameters" height="0" width="0"/><Array as="objectsParameters" scilabClass="ScilabList"><ScilabString height="1" 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\ No newline at end of file diff --git a/1133/CH8/EX8.26/Example8_26.sce b/1133/CH8/EX8.26/Example8_26.sce new file mode 100755 index 000000000..d8ecdacff --- /dev/null +++ b/1133/CH8/EX8.26/Example8_26.sce @@ -0,0 +1,3 @@ +//Example 8.26
+clc
+disp("IC 7490 is a decade counter. When two such ICs are cascaded, it becomes a divide-by-100 counter. To get a divide by 78 or MOD-78 counter, the counter is reset as soon as ot becomes 0111 1000 as shown in fig.8.54")
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y="-8.0"/></ExplicitInputPort></ExplicitLink></root></mxGraphModel><mxCell as="defaultParent" id="-40b7372e:13f1efed6d3:-7ce1" parent="-40b7372e:13f1efed6d3:-7ce0"/></XcosDiagram>
\ No newline at end of file diff --git a/1133/CH8/EX8.28/Example8_28.sce b/1133/CH8/EX8.28/Example8_28.sce new file mode 100755 index 000000000..d21a5f8c4 --- /dev/null +++ b/1133/CH8/EX8.28/Example8_28.sce @@ -0,0 +1,15 @@ +//Example 8.28
+clc
+disp("If the QD output is connected to A input of 7490 IC and, input clock is applied to B input divide by ten square wave is obtained at output QA.")
+disp("Clock Outputs")
+disp(" QA QD QC QB")
+disp(" 0 L L L L")
+disp(" 1 L L L H")
+disp(" 2 L L H L")
+disp(" 3 L L H H")
+disp(" 4 L H L L")
+disp(" 5 H L L L")
+disp(" 6 H L L H")
+disp(" 7 H L H L")
+disp(" 8 H L H H")
+disp(" 9 H H L L")
diff --git a/1133/CH8/EX8.28/Fig8_55.xcos b/1133/CH8/EX8.28/Fig8_55.xcos new file mode 100755 index 000000000..4280ac304 --- /dev/null +++ b/1133/CH8/EX8.28/Fig8_55.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_55"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-40b7372e:13f1efed6d3:-7bb1"/><mxCell id="-40b7372e:13f1efed6d3:-7bb2" parent="-40b7372e:13f1efed6d3:-7bb1"/><BasicBlock angle="90" id="-40b7372e:13f1efed6d3:-7baf" interfaceFunctionName="FROM" parent="-40b7372e:13f1efed6d3:-7bb2" simulationFunctionName="from" simulationFunctionType="DEFAULT" style="FROM;rotation=90;flip=false;mirror=false"><ScilabString as="exprs" height="1" width="1"><data column="0" line="0" value="CLK"/></ScilabString><ScilabDouble as="realParameters" height="0" width="0"/><ScilabDouble as="integerParameters" height="0" width="0"/><Array as="objectsParameters" scilabClass="ScilabList"><ScilabString height="1" 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\ No newline at end of file diff --git a/1133/CH8/EX8.30/Example8_30.sce b/1133/CH8/EX8.30/Example8_30.sce new file mode 100755 index 000000000..38d3dd8eb --- /dev/null +++ b/1133/CH8/EX8.30/Example8_30.sce @@ -0,0 +1,87 @@ +//example 10.9
+
+clc;
+clear;
+close;
+c = [0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0]; //taking the values for a mod -6 counter
+q = [0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0];
+a = [0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0];
+b = [0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0];
+y1=q;
+y2=a;
+y3=b;
+y11p=1;
+y22p=1;
+y33p=1;
+y44p=1;
+cp=1;
+yf1p=1;
+for i=1:25 // making arrays to draw the output
+ if y1(i)==1 then
+ for o=1:100
+ y11(y11p)=1;
+ y11p=y11p+1;
+ end
+ else
+ for o=1:100
+ y11(y11p)=0;
+ y11p=y11p+1;
+ end
+
+end
+if y2(i)==1 then
+ for o=1:100
+ y21(y22p)=1;
+ y22p=y22p+1;
+ end
+ else
+ for o=1:100
+ y21(y22p)=0;
+ y22p=y22p+1;
+ end
+
+end
+if y3(i)==1 then
+ for o=1:100
+ y31(y33p)=1;
+ y33p=y33p+1;
+ end
+ else
+ for o=1:100
+ y31(y33p)=0;
+ y33p=y33p+1;
+ end
+
+end
+if c(i)==1 then
+ for o=1:100
+ c1(cp)=1;
+ cp=cp+1;
+ end
+ else
+ for o=1:100
+ c1(cp)=0;
+ cp=cp+1;
+ end
+end
+
+end
+z=[2 2];
+subplot(4,1,1); //ploting the out put
+title('Timing Diagram');
+plot(c1);
+plot(z);
+ylabel('QA');
+subplot(4,1,2);
+plot(y11);
+ylabel('QB');
+plot(z);
+subplot(4,1,3);
+plot(y21);
+ylabel('QC');
+plot(z);
+subplot(4,1,4);
+plot(z);
+ylabel('QD');
+plot(y31);
+disp("The counter goes through states 0000 (Decimal 0) to 1011 (Decimal 11), i.e., through 12 states. Thus it is a MOD-12 counter.")
diff --git a/1133/CH8/EX8.30/Fig8_61_exmp8_30.jpeg b/1133/CH8/EX8.30/Fig8_61_exmp8_30.jpeg Binary files differnew file mode 100755 index 000000000..f7fa684a2 --- /dev/null +++ b/1133/CH8/EX8.30/Fig8_61_exmp8_30.jpeg diff --git a/1133/CH8/EX8.31/Example8_31.sce b/1133/CH8/EX8.31/Example8_31.sce new file mode 100755 index 000000000..b3bd8a5a3 --- /dev/null +++ b/1133/CH8/EX8.31/Example8_31.sce @@ -0,0 +1,3 @@ +//Example 8.31
+clc
+disp("The fig. 8.63 shows the cascaded connection of 4-bit binary counters. Let us see the circuit operation. The counter IC1 operates as a counter for countion in the UP direction since CLEAR = LOAD = 1. When the count reaches the maximum value (1111) its RC (Ripple Carry Output) goes HIGH which makes P and T (Enable) inputs of IC2 HIGH for one clock cycle advancing its output by 1 and making Q outputs of IC1, 0 at the next clock cycle. After this clock cycle P = T = 0 for IC2 and IC1 will go on counting the pulses. When the outputs of IC1 and IC2 both reach the maximum count, RC outputs of both of these ICs will go HIGH. This will make P = T of IC3 HIGH and therefore, in the next clock cycle IC3 count will be incremented and simultaneously IC1 and IC2 will be cleared. This way the counting will continue.")
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\ No newline at end of file diff --git a/1133/CH8/EX8.32/Example8_32.sce b/1133/CH8/EX8.32/Example8_32.sce new file mode 100755 index 000000000..643f04818 --- /dev/null +++ b/1133/CH8/EX8.32/Example8_32.sce @@ -0,0 +1,5 @@ +//Example 8.32
+clc
+disp("Cascading four 74161 (each 4-bit) counters we get 16 (4 x 4) bit counter as shown in fig 8.63.")
+disp("Therefore, we get 2^16 = 65,536 modulus counter")
+disp("However, we require divide-by-40,000 counter. The difference between 65,536 and 40,000 is 25,536, which is the number of states those must be skipped from the full modulus sequence. This can be achieved by presetting the counting from 25,536 upto 65,536 on each ful cycle. Therefore, each full cycle of the counter consists of 40,000 states.")
diff --git a/1133/CH8/EX8.33/Example8_33.sce b/1133/CH8/EX8.33/Example8_33.sce new file mode 100755 index 000000000..877afefa6 --- /dev/null +++ b/1133/CH8/EX8.33/Example8_33.sce @@ -0,0 +1,5 @@ +//Example 8.33
+clc
+disp("Although the 74X163 is a modulo-16 counter, it can be made to count in a modulus less than 16 by using the CLR'' or LD'' input to shorten the normal counting sequence. The fig.8.69 shows circuit connections for modulo-11 counter. Here, load input is activated upon activation of RCO (ripple-carry-output). Since load input is adjusted to state 5, counter counts from 5 to 15 and then starts at 5 again, for a total of 11 states per counting cycle.")
+disp("")
+disp("We can also design modulo-11 counter using CLR'' input as shown in fig.8.70. here, NAND gate is used to detect state 10 and force the next state to 0. A 2-input gate is used to detect state 10 (binary 1010) by connecting Q1 and Q3 to the inputs of the NAND gate.")
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\ No newline at end of file diff --git a/1133/CH8/EX8.34/Example8_34.sce b/1133/CH8/EX8.34/Example8_34.sce new file mode 100755 index 000000000..27107ced2 --- /dev/null +++ b/1133/CH8/EX8.34/Example8_34.sce @@ -0,0 +1,3 @@ +//Example 8.34
+clc
+disp("An excess-3 decimal counter should start counting from count 3 (binary 0011) and count upto count 12 (binary 1100). Starting count is adjusted by loading 0011 at load inputs. To recycle count from 1100 to 0011, Q3 and Q2 output are connected as inputs for 2-input NAND gate. Thus, NAND gate detects state 1100 and forces 0011 to be loaded as the next state.")
diff --git a/1133/CH8/EX8.34/Fig8_71_exmp8_34.xcos b/1133/CH8/EX8.34/Fig8_71_exmp8_34.xcos new file mode 100755 index 000000000..a3c3bff09 --- /dev/null +++ b/1133/CH8/EX8.34/Fig8_71_exmp8_34.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_71(exmp8_34)"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-40b7372e:13f1efed6d3:-7273"/><mxCell id="-40b7372e:13f1efed6d3:-7274" parent="-40b7372e:13f1efed6d3:-7273"/><SuperBlock id="-40b7372e:13f1efed6d3:-7271" parent="-40b7372e:13f1efed6d3:-7274" simulationFunctionType="DEFAULT" style="SUPER_f;flip=false;mirror=false"><SuperBlockDiagram as="child" background="-1" title="Untitled - 7:42:22 PM"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><Array as="context" scilabClass="String[]"><add value=""/></Array><mxGraphModel as="model"><root><mxCell id="-40b7372e:13f1efed6d3:-726f"/><mxCell id="-40b7372e:13f1efed6d3:-7270" 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\ No newline at end of file diff --git a/1133/CH8/EX8.35/Example8_35.sce b/1133/CH8/EX8.35/Example8_35.sce new file mode 100755 index 000000000..5fe15892b --- /dev/null +++ b/1133/CH8/EX8.35/Example8_35.sce @@ -0,0 +1,3 @@ +//Example 8.35
+clc
+disp("A binary counter with a modulus greater than 16 can be built by cascading 74X163s. When counters are cascaded, CLK, CLR'' and LD'' of all the 74X163s are connected in parallel, so that all of them count or are cleared or loaded at the same time. The RCO signal drives the ENT input of the next counter. The fig.8.73 shows modulo-60 counter. To have a modulo 60 count we need at least 6-bit counter, thus two 74X163s are cascaded. Counter is designed to count from 196 to 255. The MAXCNT signal detects the state 255 and stops the counter util GO'' is asserted. When GO'' is asserted the counter is reloaded with 196 (binary 1100 0100) and counts upto 255. To enable counting, CNTEN is connected to the ENP inputs in parallel. A NAND gate assets RELOAD'' to get back to state 196 only if GO'' is asserted and the counter is in state 255.")
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\ No newline at end of file diff --git a/1133/CH8/EX8.36/Example8_36.sce b/1133/CH8/EX8.36/Example8_36.sce new file mode 100755 index 000000000..f67116ff9 --- /dev/null +++ b/1133/CH8/EX8.36/Example8_36.sce @@ -0,0 +1,4 @@ +//Example 8.36
+clc
+disp("A binary counter may be combined with a decoder to obtain a set of 1-out-of-M coded signals, where one signal is asserted in each count state. This is useful when counters are used to control a set of devices, where a different devices is enabled in each counter state.")
+disp("The fig.8.74 shows how a 74X163 connected as a modulo-8 counter can be combined with a 74X138 3-8 decoder to provide eight signals, each one representing a counter state.")
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\ No newline at end of file diff --git a/1133/CH8/EX8.37/Example8_37.sce b/1133/CH8/EX8.37/Example8_37.sce new file mode 100755 index 000000000..43172b305 --- /dev/null +++ b/1133/CH8/EX8.37/Example8_37.sce @@ -0,0 +1,56 @@ +//Example 8.37
+clc
+disp("Excitation table")
+disp("Present State Next State Flip-flop Inputs")
+disp("QD QC QB QA Q_D+1 Q_C+1 Q_B+1 Q_A+1 JK_D JK_C JK_B JK_A")
+disp("0 0 0 0 0 0 0 1 0 0 0 1")
+disp("0 0 0 1 0 0 1 0 0 0 1 1")
+disp("0 0 1 0 0 0 1 1 0 0 0 1")
+disp("0 0 1 1 0 1 0 0 0 1 1 1")
+disp("0 1 0 0 0 1 0 1 0 0 0 1")
+disp("0 1 0 1 0 1 1 0 0 0 1 1")
+disp("0 1 1 0 0 1 1 1 0 0 0 1")
+disp("0 1 1 1 1 0 0 0 1 1 1 1")
+disp("1 0 0 0 1 0 0 1 0 0 0 1")
+disp("1 0 0 1 0 0 0 0 1 0 0 1")
+disp("1 0 1 0 X X X X X X X 1")
+disp("1 0 1 1 X X X X X X X 1")
+disp("1 1 0 0 X X X X X X X X")
+disp("1 1 0 1 X X X X X X X X")
+disp("1 1 1 0 X X X X X X X X")
+disp("1 1 1 1 X X X X X X X X")
+disp("")
+disp("K-map Simplification")
+disp(" For JK_D")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 0 0 0 0")
+disp("QD''QC 0 0 1 0")
+disp("QDQC X X X X")
+disp("QDQC'' 0 1 X X")
+disp("JK_D = QA QD + QA QB QC")
+disp("")
+disp(" For JK_C")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 0 0 1 0")
+disp("QD''QC 0 0 1 0")
+disp("QDQC X X X X")
+disp("QDQC'' 0 0 X X")
+disp("JK_C = QA QB")
+disp("")
+disp(" For JK_B")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 0 1 1 0")
+disp("QD''QC 0 1 1 0")
+disp("QDQC X X X X")
+disp("QDQC'' 0 0 X X")
+disp("JK_B = QA QD''")
+disp("")
+disp(" For JK_A")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 1 1 1 1")
+disp("QD''QC 1 1 1 1")
+disp("QDQC X X X X")
+disp("QDQC'' 1 1 X X")
+disp("JK_A = 1")
+disp("")
+disp("Fig shows the logic diagram for the synchronous decade counter using JK flip-flop")
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id="6ae06dbb:13f28693611:-79c1" ordering="1" parent="6ae06dbb:13f28693611:-7a3b" style="ExplicitInputPort;align=left;verticalAlign=middle;spacing=10.0;rotation=0;flip=false;mirror=false" value=""><mxGeometry as="geometry" height="8.0" width="8.0" x="-8.0" y="6.0"/></ExplicitInputPort></ExplicitLink></root></mxGraphModel><mxCell as="defaultParent" id="6ae06dbb:13f28693611:-7d2a" parent="6ae06dbb:13f28693611:-7d29"/></XcosDiagram>
\ No newline at end of file diff --git a/1133/CH8/EX8.38/Example8_38.sce b/1133/CH8/EX8.38/Example8_38.sce new file mode 100755 index 000000000..f6b8bcb77 --- /dev/null +++ b/1133/CH8/EX8.38/Example8_38.sce @@ -0,0 +1,48 @@ +//Example 8.38
+clc
+disp("Excitation table")
+disp(" Input Present State Next State Flip-flop Inputs")
+disp("UP/DOWN'' QC QB QA Q_C+1 Q_B+1 Q_A+1 JK_C JK_B JK_A")
+disp(" UD")
+disp(" 0 0 0 0 1 1 1 1 1 1")
+disp(" 0 0 0 1 0 0 0 0 0 1")
+disp(" 0 0 1 0 0 0 1 0 1 1")
+disp(" 0 0 1 1 0 1 0 0 0 1")
+disp(" 0 1 0 0 0 1 1 1 1 1")
+disp(" 0 1 0 1 1 0 0 0 0 1")
+disp(" 0 1 1 0 1 0 1 0 1 1")
+disp(" 0 1 1 1 1 1 0 0 0 1")
+disp(" 1 0 0 0 0 0 1 0 0 1")
+disp(" 1 0 0 1 0 1 0 0 1 1")
+disp(" 1 0 1 0 0 1 1 0 0 1")
+disp(" 1 0 1 1 1 0 0 1 1 1")
+disp(" 1 1 0 0 1 0 1 0 0 1")
+disp(" 1 1 0 1 1 1 0 0 1 1")
+disp(" 1 1 1 0 1 1 1 0 0 1")
+disp(" 1 1 1 1 0 0 0 1 1 1")
+disp("")
+disp("K-map Simplification")
+disp(" For JK_C")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 1 0 0 0")
+disp("QD''QC 1 0 0 0")
+disp("QDQC 0 0 1 0")
+disp("QDQC'' 0 0 1 0")
+disp("JK_C =UD'' QB'' QB'' + UD QB QA")
+disp("")
+disp(" For JK_B")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 1 0 0 1")
+disp("QD''QC 1 0 0 1")
+disp("QDQC 0 1 1 0")
+disp("QDQC'' 0 1 1 0")
+disp("TB =UD'' QA'' + UD QA")
+disp("")
+disp(" For JK_A")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 1 1 1 1")
+disp("QD''QC 1 1 1 1")
+disp("QDQC 1 1 1 1")
+disp("QDQC'' 1 1 1 1")
+disp("TA = 1")
+disp("")
diff --git a/1133/CH8/EX8.38/Fig8_90_exmp8_38.xcos b/1133/CH8/EX8.38/Fig8_90_exmp8_38.xcos new file mode 100755 index 000000000..4e3dca5b6 --- /dev/null +++ b/1133/CH8/EX8.38/Fig8_90_exmp8_38.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_90(exmp8_38)"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="6ae06dbb:13f28693611:-73eb"/><mxCell id="6ae06dbb:13f28693611:-73ec" parent="6ae06dbb:13f28693611:-73eb"/><BasicBlock dependsOnU="1" id="6ae06dbb:13f28693611:-73e9" interfaceFunctionName="LOGICAL_OP" ordering="17" parent="6ae06dbb:13f28693611:-73ec" simulationFunctionName="logicalop" simulationFunctionType="C_OR_FORTRAN" style="LOGICAL_OP;flip=false;mirror=false"><ScilabString as="exprs" height="4" width="1"><data column="0" line="0" value="2"/><data column="0" line="1" value="0"/><data column="0" line="2" value="1"/><data column="0" line="3" value="0"/></ScilabString><ScilabDouble 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id="6ae06dbb:13f28693611:-73e7" ordering="2" parent="6ae06dbb:13f28693611:-73e9" style="ExplicitInputPort;align=left;verticalAlign=middle;spacing=10.0;rotation=0;flip=false;mirror=false" value=""><mxGeometry as="geometry" height="8.0" width="8.0" x="-8.0" y="26.0"/></ExplicitInputPort><ExplicitOutputPort dataType="REAL_MATRIX" id="6ae06dbb:13f28693611:-73e6" ordering="1" parent="6ae06dbb:13f28693611:-73e9" style="ExplicitOutputPort;align=right;verticalAlign=middle;spacing=10.0;rotation=0;flip=false;mirror=false" value=""><mxGeometry as="geometry" height="8.0" width="8.0" x="40.0" y="16.0"/></ExplicitOutputPort><mxCell connectable="0" id="6ae06dbb:13f28693611:-73e9#identifier" parent="6ae06dbb:13f28693611:-73e9" style="noLabel=0;opacity=0;fontStyle=1" value="AND" vertex="1"><mxGeometry as="geometry" relative="1" x="0.5" y="1.1"/></mxCell><BasicBlock blockType="h" dependsOnU="1" id="6ae06dbb:13f28693611:-73d9" interfaceFunctionName="JKFLIPFLOP" parent="6ae06dbb:13f28693611:-73ec" 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\ No newline at end of file diff --git a/1133/CH8/EX8.39/Example8_39.sce b/1133/CH8/EX8.39/Example8_39.sce new file mode 100755 index 000000000..96b354a13 --- /dev/null +++ b/1133/CH8/EX8.39/Example8_39.sce @@ -0,0 +1,28 @@ +//Example 8.39
+clc
+disp("For mod-5 counter we require 3 flip-flops.")
+disp("Excitation table")
+disp(" Present State Next State Flip-flop Inputs")
+disp(" QC QB QA Q_A+1 Q_B+1 Q_C+1 T_A T_B T_C")
+disp(" 0 0 0 0 0 0 1 0 0 1")
+disp(" 1 0 0 1 0 1 0 0 1 1")
+disp(" 2 0 1 0 0 1 1 0 0 1")
+disp(" 3 0 1 1 1 0 0 1 1 1")
+disp(" 4 1 0 0 0 0 0 1 0 0")
+disp("")
+disp("K-map Simplification")
+disp(" QB''QC'' QB''QC QBQC QBQC''")
+disp("QA'' 0 0 1 0")
+disp("QA 1 X X X")
+disp("T_A = QA + QB QC")
+disp("")
+disp(" QB''QC'' QB''QC QBQC QBQC''")
+disp("QA'' 0 1 1 0")
+disp("QA 0 X X X")
+disp("T_B = QC")
+disp("")
+disp(" QB''QC'' QB''QC QBQC QBQC''")
+disp("QA'' 1 1 1 1")
+disp("QA 0 X X X")
+disp("T_C = QA''")
+disp("")
diff --git a/1133/CH8/EX8.39/Fig8_92_exmp8_39.xcos b/1133/CH8/EX8.39/Fig8_92_exmp8_39.xcos new file mode 100755 index 000000000..06526d4fc --- /dev/null +++ b/1133/CH8/EX8.39/Fig8_92_exmp8_39.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_92(exmp8_39)"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="6ae06dbb:13f28693611:-72d0"/><mxCell id="6ae06dbb:13f28693611:-72d1" parent="6ae06dbb:13f28693611:-72d0"/><SuperBlock id="6ae06dbb:13f28693611:-72b6" parent="6ae06dbb:13f28693611:-72d1" simulationFunctionType="DEFAULT" style="SUPER_f;flip=false;mirror=false"><SuperBlockDiagram as="child" background="-1" title=""><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><Array as="context" scilabClass="String[]"><add value=""/></Array><mxGraphModel as="model"><root><mxCell id="6ae06dbb:13f28693611:-72b2"/><mxCell id="6ae06dbb:13f28693611:-72b3" parent="6ae06dbb:13f28693611:-72b2"/><ExplicitInBlock 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\ No newline at end of file diff --git a/1133/CH8/EX8.4/Example8_4.sce b/1133/CH8/EX8.4/Example8_4.sce new file mode 100755 index 000000000..bbc8e867b --- /dev/null +++ b/1133/CH8/EX8.4/Example8_4.sce @@ -0,0 +1,3 @@ +//Example 8.4
+clc
+disp("When flip-flops are negatively edge triggered, the Q output of previous stage is connected to the clock input of the next stage. Fig. 8.5 shows 3-stage asynchronous counter with negative edge triggered flip-flops.")
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id="-29456bc4:13f0f33c35c:-7852" parent="-29456bc4:13f0f33c35c:-78c0" simulationFunctionType="DEFAULT" style="TEXT_f;fontStyle=1;fontSize=12;flip=false;mirror=false" value="A"><ScilabString as="exprs" height="1" width="3"><data column="0" line="0" value="A"/><data column="1" line="0" value="2"/><data column="2" line="0" value="1"/></ScilabString><ScilabString as="realParameters" height="1" width="1"><data column="0" line="0" value="A"/></ScilabString><mxGeometry as="geometry" height="20.0" width="20.0" x="130.0" y="130.0"/></TextBlock><TextBlock id="-29456bc4:13f0f33c35c:-7850" parent="-29456bc4:13f0f33c35c:-78c0" simulationFunctionType="DEFAULT" style="TEXT_f;fontStyle=1;fontSize=12;flip=false;mirror=false" value="B"><ScilabString as="exprs" height="1" width="3"><data column="0" line="0" value="B"/><data column="1" line="0" value="2"/><data column="2" line="0" value="1"/></ScilabString><ScilabString as="realParameters" height="1" width="1"><data column="0" line="0" value="B"/></ScilabString><mxGeometry as="geometry" height="20.0" width="20.0" x="290.0" y="130.0"/></TextBlock><TextBlock id="-29456bc4:13f0f33c35c:-784f" parent="-29456bc4:13f0f33c35c:-78c0" simulationFunctionType="DEFAULT" style="TEXT_f;fontStyle=1;fontSize=12;flip=false;mirror=false" value="C"><ScilabString as="exprs" height="1" width="3"><data column="0" line="0" value="C"/><data column="1" line="0" value="2"/><data column="2" line="0" value="1"/></ScilabString><ScilabString as="realParameters" height="1" width="1"><data column="0" line="0" value="C"/></ScilabString><mxGeometry as="geometry" height="20.0" width="20.0" x="460.0" y="130.0"/></TextBlock></root></mxGraphModel><mxCell as="defaultParent" id="-29456bc4:13f0f33c35c:-78c0" parent="-29456bc4:13f0f33c35c:-78bf"/></XcosDiagram>
\ No newline at end of file diff --git a/1133/CH8/EX8.40/Example8_40.sce b/1133/CH8/EX8.40/Example8_40.sce new file mode 100755 index 000000000..682f7fae3 --- /dev/null +++ b/1133/CH8/EX8.40/Example8_40.sce @@ -0,0 +1,35 @@ +//Example 8.40
+clc
+disp("Excitation table")
+disp("Present State Next State Flip-flop Inputs")
+disp(" QC QB A+ B+ J_A K_A J_B K_B")
+disp(" 0 0 1 1 1 X 1 X")
+disp(" 0 1 0 0 0 X X 1")
+disp(" 1 0 0 1 X 1 1 X")
+disp(" 1 1 1 0 X 0 X 1")
+disp("")
+disp("K-map Simplification")
+disp(" For J_A")
+disp(" B'' B")
+disp("A'' 1 0")
+disp("A X X")
+disp("J_A = B''")
+disp("")
+disp(" For K_A")
+disp(" B'' B")
+disp("A'' X X")
+disp("A 1 0")
+disp("K_A = B''")
+disp("")
+disp(" For J_B")
+disp(" B'' B")
+disp("A'' 1 X")
+disp("A 1 X")
+disp("J_B = 1")
+disp("")
+disp(" For K_B")
+disp(" B'' B")
+disp("A'' X 1")
+disp("A X 1")
+disp("K_B = 1")
+disp("")
diff --git a/1133/CH8/EX8.40/Fig8_94_exmp8_40.xcos b/1133/CH8/EX8.40/Fig8_94_exmp8_40.xcos new file mode 100755 index 000000000..2df2c54cf --- /dev/null +++ b/1133/CH8/EX8.40/Fig8_94_exmp8_40.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_94(exmp8_40)"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="6ae06dbb:13f28693611:-7184"/><mxCell id="6ae06dbb:13f28693611:-7185" parent="6ae06dbb:13f28693611:-7184"/><BasicBlock id="6ae06dbb:13f28693611:-7180" interfaceFunctionName="FROM" parent="6ae06dbb:13f28693611:-7185" simulationFunctionName="from" simulationFunctionType="DEFAULT" style="FROM;flip=false;mirror=false"><ScilabString as="exprs" height="1" width="1"><data column="0" line="0" value="CP"/></ScilabString><ScilabDouble as="realParameters" height="0" width="0"/><ScilabDouble as="integerParameters" height="0" width="0"/><Array as="objectsParameters" scilabClass="ScilabList"><ScilabString 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\ No newline at end of file diff --git a/1133/CH8/EX8.41/Example8_41.sce b/1133/CH8/EX8.41/Example8_41.sce new file mode 100755 index 000000000..ee337cb02 --- /dev/null +++ b/1133/CH8/EX8.41/Example8_41.sce @@ -0,0 +1,55 @@ +//Example 8.41
+clc
+disp("Mod-12 synchronous counter using D flip-flop :")
+disp("Let Number of flip-flop required = n")
+disp(" 2^n >= 12")
+disp(" n = 4")
+disp("Excitation table")
+disp("Present State Next State ")
+disp("QD QC QB QA Q_D+1 Q_C+1 Q_B+1 Q_A+1")
+disp("0 0 0 0 0 0 0 1")
+disp("0 0 0 1 0 0 1 0")
+disp("0 0 1 0 0 0 1 1")
+disp("0 0 1 1 0 1 0 0")
+disp("0 1 0 0 0 1 0 1")
+disp("0 1 0 1 0 1 1 0")
+disp("0 1 1 0 0 1 1 1")
+disp("0 1 1 1 1 0 0 0")
+disp("1 0 0 0 1 0 0 1")
+disp("1 0 0 1 1 0 1 0")
+disp("1 0 1 0 1 0 1 1")
+disp("1 0 1 1 0 0 0 0")
+disp("")
+disp("K-map Simplification")
+disp(" For D_A")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 1 0 0 1")
+disp("QD''QC 1 0 0 1")
+disp("QDQC X X X X")
+disp("QDQC'' 1 0 0 1")
+disp("D_A = QA''")
+disp("")
+disp(" For D_B")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 0 1 0 1")
+disp("QD''QC 0 1 0 1")
+disp("QDQC X X X X")
+disp("QDQC'' 0 1 0 1")
+disp("D_B = QB'' QaA + QA'' QB")
+disp(" = QA XOR QB")
+disp("")
+disp(" For D_C")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 0 0 1 0")
+disp("QD''QC 1 1 0 1")
+disp("QDQC X X X X")
+disp("QDQC'' 0 0 0 0")
+disp("D_C = QC QB'' + QC QA'' + QD'' QC'' QB QA")
+disp("")
+disp(" For D_D")
+disp(" QB''QA'' QB''QA QBQA QBQA''")
+disp("QD''QC'' 0 0 0 0")
+disp("QD''QC 0 0 1 0")
+disp("QDQC X X X X")
+disp("QDQC'' 1 1 0 1")
+disp("D_D = QD QB'' + QC QB QA + QD QA''")
diff --git a/1133/CH8/EX8.41/Fig8_95_exmp8_41.xcos b/1133/CH8/EX8.41/Fig8_95_exmp8_41.xcos new file mode 100755 index 000000000..b822c23c3 --- /dev/null +++ b/1133/CH8/EX8.41/Fig8_95_exmp8_41.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_95(exmp8_41)"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="6ae06dbb:13f28693611:-710d"/><mxCell id="6ae06dbb:13f28693611:-710e" parent="6ae06dbb:13f28693611:-710d"/><BasicBlock id="6ae06dbb:13f28693611:-7105" interfaceFunctionName="FROM" parent="6ae06dbb:13f28693611:-710e" simulationFunctionName="from" simulationFunctionType="DEFAULT" style="FROM;flip=false;mirror=false"><ScilabString as="exprs" height="1" width="1"><data column="0" line="0" value="CP"/></ScilabString><ScilabDouble as="realParameters" height="0" width="0"/><ScilabDouble as="integerParameters" height="0" width="0"/><Array as="objectsParameters" scilabClass="ScilabList"><ScilabString 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\ No newline at end of file diff --git a/1133/CH8/EX8.42/Example8_42.sce b/1133/CH8/EX8.42/Example8_42.sce new file mode 100755 index 000000000..75c4db6ff --- /dev/null +++ b/1133/CH8/EX8.42/Example8_42.sce @@ -0,0 +1,3 @@ +//Example 8.42
+clc
+disp("The fig.8.99 shows the circuit diagram for a 4-bit, 4-state ring counter with a single circulating 1. Here, 74X194 universal shift register is connected so that it normally preforms a left-shift. However, when RESET is asserted it loads 0001. Once RESET is negated, the 74194 shifts left on each clock pulse. The D_SL serial input is connected to the leftmost output (Q3 : MSB), so the next states are 0010, 0100, 1000, 0001, 0010, ..... Thus the counter counter visits four unique states before repeating.")
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\ No newline at end of file diff --git a/1133/CH8/EX8.44/Example8_44.sce b/1133/CH8/EX8.44/Example8_44.sce new file mode 100755 index 000000000..5d1e710ee --- /dev/null +++ b/1133/CH8/EX8.44/Example8_44.sce @@ -0,0 +1,16 @@ +//Example 8.44
+clc
+disp("Johnson counter is basically a twisted ring counter. The fig.8.104(a) shows the basic circuit for a Johnson counter. The table shows the states of a 4-bit Johnson counter.")
+disp("")
+disp("States of 4-bit Johnson counter")
+disp("State name Q3 Q2 Q1 Q0")
+disp(" S1 0 0 0 0")
+disp(" S2 0 0 0 1")
+disp(" S3 0 0 1 1")
+disp(" S4 0 1 1 1")
+disp(" S5 1 1 1 1")
+disp(" S6 1 1 1 0")
+disp(" S7 1 1 0 0")
+disp(" S8 1 0 0 0")
+disp("")
+disp("This counter can be modified to have self correcting Johnson counter as shown in fig.8.104(c). Here, the connections are made such that circuit oads 0001 as the next state whenever the current state is 0XX0.")
diff --git a/1133/CH8/EX8.44/Fig8_104_a_exmp8_44.xcos b/1133/CH8/EX8.44/Fig8_104_a_exmp8_44.xcos new file mode 100755 index 000000000..abe4d96d1 --- /dev/null +++ b/1133/CH8/EX8.44/Fig8_104_a_exmp8_44.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_104(a)(exmp8_44)"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-33fcee59:13f2f8c40db:-7ddc"/><mxCell id="-33fcee59:13f2f8c40db:-7ddd" parent="-33fcee59:13f2f8c40db:-7ddc"/><SuperBlock id="-33fcee59:13f2f8c40db:-7dda" parent="-33fcee59:13f2f8c40db:-7ddd" simulationFunctionType="DEFAULT" style="SUPER_f;flip=false;mirror=false"><SuperBlockDiagram as="child" background="-1" title="Untitled - 12:13:55 PM"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><Array as="context" scilabClass="String[]"><add value=""/></Array><mxGraphModel as="model"><root><mxCell id="-33fcee59:13f2f8c40db:-7dd8"/><mxCell id="-33fcee59:13f2f8c40db:-7dd9" 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\ No newline at end of file diff --git a/1133/CH8/EX8.45/Example8_45.sce b/1133/CH8/EX8.45/Example8_45.sce new file mode 100755 index 000000000..538ed253a --- /dev/null +++ b/1133/CH8/EX8.45/Example8_45.sce @@ -0,0 +1,3 @@ +//Example 8.45
+clc
+disp("Johnson counter will produce a modulus of 2xn where n is the number of stages (i.e. flip-flops) in the counter. Therefore, Mod 10 requires 5 flip-flops and Mod 16 requires 8 flip-flops.")
diff --git a/1133/CH8/EX8.5/Example8_5.sce b/1133/CH8/EX8.5/Example8_5.sce new file mode 100755 index 000000000..d1093b331 --- /dev/null +++ b/1133/CH8/EX8.5/Example8_5.sce @@ -0,0 +1,5 @@ +//example 8.5
+clc
+of=50/14
+format(5)
+disp(of,"Output frequency = 50 kHz / 14 =")
diff --git a/1133/CH8/EX8.6/Example8_6.sce b/1133/CH8/EX8.6/Example8_6.sce new file mode 100755 index 000000000..86d2fd1cb --- /dev/null +++ b/1133/CH8/EX8.6/Example8_6.sce @@ -0,0 +1,5 @@ +//Example 8.6
+clc
+disp("We know that MOD-32 uses five flip-flops. With t_pd = 50 ns, the f_max for ripple counter can be given as,")
+fm=(1/(250*10^-9))*10^-6
+disp(fm,"f_max(ripple) = ")
diff --git a/1133/CH8/EX8.8/Example8_8.sce b/1133/CH8/EX8.8/Example8_8.sce new file mode 100755 index 000000000..36a898226 --- /dev/null +++ b/1133/CH8/EX8.8/Example8_8.sce @@ -0,0 +1,4 @@ +//Example 8.8
+clc
+disp("The 4-bit counter needs four flip-flops. The circuit for 4-bit up/down ripple counter is similar to 3-bit up/down ripple counter except that 4-bit counter has one more flip-flop and its clock driving circuiting.")
+disp(" The fig. 8.14 shows the 4-bit up/down ripple counter.")
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id="-29456bc4:13f0f33c35c:-752e" ordering="1" parent="-29456bc4:13f0f33c35c:-752f" style="ExplicitInputPort;align=left;verticalAlign=middle;spacing=10.0;rotation=0;flip=false;mirror=false" value=""><mxGeometry as="geometry" height="8.0" width="8.0" x="-8.0" y="6.0"/></ExplicitInputPort></ExplicitLink></root></mxGraphModel><mxCell as="defaultParent" id="-29456bc4:13f0f33c35c:-7586" parent="-29456bc4:13f0f33c35c:-7585"/></XcosDiagram>
\ No newline at end of file diff --git a/1133/CH8/EX8.9/Example8_9.sce b/1133/CH8/EX8.9/Example8_9.sce new file mode 100755 index 000000000..5304dca8e --- /dev/null +++ b/1133/CH8/EX8.9/Example8_9.sce @@ -0,0 +1,5 @@ +//Example 8.9
+clc
+disp("Internal structure of 7492 is as shown in fig.8.16.")
+disp("")
+disp("The circuit diagram for divide-by-9 counter is as shown in fig.8.17.")
diff --git a/1133/CH8/EX8.9/Fig8_16.xcos b/1133/CH8/EX8.9/Fig8_16.xcos new file mode 100755 index 000000000..d8532991b --- /dev/null +++ b/1133/CH8/EX8.9/Fig8_16.xcos @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8"?><XcosDiagram background="-1" title="Fig8_16"><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-732e"/><mxCell id="-29456bc4:13f0f33c35c:-732f" parent="-29456bc4:13f0f33c35c:-732e"/><SuperBlock angle="270" id="-29456bc4:13f0f33c35c:-703a" parent="-29456bc4:13f0f33c35c:-732f" simulationFunctionType="DEFAULT" style="SUPER_f;rotation=270;flip=false;mirror=false"><SuperBlockDiagram as="child" background="-1" title=""><!--Xcos - 1.0 - scilab-5.4.1 - 20130329 1735--><Array as="context" scilabClass="String[]"><add value=""/></Array><mxGraphModel as="model"><root><mxCell id="-29456bc4:13f0f33c35c:-7038"/><mxCell id="-29456bc4:13f0f33c35c:-7039" parent="-29456bc4:13f0f33c35c:-7038"/><ExplicitInBlock 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