Samples of VHDL code added for testing

1 files changed, 15 insertions, 0 deletions

diff --git a/VHDL/myxor.vhdl b/VHDL/myxor.vhdl
new file mode 100644
index 0000000..b49f3ca
--- /dev/null
+++ b/VHDL/myxor.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity myxor is
+       port (a : in  std_logic_vector(0 downto 0); 
+             b : in  std_logic_vector(0 downto 0);
+             c : out std_logic_vector(0 downto 0)); 
+     end myxor;
+     
+     architecture rtl of myxor is
+     begin
+        
+        c <= a xor b;
+        
+     end rtl;