| Mode | Name | Size | |
|---|---|---|---|
| d--------- | Examples | 833 | logplain |
| d--------- | LPCSim | 129 | logplain |
| -rw-r--r-- | README.md | 0 | logplain |
| d--------- | analysisInserter | 41 | logplain |
| -rw-r--r-- | copyProject.sh | 537 | logplain |
| d--------- | forntEnd | 396 | logplain |
| d--------- | images | 911 | logplain |
| d--------- | kicadtoNgspice | 152 | logplain |
| d--------- | library | 1796 | logplain |
| d--------- | modelEditor | 1187 | logplain |
| d--------- | modelLibrary | 607 | logplain |
| d--------- | report / presentation | 39 | logplain |
| -rw-r--r-- | setPath.py | 50 | logplain |
| -rw-r--r-- | setPathInstall.py | 47 | logplain |
| d--------- | subcktEditor | 459 | logplain |
| d--------- | subcktLibrary | 664 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |