| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 26 | logplain |
| -rw-r--r-- | example_8.1-cache.bak | 2618 | logplain |
| -rw-r--r-- | example_8.1-cache.lib | 2616 | logplain |
| -rw-r--r-- | example_8.1.bak | 4336 | logplain |
| -rw-r--r-- | example_8.1.cir | 521 | logplain |
| -rw-r--r-- | example_8.1.cir.ckt | 307 | logplain |
| -rw-r--r-- | example_8.1.cir.out | 348 | logplain |
| -rw-r--r-- | example_8.1.pro | 1411 | logplain |
| -rw-r--r-- | example_8.1.proj | 28 | logplain |
| -rw-r--r-- | example_8.1.sch | 4336 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |