| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 26 | logplain |
| -rw-r--r-- | example_7.4-cache.bak | 2391 | logplain |
| -rw-r--r-- | example_7.4-cache.lib | 2391 | logplain |
| -rw-r--r-- | example_7.4.bak | 6263 | logplain |
| -rw-r--r-- | example_7.4.cir | 592 | logplain |
| -rw-r--r-- | example_7.4.cir.ckt | 394 | logplain |
| -rw-r--r-- | example_7.4.cir.out | 435 | logplain |
| -rw-r--r-- | example_7.4.pro | 1410 | logplain |
| -rw-r--r-- | example_7.4.proj | 30 | logplain |
| -rw-r--r-- | example_7.4.sch | 6263 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |