| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 26 | logplain |
| -rw-r--r-- | example_7.1-cache.bak | 1778 | logplain |
| -rw-r--r-- | example_7.1-cache.lib | 1778 | logplain |
| -rw-r--r-- | example_7.1.bak | 4116 | logplain |
| -rw-r--r-- | example_7.1.cir | 494 | logplain |
| -rw-r--r-- | example_7.1.cir.ckt | 341 | logplain |
| -rw-r--r-- | example_7.1.cir.out | 381 | logplain |
| -rw-r--r-- | example_7.1.pro | 1409 | logplain |
| -rw-r--r-- | example_7.1.proj | 30 | logplain |
| -rw-r--r-- | example_7.1.sch | 4112 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |