| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 26 | logplain |
| -rw-r--r-- | example_3.9-cache.bak | 2001 | logplain |
| -rw-r--r-- | example_3.9-cache.lib | 1999 | logplain |
| -rw-r--r-- | example_3.9.bak | 3559 | logplain |
| -rw-r--r-- | example_3.9.cir | 466 | logplain |
| -rw-r--r-- | example_3.9.cir.ckt | 302 | logplain |
| -rw-r--r-- | example_3.9.cir.out | 341 | logplain |
| -rw-r--r-- | example_3.9.pro | 1409 | logplain |
| -rw-r--r-- | example_3.9.proj | 30 | logplain |
| -rw-r--r-- | example_3.9.sch | 3966 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |